US 10049080

I'll verify current status and any 2026 appellate activity before summarizing.

Let me check the PTAB outcomes and any 2026 appellate activity for this specific patent.

Let me confirm the PTAB outcome and check for any appellate docket.

US Patent 10,049,080 — Analyst Summary

Interpretation note: I have treated the identifier literally as 10049080 (i.e., US 10,049,080 B2) and excluded near-miss numbers. All bibliographic data below is taken from the authoritative full text supplied in the prompt; litigation and PTAB data is from search results, cited by URL.

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1. Bibliographic data

Notes: US 10,049,080 is a continuation, not the original filing — the '080 and its sibling US 10,740,281 both trace priority to Dec. 22, 2011. The expiration date of 2031-12-22 therefore runs from the 2011 parent filing, not the 2017 continuation filing.

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2. Abstract (verbatim)

"A method is described that entails operating enabled cores of a multi-core processor such that both cores support respective software routines with a same instruction set, a first core being higher performance and consuming more power than a second core under a same set of applied supply voltage and operating frequency."

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3. Plain-language overview of the independent claims

The patent's central idea: put two groups of cores on one die that run the same instruction set (ISA), where the "small" cores are deliberately built from lower-power standard-cell libraries (narrower drive transistors) rather than by deleting logic. Because the ISA is identical, the OS sees no difference and needs no special software handling — but at the lowest performance/power states the chip can fall back to the low-power cores and save more energy than a conventional all-identical-core design.

Claim 1 — Multi-core processor (apparatus)

• A processor with a first plurality of cores and a second plurality of cores that support the same instruction set.
• The second group consumes less power at the same applied operating frequency and supply voltage as the first group.
• Power management hardware that, starting from a state in which both groups are enabled, disables all of the first group on a drop in demand below a threshold, without disabling any of the second group (i.e., the low-power cores are the last to be turned off).
• An operating system executing on the processor monitors demand for the processor and controls the power-management hardware based on that demand.

The final "operating system" element was the contested limitation in the PTAB proceedings (see §4) — petitioners argued the prior art's core-switching module/hypervisor qualified; the patent owner argued it did not.

Claim 9 — Method

• Operating a multi-core processor so that both groups execute the same instruction set, the second group being lower power at equal frequency/voltage.
• Disabling, with power-management hardware, from an enabled state, all of the first group on a drop in demand below a threshold without disabling any of the second group.
• An operating system executing on the processor monitors demand and controls the power-management hardware based on that demand.

Claim 17 — Non-transitory machine-readable medium

• A non-transitory machine-readable medium containing program code that, when processed by a machine, causes the method of claim 9 to be performed (same limitations: same-ISA asymmetric core groups, all-high-power-cores-off-on-demand-drop, OS-monitored demand control of the power-management hardware).

Representative dependent claims: narrower drive transistors in the second group (claims 2, 10, 18); lower power-consuming logic gates (3, 11, 19); lower maximum operating frequency for the second group (4, 12, 20); sequential disablement of remaining low-power cores down to a single core with frequency/voltage lowering (5, 13, 21); voltage/frequency raise on higher demand (6, 14, 22); first group at maximum operating frequency in the stated state (7, 15, 23); re-enablement of all high-power cores on a demand increase above the threshold (8, 16, 24).

The specification also discloses the design method (FIG. 8): one high-level VHDL/Verilog description → a single RTL netlist → synthesized twice using two different technology libraries (wide-transistor library for high-power cores, narrow-transistor library for low-power cores).

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4. Litigation and PTAB status (as found in search results)

PTAB — IPR2023-01333 (Mercedes-Benz USA, LLC et al. v. Daedalus Prime LLC), filed 2023-08-18, challenging claims 1–24; instituted 2024-02-13; art included Sutardja (US 2008/0288748), Mathieson (US 2011/0213950), Rychlik, Carmack; Final Written Decision, case terminated 2025-01-08, and an IPR certificate (kind code K1) issued 2025-04-21.
Sources: https://ipverse.greyb.com/ptab-web/cases/case-details/IPR2023-01333 ; https://portal.unifiedpatents.com/ptab/case/IPR2023-01333

PTAB — IPR2023-00567 (Samsung Electronics / Samsung Electronics America / Qualcomm et al., joined by Mercedes-Benz and others), effective date 2023-02-14 — listed by Google Patents as terminated by settlement.
https://portal.unifiedpatents.com/ptab/case/IPR2023-00567

District court complaints (all filed 2022-08-23 by Daedalus Prime):

• D. Del. 1:22-cv-01107 (Arrow Electronics et al.)
• D. Del. 1:22-cv-01108 (Mazda Motor et al.)
• D. Del. 1:22-cv-01109 (Mazda Motor et al.)
• E.D. Tex. 2:22-cv-00352 (Samsung / TSMC)

ITC Section 337 investigations: 337-TA-1332, 337-TA-1335, and 337-TA-3640. The '080 was one of six asserted patents (with US 8,775,833; 8,898,494; 9,575,895; 10,394,300; 10,705,588) in the ITC complaint filed 2022-08-23.
https://portal.unifiedpatents.com/litigation/International%20Trade%20Commission/case/337-TA-1332

Federal Circuit (CAFC) 2026 dockets: I did not find an identifiable Federal Circuit appeal docketed in 2026 that names US 10,049,080 specifically. My searches returned only unrelated 2026 Federal Circuit decisions (e.g., Apple v. ITC, Masimo; VideoLabs/Unified Patents). I cannot confirm or exclude a 2026 appeal without a direct Court of Appeals docket query, and I would flag this as unverified rather than report no appeal.

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5. Explicit uncertainties and caveats

1. Date discrepancy in the tooling. Your prompt states the current date is April 26, 2026, but the authoritative patent page in my context is timestamped 2026-09-23, and one search result references a "September 10, 2026" Law360 item about Arm Ltd. invalidating a Daedalus Prime chip patent. That Arm item may relate to a different patent in the same Daedalus Prime portfolio (the family is large), not necessarily to the '080. I have not assumed it applies to US 10,049,080.
2. PTAB outcome specifics. The record shows a Final Written Decision (terminated 2025-01-08) and an IPR certificate issued 2025-04-21 for the '080. Certificates of this type typically issue pursuant to 35 U.S.C. § 318(b) to cancel claims held unpatentable, which would suggest cancellation of at least some challenged claims — but I could not retrieve the operative FWD text confirming exactly which of claims 1–24 were cancelled. Do not state as fact that all claims were cancelled without pulling the certificate itself.
3. Live status. Google Patents still lists the '080 as "Active" with maintenance fees paid through the 8th year (event 2026-02-03) and anticipated expiration 2031-12-22. Maintenance-fee status and claim status can diverge after an IPR certificate; the two should be checked separately.
4. Assignee. "Daedalus Prime LLC" is the recorded current owner; the title table's "Current Assignee (the listed assignees may be inaccurate)" disclaimer on the source page is Google's standard boilerplate, not an indication of a defect in the assignment.

Bottom line: US 10,049,080 is an Intel-originated (now Daedalus Prime) continuation patent, priority 2011-12-22, issued 2018-08-14, covering a multi-core processor with same-ISA high-power and low-power core groups in which the low-power cores are the last to be powered down, under OS-directed demand monitoring. Its three independent claims (1, 9, 17) recite the same substantive limitations in apparatus, method, and non-transitory-medium form respectively.

I'll research the litigation history for US patent 10049080. Let me search multiple sources.

Let me dig into the district court cases and the PTAB proceedings, including their outcomes.

Let me get the outcomes of the district court cases and the PTAB final decisions.

Litigation Involving U.S. Patent No. 10,049,080 ("the '080 patent")

Patent: US 10,049,080 B2 — "Asymmetric performance multicore architecture with same instruction set architecture"
Inventors: Varghese George; Sanjeev S. Jahagirdar; Deborah T. Marr
Original assignee: Intel Corp. → Current assignee: Daedalus Prime LLC (assignment recorded June 6, 2022; effective June 3, 2022; REEL/FRAME 060392/0594)
Priority date: December 22, 2011 | Granted: August 14, 2018 | Anticipated expiration: December 22, 2031

The Google Patents "Family has litigation" record for the '080 patent lists nine proceedings. I have verified most of them and set out the details below. Note the '080 patent is one of a Daedalus Prime portfolio (typically including U.S. 8,775,833; 8,898,494; 9,575,895; 10,049,080; 10,394,300; 10,705,588) asserted together, so it appears in multi-patent campaigns.

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1. District Court Litigation

• Case Nos. 1–3 (D. Del.) each asserted six patents: U.S. 8,775,833; 8,898,494; 9,575,895; 10,049,080; 10,394,300; 10,705,588.
• The E.D. Tex. Samsung/TSMC action asserted eight patents including 10,049,080, plus 8,775,833, 8,898,494, 9,831,306, 10,319,812, 10,700,178, 11,251,281 and 10,705,588.
• Source (D. Del. 1:22-cv-01107 docket): https://www.docketalarm.com/cases/Delaware_District_Court/1--22-cv-01107/Daedalus_Prime_LLC_v._Arrow_Electronics_Inc._et_al/
• Source (D. Del. 1:22-cv-01108 complaint): https://www.docketalarm.com/cases/Delaware_District_Court/1--22-cv-01108/Daedalus_Prime_LLC_v._Mazda_Motor_Corporation_et_al/
• Source (E.D. Tex. 2:22-cv-00352 docket): https://www.courtlistener.com/docket/65340358/daedalus-prime-llc-v-samsung-electronics-co-ltd/

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2. U.S. International Trade Commission (Section 337) Investigations

Investigation No. 337-TA-1332 — "Certain Semiconductors and Devices and Products Containing the Same, Including Printed Circuit Boards, Automotive Parts, and Automobiles"

• Complainant: Daedalus Prime LLC (Bronxville, NY)
• Instituted respondents: Avnet, Inc.; Digi-Key Electronics; Mercedes-Benz Group AG; Mercedes-Benz AG; Mercedes-Benz USA, LLC; Mouser Electronics, Inc.; Newark; NXP Semiconductors N.V.; NXP USA, Inc.
• Not instituted (insufficient importation/sale allegations): Arrow Electronics; Future Electronics; Rochester Electronics; MediaTek Inc.; MediaTek USA; Visteon; Mazda Motor Corp.; Mazda North American Operations; Mazda Motor of America
• Filed: August 23, 2022 (DN 3637) | Instituted: October 6, 2022 (published 87 FR 62454, Oct. 14, 2022)
• Patents asserted: 8,775,833; 8,898,494; 9,575,895; 10,049,080 (claims 1–24); 10,394,300; 10,705,588
• Outcome: Terminated Feb. 27, 2023, after the ALJ's initial determination (Order No. 16, Jan. 30, 2023) terminating the investigation as to all named respondents based on withdrawal of the complaint; Commission declined review.
• Source: https://www.govinfo.gov/metadata/granule/FR-2022-10-14/2022-22288/mods.xml ; https://ipwatchdog.com/wp-content/uploads/2023/09/EDIS-Doc.-ID-[781870](/patent/781870).pdf

Investigation No. 337-TA-1335 — "Certain Integrated Circuits, Mobile Devices Containing the Same, and Components Thereof"

• Complainant: Daedalus Prime LLC
• Respondents: Samsung Electronics Co., Ltd.; Samsung Electronics America, Inc.; Qualcomm Inc. (OUII also a party)
• Filed: September 13, 2022 (supplement Oct. 12, 2022) | Instituted: October 13/19, 2022 (87 FR 63528, Oct. 19, 2022)
• Patents asserted: 8,775,833 (claims 1–5, 7, 13–18); 8,898,494 (claims 1, 3, 12, 14, 15); 10,049,080 (claims 1–8); 10,705,588 (claims 1–19)
• Outcome:
  • Samsung — terminated July 19, 2023 based on settlement (Order No. 39).
  • '080 and other claims — investigation terminated as to all asserted claims of the '494, '833 and '080 patents following withdrawal of the allegations (Orders 31, 32, 42, 49, 59; unreviewed June–Sept. 2023).
  • Qualcomm — investigation terminated in its entirety based on settlement; Commission vote April 11, 2024 (ID Order No. 84 granting joint motion to terminate).
• Source: https://www.federalregister.gov/documents/full_text/xml/2024/04/16/2024-08025.xml

ITC Investigation No. 337-TA-3640 (as listed on the Google Patents litigation record)

• The Google Patents page lists a second ITC matter for this patent family under case 337-TA-3640 (https://portal.unifiedpatents.com/litigation/International%20Trade%20Commission/case/337-TA-3640).
• I could not verify the parties, filing date, or outcome of this investigation from the sources retrieved. I am flagging it rather than assuming: I have no independent confirmation that a 337-TA-3640 investigation exists or that it involves the '080 patent. Treat this entry as unconfirmed.

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3. PTAB (Inter Partes Review) Proceedings

• IPR2023-00567 was filed against U.S. 10,049,080 (Petitioners later included Samsung; the petition was terminated as to Samsung, with a motion to join IPR2023-00567). Sources: Google Patents legal events for US10049080; Mercedes-Benz petition papers at https://ptacts.uspto.gov/ptacts/public-informations/petitions/[1554517](/patent/1554517)/
• IPR2023-01333 challenged all claims 1–24 of the '080 patent. Grounds included Sutardja (Ground 1), Sutardja + Rychlik (Ground 2), Sutardja + Carmack (Ground 3), Mathieson + Sutardja (Ground 4), and Mathieson + Sutardja + Rychlik (Ground 5). Sources: https://ipverse.greyb.com/ptab-web/cases/case-details/IPR2023-01333 ; Docket Alarm case file https://www.docketalarm.com/cases/PTAB/IPR2023-01333/
• Caveat on the IPR2023-01333 outcome: I confirmed the proceeding reached a Final Written Decision (Jan. 8, 2025) and that an inter partes review certificate issued April 21, 2025. I could not confirm from the retrieved sources which claims, if any, were held unpatentable or cancelled. The Google Patents record continues to list US10049080B2 as "Active." Do not assume total invalidation without checking the FWD and the K1 certificate directly.

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4. Related developments (not confirmed to involve the '080 patent)

• Arm Ltd. v. Daedalus Prime LLC, IPR2025-00207 — challenges U.S. Patent No. 8,984,228, not the '080 patent. News reports of an Arm PTAB win invalidating a Daedalus chip patent (Sept. 2026) most plausibly relate to that or another Daedalus patent, not the '080 patent. Source: Arm's IPR2025-00207 papers at https://ptacts.uspto.gov/ptacts/public-informations/petitions/[1556969](/patent/1556969)/
• Daedalus Prime LLC v. MediaTek Inc., 2:24-cv-00235 (E.D. Tex.) — terminated; Daedalus Prime LLC v. Google LLC, 7:25-cv-00313 (W.D. Tex.) and Daedalus Prime LLC v. Marvell Technology, Inc., 7:25-cv-00413 (W.D. Tex.) — pending. These were identified in the context of U.S. 8,984,228; I have not confirmed the '080 patent is asserted in them.
• Daedalus Prime LLC v. Xiaomi Communications Co., Ltd. et al. (UPC Hamburg; appeal UPC_CoA_183/2024) — a European Unitary Patent Court action by Daedalus Prime against Xiaomi/MediaTek; the patents at issue were not confirmed and this relates to EP counterparts, not the US '080 patent.
• The '080 patent is part of UPC/DE family litigation (Darts-IP family 46578386) per the Google Patents record.

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Summary

The '080 patent has been asserted in at least four U.S. district court actions (D. Del. 1:22-cv-01107, -01108 and -01109; E.D. Tex. 2:22-cv-00352), two ITC Section 337 investigations (337-TA-1332 and 337-TA-1335), and challenged in two PTAB inter partes reviews (IPR2023-00567 — settled; IPR2023-01333 — Final Written Decision and IPR certificate). All district court and ITC matters asserted the '080 patent as part of a multi-patent Daedalus Prime family, and all identified outcomes resolved by settlement, withdrawal, or stay rather than a litigated judgment on the '080 patent's merits — the exception being PTAB IPR2023-01333, which reached a Final Written Decision in January 2025.

Two items I could not verify and therefore do not assert as fact: (1) ITC investigation 337-TA-3640, listed on the Google Patents litigation record with no details obtainable; and (2) the substantive holding of the IPR2023-01333 Final Written Decision (which claims survived or were cancelled). I recommend pulling the actual FWD (Paper) and the K1 IPR certificate (PTO) if a definitive merits outcome is needed.

I'll start by pulling the proceedings list from the structured block and the patent's own legal-events record, then verify claim-level outcomes via web search.

Good — both proceedings are surfacing. Now I need the claim-level FWD outcome in IPR2023-01333.

Let me find the actual FWD text for IPR2023-01333.

Proceedings overview

Two AIA trial proceedings have been filed against US 10049080 — one settled before any final adjudication (IPR2023-00567), one ran all the way to a Final Written Decision and a § 318(b) certificate (IPR2023-01333); neither resulted in a cancelation I could positively verify from the sources retrieved, so this is a patent that was challenged hard and mostly bought out, not one that was invalidated and not one that was decisively "hardened" by a merits win.

Two threshold flags before anything else:

1. The structured "PTAB proceedings on file" block reports no AIA proceedings from ODP. That is contradicted by the patent's own record: the Google Patents legal-events table for US10049080 lists an IPR2023-00567 filing (2023-05-09) and an IPR2023-01333 filing (2023-09-26), plus an inter partes review certificate issued 2025-04-21 ("IPR CERTIFICATE; TRIAL NO. IPR2023-01333, AUG. 18, 2023 … ISSUED APR. 21, 2025"). The "Family has litigation" block likewise tags "PTAB case IPR2023-00567 filed (Settlement)" and "PTAB case IPR2023-01333 filed (Final Written Decision)." Treat the ODP "none" as an ingest gap, not as an absence of PTAB activity.
2. The single fact I could not nail down from public sources is the claim-level disposition of the IPR2023-01333 FWD (which claims, if any, were held unpatentable). I flag it as MUST-VERIFY below and tell you exactly which document resolves it. I am not going to guess a claim-level verdict.

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IPR2023-01333 — Mercedes-Benz USA, LLC, et al. v. Daedalus Prime LLC

(Most impactful: it is the only proceeding on this patent that produced a merits decision.)

• Type: Inter Partes Review
• Filed: 2023-08-18 (petition filed; structured litigation record logs the event 2023-09-26)
• Status: "PTAB case IPR2023-01333 filed (Final Written Decision)" (verbatim from the structured data). Plain English: instituted, tried, FWD issued; reported termination date 2025-01-08; § 318(b) certificate effective 2025-04-21.
• Real parties-in-interest: Mercedes-Benz USA, LLC; Mercedes-Benz Intellectual Property GmbH & Co. KG; Mercedes-Benz Group AG; Mercedes-Benz AG. Patent Owner: Daedalus Prime LLC (NPE; '080 patent acquired from Intel, assignment recorded 2022-06-06).
• Judge panel: Gregg Anderson, Thomas Giannetti, William Saindon (as reported by Docket Alarm; confirm against the FWD caption). Petitioner counsel: Hogan Lovells (Celine J. Crowson, Joseph J. Raffetto, Scott Hughes, Damon M. Lewis, Ryan Stephenson, Nicholas Rotz, Helen Trac). Patent Owner counsel: Ascenda Law Group (Tarek N. Fahmi, Jonathan Tsao). Experts: Dr. Horst (Mercedes) for Petitioner; Dr. Michael C. Brogioli (Rice University / Polymathic Consulting) for Patent Owner.
• Petition grounds: challenged all of claims 1–24 (independents: 1, 9, 17) under § 103 only:
  • Ground 1 — claims 1–4, 7–12, 15–20, 23–24 obvious over Sutardja (Ex. 1007; U.S. Pub. 2008/0288748, "Dynamic core switching," which incorporates Ex. 1008, Sutardja '785, U.S. Pub. 2007/0083785)
  • Ground 2 — claims 5–6, 13–14, 21–22 over Sutardja + Rychlik
  • Ground 3 — claims 7, 15, 23 over Sutardja + Carmack
  • Ground 4 — claims 1–4, 7–12, 15–20, 23–24 over Mathieson + Sutardja
  • Ground 5 — claims 5–6, 13–14, 21–22 over Mathieson + Sutardja + Rychlik
• Institution decision: 2024-02-13 — instituted as to all challenged claims and all five grounds (Institution Decision date per GreyB/ipverse; the Board's later FWD-series materials confirm institution as to "all challenged claims and all asserted grounds" in the parallel Mercedes/Daedalus trials).
• Procedural notes: Mercedes concurrently filed a contingent motion for joinder with Qualcomm's IPR2023-00567; Daedalus opposed it (PO Opposition filed 2023-09-15) arguing it was an improper conditional motion and that Mercedes had refused to be a true "understudy." The motion was mooted by the 2024-01 termination of IPR2023-00567. PO Response 2024-05-07; Petitioner objections to PO evidence 2024-05-14; Brogioli deposition 2024-07-31; PO and Petitioner requests for oral argument 2024-10-01; oral hearing 2024-11-13. The live disputes at hearing were narrow: whether Sutardja's "core switching module" is power management hardware (vs. software), whether Sutardja's/the Mathieson controller's control amounts to an operating system that "monitor[s] a demand … and control[s] the power management hardware," and whether Mathieson discloses the "same operating frequency and supply voltage / less power" limitation.
• Final Written Decision: issued 2025-01-08 (reported termination date). ⚠️ Claim-level verdict NOT verified. I retrieved the petition, PO Response, expert declarations, demonstratives, and hearing transcript, but not the FWD text itself. Do not assume a direction. Sibling context (same petitioner, same institution date 2024-02-13, same FWD date 2025-01-08): in IPR2023-01343 on US 8,898,494 the Board found the petitioner had not proven the challenged claims unpatentable, while in IPR2023-01344 on US 9,575,895 the Board found all challenged claims unpatentable — this petitioner/panel pairing is genuinely mixed, so the sibling results do not let you infer the '080 outcome.
• Settlement / termination: No settlement; tried to FWD.
• Appeal: No Federal Circuit appeal located in the sources retrieved. The § 318(b) certificate issued 2025-04-21, roughly 3.5 months after the FWD — consistent with no party appealing (the 63-day notice-of-appeal window from 2025-01-08 would have run about 2025-03-12).
• Defensive value: This is the only proceeding on the '080 patent that produced an adjudicated result, and the resulting certificate (effective 2025-04-21) is the operative document that tells you which claims remain enforceable. Pull it before you evaluate any infringement theory. If the certificate cancels claim 1, 9, or 17, any demand letter or complaint built on that independent claim is worthless; if it confirms them, you inherit a patent that already survived a five-ground obviousness attack on all 24 claims.

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IPR2023-00567 — Samsung Electronics Co., Ltd. / Qualcomm Incorporated v. Daedalus Prime LLC

• Type: Inter Partes Review
• Filed: 2023-02-14 (per Mercedes' mandatory notices; structured litigation record logs the event 2023-05-09)
• Status: "PTAB case IPR2023-00567 filed (Settlement)" (verbatim from the structured data). Plain English: terminated by joint motion under 35 U.S.C. § 317(a) / 37 C.F.R. § 42.74, with the settlement agreement filed as confidential Exhibit 1039 and kept separate from the patent file under § 42.74(c).
• Judge panel: Not identified in the sources retrieved.
• Petition grounds: Challenged the '080 patent; Mercedes' IPR2023-01333 petition describes itself as "substantively the same as the Qualcomm IPR petition … challenging the same claims, on the same grounds, and rel[ying] on the same prior art," and Mercedes relied on the Declaration of Dr. Trevor Mudge submitted in IPR2023-00567. So: claims 1–24, § 103, on the same Sutardja-family and Mathieson-family art that later appeared in IPR2023-01333. I did not retrieve the Qualcomm petition's ground-by-ground chart, so treat the "same grounds/same art" statement as Mercedes' characterization.
• Institution decision: Not confirmed. Institution was originally due 2023-09-15 (Board e-mail of 2023-04-28 listing DI deadlines). As of Daedalus' 2023-09-15 filing, "no institution decision ha[d] yet been reached." Docket Alarm's file naming for the termination papers ("…Motion_to_terminate_due_to_settlement_post_DI-21…") is suggestive of a post-institution posture, but I could not verify it. Flag as unverified.
• Final Written Decision: None — terminated before any merits decision.
• Settlement / termination: Samsung notified the Board of a settlement in principle on 2023-04-28 and asked for a 30-day POPR extension (unopposed by Daedalus), simultaneously abandoning a cluster of related Samsung IPRs against Daedalus patents (IPR2023-00547, -00550, -00617, -00659, -00660, -00661, -00727, -00753). The proceeding was terminated as to Samsung, leaving Qualcomm as the sole remaining petitioner. Qualcomm and Daedalus then reached their own settlement; the Board authorized a joint termination motion on 2024-01-08 and the Joint Motion to Terminate was filed 2024-01-11. Terms are confidential (Ex. 1039, business confidential). The parties represented that the settlement resolved the '080 dispute across this IPR, Daedalus Prime LLC v. Mazda Motor Corp. et al., No. 1:22-cv-1109 (D. Del.), and ITC Inv. No. 337-TA-1335, and that they "do not anticipate further litigation between them concerning the '080 Patent."
• Appeal: N/A (no FWD to appeal).
• Defensive value: This proceeding creates no estoppel and no claim-level precedent. Because it ended in settlement before any FWD, § 315(e)(2) estoppel never attached to Samsung or Qualcomm — a defendant that is a successor, customer, or privy of either is not boxed out of re-running this art (subject to the § 315(b) one-year bar and § 325 time bars in your own case). Antitrust/FRAND-flavored reading: the two largest asserted defendants bought peace; only the automotive/NXP cluster fought it out.

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Strategic summary

Claim status on US 10049080. Claims 1–24 (independents 1, 9, 17) were challenged in both IPRs. No claim has been affirmatively verified as canceled in any decision I retrieved, and no claim has been verified as sustained. The only merits decision is the IPR2023-01333 FWD of 2025-01-08, whose claim-level verdict I could not confirm; the resulting § 318(b) inter partes review certificate (effective 2025-04-21) is the controlling document and will state on its face which claims were canceled and which were confirmed. Until you read that certificate, any statement about surviving claims is speculation. The claims are also not untested in adversarial proceedings — every one of claims 1–24 was charted in two petitions and one full trial. Notably, Daedalus withdrew the asserted '080 claims from ITC Inv. No. 337-TA-1335 (337-TA-1336 settlement notice, Commission determination 2023-12-14; FR notice of 2024-04-16 terminating 337-TA-1335 as to Samsung and Qualcomm), and the parallel ITC action naming Mercedes/NXP, 337-TA-1332, was terminated based on complainant's withdrawal (Commission notice 2023-02-27) — an assertion posture that moved from ITC exclusion relief to settlements and, for Mercedes, to a PTAB merits fight.

Estoppel landscape. § 315(e)(2) estoppel attaches to a petitioner only after an FWD. So:

• Mercedes-Benz (all four RPIs) is estopped — as to the '080 patent — from raising in district court or the ITC any ground of § 102/§ 103 invalidity it raised or reasonably could have raised (the five Sutardja/Mathieson/Rychlik/Carmack combinations, and any art a skilled searcher would have found and used on those same claim limitations). That is a meaningful gift to co-defendants: the best-resourced automotive challenger has spent its shot.
• Samsung and Qualcomm are NOT estopped on the '080 patent (no FWD — settlement). But they are effectively out of the fight commercially, and any new petitioner faces the § 315(b) one-year bar running from service of a complaint asserting the '080 patent.
• Prior art that remains available to a new defendant: art outside the Sutardja '748/'785, Mathieson, Rychlik, and Carmack family; newly applied combinations of those references that could not reasonably have been raised; and any § 112 grounds (never raised — both petitions were pure § 103), subject to the IPR/PGR channeling rules.

Pattern signals. Daedalus Prime — a former Intel portfolio monetizer (assignment from Intel recorded 2022-06-06; patent expired/expiring 2031-12-22) — ran a coordinated multi-patent campaign: D. Del. suits 1:22-cv-01107/-01108/-01109, ITC 337-TA-1332 (Mercedes/Mazda/NXP/Arrow) and 337-TA-1335 (Samsung/Qualcomm), plus a further 2025/2026-era ITC investigation linked in the patent's litigation record (337-TA-3640 — I could not confirm whether the '080 is asserted there). On the other side, Mercedes-Benz filed a family of IPRs against Daedalus patents and is the only party that took the '080 to judgment, while Samsung filed nine IPRs against Daedalus patents and abandoned all of them in one settlement. No defensive aggregator (Unified Patents) is in the chain on this patent — the Unified Patents and Darts-IP references in the record are litigation-database attributions, not petitioner/party involvement. On the Patent Owner side, Daedalus litigates PTAB decisions aggressively where it loses: in the sibling '494 case it successfully defended before the Board (FWD 2025-01-08 finding no claim unpatentable), and its opponent, not it, sought Director Review.

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Recommended next steps

1. Pull the § 318(b) certificate first. It is the single document that converts all of the above into an answer. Get it from PTAB E2E (https://e2e.uspto.gov) for IPR2023-01333, and cross-check the certified copy attached to the '080 patent's file wrapper at USPTO Patent Center (https://patentcenter.uspto.gov). The date to look for is 2025-04-21; the paper will enumerate any canceled claims and incorporate by operation of the certificate any claim held patentable.
2. Pull the IPR2023-01333 Final Written Decision (2025-01-08) from PTAB E2E / the PTAB Decisions site and read the "Conclusion" paragraph. The FWD is public; the panel's caption will also confirm the APJ panel (reported as Anderson, Giannetti, Saindon) and the exact disposition. This is the paper to cite and quote to opposing counsel and to a court — not a summary.
3. Key filing for the trial record, if you need the arguments: Petitioner's Request for Oral Argument (2024-10-01) and Patent Owner's Request for Oral Argument (2024-10-01) frame the five grounds exactly as reproduced above (https://www.docketalarm.com/cases/PTAB/IPR2023-01333/Mercedes-Benz_USA_LLC_v._DAEDALUS_PRIME_LLC/). The hearing transcript is in the PTAB record (https://ptacts.uspto.gov/ptacts/public-informations/petitions/[1554517](/patent/1554517)).
4. If you are a defendant and the FWD canceled claims, link the FWD and the certificate, quote the disposition verbatim, and point out that a demand letter or complaint resting on a canceled independent claim (1, 9, or 17) is untenable. Note there is no CAFC appeal on the docket for IPR2023-01333, so there is no risk of the verdict being reversed out from under your defense.
5. If the FWD sustained the claims, price the residual risk accordingly: Mercedes is now estopped, and the remaining realistic attack surface is new art and § 112 — which means the strongest play may be a design-around or a licensing posture rather than another IPR. Check whether Daedalus has already licensed Samsung, Qualcomm, and TSMC (ITC 337-TA-1335/1336 settlements, 2023-12-14 and 2024-04-16); if the major AP/SoC suppliers are licensed, an end-product defendant may have an exhaustion or license defense that is cheaper than an IPR.
6. Do not over-read the settlement history. The absence of a cancelation after two challenges is not proof of a strong patent — it is proof that two well-funded challengers (Samsung, Qualcomm) preferred to settle, and the third (Mercedes) either lost or won on 2025-01-08 depending on the FWD. The certificate resolves which.

Verification status: proceeding numbers, parties, filing dates, panel, grounds, institution date, oral-argument date, FWD date, and settlement/termination events are sourced from the patent's own legal-events record, the Unified Patents litigation links in the structured block (https://portal.unifiedpatents.com/ptab/case/IPR2023-01333 and https://portal.unifiedpatents.com/ptab/case/IPR2023-00567), the PTAB file (https://ptacts.uspto.gov/ptacts/public-informations/petitions/1554517), Docket Alarm's PTAB dockets (https://www.docketalarm.com/cases/PTAB/IPR2023-00567/Samsung_Electronics_Co._Ltd._v._Daedalus_Prime_LLC/), GreyB/ipverse (https://ipverse.greyb.com/ptab-web/cases/case-details/IPR2023-01333), and the ITC's Federal Register notices (https://www.federalregister.gov/documents/full_text/xml/2024/04/16/2024-08025.xml). Unverified items, explicitly flagged: the claim-level FWD disposition and any resulting cancelations in IPR2023-01333; whether an institution decision issued in IPR2023-00567; and the APJ panel in IPR2023-00567.

I'll research the assignment chain, correspondent of record, and asserter status for US 10,049,080.

Let me dig into the assignment record details, correspondent, and who is behind Daedalus Prime.

Now let me pin down the specific reel/frame entries and the correspondent of record.

US 10,049,080 — Ownership Chain & NPE Pattern Analysis

Method note / limitation up front. I could not open the Assignment Center UI directly (it is a JavaScript search app that does not expose records to text retrieval). The reel/frame data below is taken from (a) the Google Patents legal-events block supplied in the authoritative full text — which gives Reel/Frame 060392/0594, recorded 2022-06-06, effective 2022-06-03 — and (b) cross-corroborating records for sibling patents in the same Intel→Daedalus recording block, plus court filings that quote the assignment itself. I was not able to retrieve the correspondent-of-record name for this patent; I flag that as an explicit gap rather than guess (see NPE signal 3).

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Inventors

Pattern notes. All three are career Intel power-management/architecture personnel and all three assigned to Intel (see next section). There is no inventor-side anomaly in the sense you asked about: nothing in the record shows inventors departing Intel near filing or holding personal rights that were later sold — the patent vested in Intel and stayed with Intel for ~10.5 years. The unusual feature here is on the corporate side, not the inventor side: a seasoned, decade-old asset (priority 2011-12-22) was swept into a ~250-asset bulk transfer to a licensing entity in 2022, not a fresh-out-of-prosecution sale. The inventors' equity has no bearing on the assertion chain; Daedalus Prime asserts as Intel's successor-in-interest, not as an inventor-held portfolio.

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Original assignee

• Intel Corporation (Delaware corporation; 2200 Mission College Blvd., Santa Clara, CA 95054) is the assignee named on the face of US 10,049,080 B2 and the original assignee of record.
• Business: Intel is a fab-owning semiconductor operating company — it manufactures and sells the microprocessors to which this patent's subject matter relates (same-ISA asymmetric/hybrid multicore power management).
• Product question: Whether Intel ever shipped an SKU that practices the claims is not something I can confirm from this record. The specification's same-ISA big/low-power core pairing is architecturally the ancestor of Intel's later hybrid client parts, but I have no evidence tying a specific Intel product to these claims, and I will not assert one. What is documented is that Intel retained a license-back to practice the transferred patents after the Daedalus transfer — Daedalus told the ITC that "Complainant's licensee, Intel Corporation... is authorized to practice the Asserted Patents" (337-TA-1336 public-interest statement, 2022-09-12).
• Status: Operating and solvent. No bankruptcy, no fire-sale, no dissolution anywhere in this chain.

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Assignment timeline

Link 0 — inventors → Intel (pre-issuance, parent application). The '080 is a continuation of App. 13/335,257 (US 9,569,278 B2), filed 2011-12-22, and the record is consistent with the standard Intel employee assignment. However, I could not retrieve the reel/frame for the inventor→Intel assignment, and Google Patents' legal-events block for the '080 does not list one. I am therefore recording it as unverified rather than inventing a reel number. If a fresh Assignment Center query is run, expect a 2011–2012-era Intel recording on the parent, not on the '080 itself.

Link 1 — Intel → Daedalus Prime LLC (the operative transfer for the '080)

• 2022-06-03 (executed) / recorded 2022-06-06 — Reel 060392/0594
  • Conveyance: Assignment
  • Assignor: Intel Corporation ("Seller"), a Delaware corporation
  • Assignee: Daedalus Prime LLC ("Buyer"), a Delaware limited liability company, 51 Pondfield Road, Suite 3, Bronxville, NY 10708
  • Correspondent: not retrievable from my sources — recorded as unverified. The only structural inference I can make is that Reel 060392 is a single bulk recording block: sibling Intel patents in the identical family/era were recorded in the same reel at nearby frames (e.g. 060392/0603 for US 9,877,139, same effective date 2022-06-03). That is consistent with one filing firm handling the whole portfolio recording, but I do not have the name and will not supply one.
  • Context: Transfer-to-asserter. Operating semiconductor manufacturer → single-purpose licensing LLC, executed ~2.5 months before the first infringement suits.

Link 2 — later-recorded confirmatory / corrective recordings in the same block

• For sibling patents in the same Intel→Daedalus block, records exist for a short-form assignment effective 2021-04-26, recorded 2023-02-13 at Reel 062746/0654, and a corrective assignment recorded 2023-05-18 at Reel 063695/0134. The corrective assignment in that reel block states it was filed to fix a mis-identified patent number (a US 10,592,626 / 10,593,626 transcription error) in the earlier recording.
• Flag: the '080 itself shows only the 060392/0594 (2022-06-06) entry in the legal-events block I hold. I cannot confirm whether a 2021-effective short-form and/or a corrective record also exist for the '080. Two cautions follow: (i) treat the 060392 reel as known to contain at least one erroneous patent-number identification, and (ii) note that the real-world transfer date for this block is itself in litigation — see the contradiction flag below.

Contradiction with prior analysis / internal record dispute (important). The earlier general statute-of-limitations summary you supplied describes the transfer as "effective 2022-06-03," citing the recorded assignment and RPX's statement that Daedalus "acquired the asserted portfolio from Intel in early June 2022." That is correct as to what was recorded. But the parties themselves later took a different position in litigation: TSMC's operative complaint alleges that "Intel and Daedalus now contend the Assigned Patents were transferred on April 21, 2021" — per a 2021 "Patent Agreement" referenced in the June 2022 assignment — while Daedalus recorded the assignment with the USPTO under a June 3, 2022 effective date. TSMC pleaded that this timing conflict implicated Intel's LOT Agreement with TSMC (signed 2022-05-05 deliberately after the claimed 2021 transfer). So there are two competing transfer dates in the public record for this asset block: 2021-04-21 (asserted by the parties in litigation) and 2022-06-03/06 (recorded at the USPTO). For chain-of-title purposes, the recorded date controls what the Assignment Center shows; the litigation date is what Daedalus and Intel assert for license-gap purposes. Any downstream reliance on "Daedalus acquired this in June 2022" should carry that caveat.

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Timeline diagram

timeline
    title Ownership of US 10049080
    2011 : Filed by Intel employees as parent case
         : Priority date 22 Dec 2011
    2018 : US 10049080 B2 issues to Intel
    2021 : Daedalus Prime LLC formed in Delaware
         : Intel and Daedalus sign April Patent Agreement
    2022 : Assignment executed 3 June
         : Recorded 6 June at reel 060392 frame 0594
         : Daedalus Prime files first suits 23 Aug
    2023 : Samsung and Mercedes IPR petitions filed
    2025 : IPR certificate issued 21 Apr

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NPE / troll-pattern signals

1. Shell-entity transfer — PRESENT.
Intel Corporation (operating, fab-owning) → Daedalus Prime LLC, per Reel 060392/0594, executed 2022-06-03. The assignee is a single-purpose Delaware LLC formed 2021-01-26 (per Mondaq's portfolio analysis), with a non-corporate address at 51 Pondfield Road, Suite 3, Bronxville, NY 10708, and no products. TSMC's declaratory-judgment complaint states flatly: "Daedalus, an NPE, manufactures nothing, but instead acquires other companies' patents to enforce" (D. Del. 1:22-cv-01647, D.I. 37). Daedalus's own ITC filing confirms its only "licensee" is Intel, the transferor. This is the core signal and it is documented, not inferred from the name.

2. Known asserter in the chain — PRESENT.
Daedalus Prime does not appear on the classic lists you supplied (Acacia, Marathon, IV, Wi-LAN, etc.), but it is a high-frequency plaintiff surfaced by the asserter-tracking community: RPX's Q3 semiconductor data byte names Daedalus Prime as a 2022 campaign launcher; IAM Media covers its assertion and subsequent patent sales; Unified Patents/RPX-tracked IPRs were filed against it by Samsung, Qualcomm and Mercedes-Benz (IPR2023-00567, IPR2023-01333 and companions). Public records link it to Ed Gomez, a named patent-monetization principal who also runs Daedalus Group LLC (received 500+ US assets from IBM in 2019) and Daedalus Blue LLC, and who is general counsel of Fullbrite Capital Partners — an entity associated with the NPEs Ocean Semiconductor LLC and Vantage Micro LLC. That is repeat-player NPE management, sourced to Mondaq/Unified Patents coverage rather than to name-similarity.

3. Repeat correspondent across the chain — UNCLEAR (data gap).
I could not retrieve the correspondent of record for Reel 060392/0594 (or for any link in this chain). I am expressly not inferring a name from the "Daedalus" naming pattern. What I can report structurally: the identical recording block 060392 carries many Intel-family patents at nearby frames (e.g. 060392/0603 for US 9,877,139) with the same 2022-06-03 effective date, which is the signature of one firm recording an entire bulk portfolio in a single reel — so a repeat correspondent almost certainly exists across these frame entries, but I have not verified the identity or the name, and it should not be asserted without pulling the reel itself.

4. Cascading transfers — PARTIALLY PRESENT.
Within the Daedalus side of the chain, the structure is Daedalus Prime LLC ← Daedalus Group LLC (its disclosed corporate parent, D. Del. 1:22-cv-01647 D.I. 22, Rule 7.1 disclosure) ← and onward sales out: IAM Media reports Daedalus Prime sold patents to Qualcomm and to TSMC in close proximity to settlements of its litigation. So the chain both takes in a bulk portfolio and parcels assets back out. For the '080 specifically I have no evidence of a further transfer — the Google Patents legal events show no assignment out of Daedalus Prime, and Google still lists Daedalus Prime as current assignee with the 8th-year maintenance fee paid (2026-02-03). Treat the "on-sale" cascade as a family-level pattern, not an '080-specific finding.

5. Pre-litigation transfer — PRESENT.
Recorded transfer 2022-06-06; first suits filed 2022-08-23 (D. Del. 1:22-cv-01107/01108/01109; E.D. Tex. 2:22-cv-00352). That is ~11 weeks — comfortably inside the 6-month window. The '080 was expressly asserted in the 2022-08-23 wave: the AO-120 form in E.D. Tex. 2:22-cv-352 lists "US 10,049,080 B2 — 8/14/2018 — Holder of Patent or Trademark: Daedalus Prime LLC." On the alternative litigated theory (transfer 2021-04-21), the gap is ~16 months, but the recorded chain is the one that enabled assertion.

6. Bankruptcy fire-sale — NOT PRESENT.
No Chapter 7/11 anywhere; Intel was and is solvent. The 2022 transfer was a negotiated portfolio monetization, structured with a license-back and an NPE-aware contract clause (the June 2022 assignment's recitals quote the 2021 Patent Agreement, and the TSMC litigation quotes the agreement's own definition of "NPE").

7. Privateering — PRESENT as to structure; UNCLEAR as to direction.
The documented structure has the classic privateering shape: Intel transfers the asset to an NPE, keeps a license to practice it (Daedalus's ITC public-interest statement), and the NPE sues Intel's foundry/SOC competitors (TSMC, Samsung) — while Intel simultaneously argued it had no remaining ownership and no exposure (Intel's motion to dismiss in 1:22-cv-01647). TSMC further alleged the June 2022 timing was arranged to fall after Intel's 2022-05-05 LOT Agreement with TSMC, i.e., to escape a license Intel had just granted. That is a well-pleaded privateering/license-gap theory, and a federal court in Delaware is where it is being tested. The element I cannot confirm is whether Intel directed Daedalus's assertion (Intel contested that characterization and sought dismissal as a non-owner). So: structure = present; control/direction = unclear.

8. Defensive aggregator — NOT PRESENT.
The chain terminates at an asserting NPE, not at RPX, AST, LOT, Unified or OIN. Note the bitter irony that this asset was the subject of a LOT-Agreement dispute rather than being neutralized by one.

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Verdict

NPE — high confidence.

Justification: the '080 moved from an operating manufacturer to a single-purpose Delaware LLC formed 2021-01-26 with no products, by an assignment executed 2022-06-03 and recorded 2022-06-06 at Reel 060392/0594 — and that entity asserted the patent in litigation ~11 weeks later (first suits 2022-08-23; the '080 appears on the AO-120 report in E.D. Tex. 2:22-cv-00352 as held by Daedalus Prime LLC). The assignee is independently identified as an NPE by the counterparty ("Daedalus is an NPE... manufactures nothing," D. Del. 1:22-cv-01647 D.I. 37), is tied by public records to repeat NPE manager Ed Gomez (Daedalus Group / Daedalus Blue / Fullbrite), and the transfer carried a license-back to the transferor plus a later-litigated license-gap theory against TSMC — three independent, dated, documented signals rather than naming alone.

Verification link (Assignment Center, search "10049080"): https://assignment.uspto.gov/patent/index.html#/patent/search?q=10049080

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Open items to close with a direct Assignment Center pull

1. Correspondent of record for Reel 060392/0594 (and whether the same name appears across frames 0594, 0603, etc. in the same reel).
2. Whether the inventor→Intel assignment for parent App. 13/335,257 is recorded (reel/frame), and whether the '080 has its own.
3. Whether the 2021-04-26-effective short-form assignment (Reel 062746/0654) and the 2023-05-18 corrective assignment (Reel 063695/0134) also cover the '080 — the correctives in that block fixed a mis-identified patent number, so reel 060392/062746 entries should be read with that in mind.

I'll verify the citation records and the PTAB/prior-art record for US 10,049,080 before analyzing each reference.

Good — I now have the IPR record and full text of key references. Let me verify the examiner-cited art (Grochowski) and a few remaining citations.

Prior-Art Analysis — US 10,049,080 B2

Patent under analysis: US 10,049,080 B2, Asymmetric performance multicore architecture with same instruction set architecture (George, Jahagirdar, Marr; orig. Intel Corp.; now Daedalus Prime LLC)
App. No. 15/431,527 · Filed 2017-02-13 · Granted 2018-08-14 · Priority 2011-12-22 (continuation of 13/335,257 → US 9,569,278 B2)
Status of this analysis: build-on to the earlier bibliographic/claims/litigation sections; nothing here repeats them. Where the earlier summary flagged an open item (PTAB certificate scope, 2026 CAFC docket), I carry the caveat forward rather than resolve it.

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0. Headline finding before the reference-by-reference work

No front-of-patent citation appears to be a clean, single-reference §102 anticipation of independent claims 1, 9, or 17. The reason is structural, not incidental: each of claims 1/9/17 ends with the same conjunctive limitation —

"wherein an operating system to execute on the multi-core processor is to monitor a demand for the multi-core processor and control the power management hardware based on the demand"

— coupled to the negative limitation *"disable all of the first plurality of cores … without disabling any of the second plurality of cores," started "from a state where the first plurality of cores and the second plurality of cores are enabled." The front-page art is (i) core-switching art (one core in, one core out — the opposite of "both enabled"), (ii) DVFS/cluster art (voltage-frequency, not core-mix), or (iii) architecture art (heterogeneous cores) that is silent on who monitors demand. This matches the litigation record exactly: in IPR2023-01333 the petitioner pleaded obviousness under §103 only, for all challenges — no §102 ground — and the dispute collapsed onto whether the disclosure's core switching module / hypervisor (Sutardja) or controller below the OS (Mathieson) could be the claimed "operating system." (Petition, IPR2023-01333; PO Response)

So the honest answer to "which claims does X anticipate under §102" is almost always: the dependent architectural claims (2–7, 10–15, 18–23), not the independents. I say so explicitly at each reference rather than manufacture anticipation.

Legal framework applied. Priority is 2011-12-22, so pre-AIA §§102/103 govern (assuming the claims are entitled to the '257 parent's date; the '080 is a straight continuation, so they should be). The relevant categories are §102(a)/(b) (publication more than one year before, or before invention) and §102(e) (US patent or published US application as of its filing date, for subject matter "by another"). Two citations on the face publish after 2011-12-22 and therefore stand or fall on §102(e) filing dates — I flag them.

Important discriminator used below. Google's table marks certain citations with an asterisk ("cited by examiner"). Eight of the 21 were substantively before the examiner: US 2006/0095807, US 2006/0279152, US 2008/0263324, US 2009/0271646, US 2010/0131781, US 2011/0093733, US 2011/0252260, US 2012/0260258. The other thirteen are non-examiner citations. This distinction matters because §102 anticipation is a reference-alone test — the examiner-flagged set is the set that was actually tested against a single reference and survived.

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1. The 21 patent citations (face of US 10,049,080)

* §102 category assumes the pre-AIA statute and assumes the citation's own date is the operative date; see §3 caveats.
★ = flagged "cited by examiner" in the Google Patents citation table.
Source of all dates/titles/assignees: the authoritative full text supplied in the prompt (face pages), cross-checked against Google Patents US10049080B2.

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2. Reference-by-reference §102 analysis

TIER 1 — the art that actually matters

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C-02. US 2006/0095807 A1 — Grochowski et al., Method and apparatus for varying energy per instruction according to the amount of available parallelism

• Full citation: US 2006/0095807 A1; filed 2004-09-28 (App. 10/952,627); published 2006-05-04; assignee Intel Corp.; inventors E. Grochowski, J. Shen, H. Wang, D. Orenstein, G. Sheaffer, R. Ronen, M. Annavaram. Granted as US 7,437,581 B2 on 2008-10-14. (US 7,437,581)
• §102 category: §102(b) (published 2006-05-04, >1 yr pre-priority). Also §102(a) as to invention date.
• Brief description: A chip-level multiprocessor with two populations of cores on one die — "A cores" and "B cores" — where a throttle module "determine[s] the amount of parallelism present in the currently-executing program" and reassigns/migrates threads across the two populations: "If the amount of parallelism is high, then the processor may be configured to run a larger amount of threads on cores configured to consume less power. If the amount of parallelism is low, then the processor may be configured to run a smaller amount of threads on cores configured for greater scalar performance." The disclosure gives an explicit power ratio (one A core ≈ 25 B cores) and a shared power-budget framing, plus FCS/VCS-style frequency and voltage change sequences.
• Why this is the single most important citation: the IPR petition states that the examiner rejected the independent claims of the '080 over Grochowski, relying on Grochowski's "parallelism in the program" as the claimed "demand." (Petition excerpt) The applicant's file history then located novelty in the power-management-hardware / OS-control language.
• Claim mapping (potential §102):
  • Claims 1, 9, 17 — architecturally close, but not anticipatory on the present record. Grochowski supplies the first/second plurality of differently-powered cores on one die (§102 element (a) partially, element (b) squarely) and demand-responsive reconfiguration of the core mix. It does not squarely supply (i) the same instruction set across A and B cores as a claimed positive limitation, (ii) the "disable all of the first plurality … without disabling any of the second plurality" ordering at the claimed threshold (its taught direction on decreasing parallelism is the reverse — the petition itself notes "Grochowski discloses enabling high-power (A) cores and disabling low-power (B) cores in response to decreasing 'parallelism,'" i.e., opposite behavior), and (iii) it is equivocal on OS control: one embodiment is "transparent to software," while another is expressly "not transparent to software … performed by an operating system scheduler." That optional embodiment is the best §102 hook in the entire front page for the claim-1 OS limitation — and, notably, it is the limitation the examiner never succeeded on.
  • Dependent claims: strongest on claims 2/3 (differently-sized/leakage transistors — the B cores), 4/12/20 (lower max operating frequency of the low-power population), and 5/13/21 and 6/14/22 (frequency/voltage change sequences on demand transitions).
• Verdict: Best available single-reference §102(e)/(b) candidate against claim 1 — Low-to-Medium confidence, hinging entirely on (i) and (iii) above; strong as §102 or §103 art against claims 2–7, 10–15, 18–23.

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C-05. US 2008/0263324 A1 — Sutardja et al., Dynamic core switching (Sutardja '324)

C-06. US 2008/0288748 A1 — Sutardja et al., Dynamic core switching (Sutardja '748)

• Full citations: US 2008/0263324 A1, pub. 2008-10-23, earliest priority 2006-08-10 (Marvell-family provisionals), inventors S. Sutardja, H.-Y. Chen, P. Sakarda, M. Fullerton, J. Heeb; and US 2008/0288748 A1, pub. 2008-11-20, same priority, filed as a continuation of App. 12/145,660 (2008-06-25) and a continuation-in-part of App. 11/523,996 (2006-09-20). '748 is a continuation of '324 and a CIP of Sutardja '785 (US 2007/0083785 A1, pub. 2007-04-12), which '748 incorporates by reference.
• §102 category: §102(b) both.
• Brief description (verified against the published applications): A processing system with a high-speed/high-power ("HP") core and a low-speed/low-power ("LP") core plus a core switching module that swaps execution between them. Expressly disclosed:
  • "Both may use the same ISA's" / "The LP core 28 may use an ISA that is the same as or a subset of the ISA of the HP core 24" — the LP/HP ISAs are "compatible," with the HP ISA a superset;
  • HP core fabricated with a high-leakage/high-speed process, LP core with a low-leakage/low-speed process, with transistors 106 larger than transistors 110, larger gates, larger gate count in the HP core;
  • Multiple HP cores ("The HP core 204 may comprise multiple identical cores") and (via '785, as pleaded) multiple LP cores;
  • Switching transparent to the OS; core-switching module executes above the kernel / integrated with a hypervisor; PMS module disables interrupts and issues a system call; control returns to the kernel afterwards;
  • Threshold-based triggering (core profile module, CCS thresholds, FCS frequency change sequence, VCS voltage change sequence); L2 cache powered down with the inactive core; SOC/SIP packaging.
    (US 2008/0263324 full text; US 2008/0288748 full text)
• Claim mapping (potential §102):
  • Claims 1, 9, 17 — does not anticipate. Two independent gaps, and they are the same two gaps the Patent Owner won on in IPR2023-01333: (i) Sutardja teaches mutual exclusion — the HP core "is inactive" while the LP core runs, and vice versa — which is the opposite of the claim's "from a state where the first plurality of cores and the second plurality of cores are enabled"; and (ii) the entity that "control[s] the power management hardware" is the core switching module (software above the kernel, or integrated into a hypervisor), not "an operating system to execute on the multi-core processor." The Patent Owner's position was that the module's involvement is a call/request to the OS, not OS control, and that "the core switching module … returns control to the kernel." (PO Response §VI; Brogioli Decl.)
  • Dependent claims — genuinely anticipatory-suggestive on the architecture leg:
    • Claims 2 / 10 / 18 (narrower logic-gate driver transistors in the second plurality): §102-suggestive — Sutardja's LP core uses smaller transistors/larger HP gate sizes ("transistors 106 may have a size that is greater than a size of the transistors 110").
    • Claims 3 / 11 / 19 (lower-power logic gates): §102-suggestive — low-leakage process vs. high-leakage process.
    • Claims 4 / 12 / 20 (second plurality's max frequency < first plurality's): §102-suggestive — "a first maximum speed of said first asymmetric core is greater than a second maximum speed of said second asymmetric core" (Sutardja '324 cl. 5).
    • Claims 5 / 13 / 21 (sequentially disabling further cores down to one, lowering frequency/voltage): §102-suggestive in substance via the CCS/FCS/VCS modules and "selectively activating and deactivating more than one of said plurality of said first asymmetric core."
    • Claims 7 / 15 / 23 (first plurality at maximum operating frequency in the state): supported by the FCS "low-to-high … until the highest and/or desired operating frequency … is reached."
    • Claims 8 / 16 / 24 (re-enable all first plurality on a demand rise without disabling the second plurality): weak — Sutardja's transition is a swap; nothing teaches the second plurality staying enabled.
• Verdict: Primary §103 art (as pleaded), and §102-suggestive on the dependent architectural claims. Not an anticipation of 1/9/17. This is also the reference that generated the "operating system" fight, so its §102 relevance is now largely historical.

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C-16. US 2010/0153954 A1 — Qualcomm Inc., Apparatus and Methods for Adaptive Thread Scheduling on Asymmetric Multiprocessor

• Full citation: US 2010/0153954 A1; priority 2008-12-11; published 2010-06-17; assignee Qualcomm Incorporated. No asterisk (not an examiner citation).
• §102 category: §102(b).
• Brief description: Adaptive thread scheduling for an asymmetric multiprocessor — i.e., cores of unequal performance/capability in one processor, with the scheduler assigning work to cores by capability. By its title and class it targets exactly the architectural predicate of claims 1/9/17 element (a)+(b).
• Claim mapping (potential §102):
  • Claims 1/9/17: potentially supplies the "asymmetric cores, scheduler assigns work by core class" predicate; does not appear (from the title/face record available to me) to supply the two claim-1-specific negatives — disabling all of the high-power group while disabling none of the low-power group, under OS-monitored demand.
  • Dependent claims 4/12/20 and 7/15/23: plausible support for asymmetric max-frequency/power ceilings.
• Caveat: I did not retrieve the full text of this reference in this session; the description above is drawn from its title, classification and assignee as recorded on the '080's own face. Do not rely on the element mapping without pulling the document. Rank it Tier 1–2 for the architectural element and unverified for the OS-control element.

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C-01. CN 101076770 A — Intel (英特尔公司), same title as C-02

• Full citation: CN 101076770 A; priority 2004-09-28; published 2007-11-21; assignee Intel.
• §102 category: §102(a)/(b) as of its 2007-11-21 publication (a foreign printed publication; pre-AIA §102(e) does not reach foreign patents/applications).
• Brief description: the Chinese family member of Grochowski (C-02). Same disclosure substance.
• Claim mapping: identical analysis to C-02, with one practical note: because it is Chinese-language, it is normally cited as corroborating family art for Grochowski rather than as the standalone reference. Anticipation value: same as C-02, but procedurally weaker.

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TIER 2 — meaningful but single-element art

C-04. US 2006/0279152 A1 — LG Electronics, Method and apparatus for implementing a hybrid mode for a multi-core processor ★

• Priority 2005-06-11; pub. 2006-12-14; §102(b). Examiner-flagged.
• Disclosure: a "hybrid mode" across cores of a multi-core processor — i.e., operating the cores in a mixed, non-uniform mode rather than all-active/all-idle.
• §102 mapping: bears on the "from a state where both are enabled" concept and on mixed-core operation, but the title record shows nothing about same-ISA asymmetry or OS-monitored demand thresholds. At best §102/§103 against claims 8/16/24 (core-mix transition behavior). Full text not retrieved in this session.

C-10. US 2009/0271646 A1 — Talwar, Ranganathan, Kumar (HP), Power Management Using Clustering In A Multicore System ★

• Full citation: US 2009/0271646 A1; App. 12/263,411, filed 2008-10-31 (Google lists a 2008-04-24 priority); published 2009-10-29; HP. (Reference front page)
• §102 category: §102(b).
• Brief description (verified): cores on a multi-core chip share fewer voltage sources than there are cores; cores are grouped into "clusters" per voltage source; all cores in a cluster run at one frequency; a management module (MPM) inside the hypervisor applies power-management policies specifying thresholds (e.g., "if a VM is at 85% capacity … increase frequency; if at 50% for a predetermined period … decrease") and migrates VMs between clusters rather than changing a core's frequency in place.
• Claim mapping (potential §102):
  • Claims 1/9/17: supply the power-management-hardware + thresholded, policy-based demand response half of the claim (elements (c)-(d) in part), and a hypervisor-resident monitor/control (relevant because a hypervisor is not "an operating system to execute on the multi-core processor" in the claim's terms — a point Daedalus pressed in IPR). It is silent on same-ISA asymmetric core groups (all cores in a cluster are treated uniformly). Not anticipatory.
  • Best fit: claims 5/13/21 and 6/14/22 (threshold-driven frequency reduction/raising) and the generic "demand below a threshold" language.
• Independent corroboration of its weight: HP/Talwar was separately asserted as core DVFS-clustering art in other multi-core IPRs (e.g., IPR2025-00485), where it was used in a White/Talwar/Lee §103 combination for cluster-level DVFS. (Exhibit transcript) It is strong §103 material, weak §102 material.

C-12. US 2009/0328055 A1 — P. Bose (IBM), Systems and methods for thread assignment and core turn-off for integrated circuit energy efficiency and high-performance

• Priority 2008-06-30; pub. 2009-12-31; §102(b).
• Representative disclosure: energy-efficient multi-core operation via thread assignment plus turning cores off — i.e., core-count modulation as a power lever, which is the general mechanism of claim 1 element (c).
• §102 mapping: on-point for claims 5/13/21 (successive core disabling as demand falls) and for the general "disable cores on low demand" concept; silent (on the title record) as to same-ISA asymmetric populations and OS control. Not anticipatory of 1/9/17. Full text not retrieved in this session.

C-13. US 2010/0058086 A1 — Hallym Univ. Industry-Academic Cooperation Foundation, Energy-efficient multi-core processor

• Priority 2008-08-28; pub. 2010-03-04; §102(b).
• §102 mapping: generic energy-efficient multi-core power management (per-core clock/power gating, DVFS). Relevant to the "power management hardware" element in isolation; silent on asymmetric-ISA-compatible core groups. Not anticipatory. Full text not retrieved in this session.

C-19. US 2011/0252260 A1 — IBM, Reducing Power Requirements of a Multiple Core Processor ★

• Priority 2010-04-08; pub. 2011-10-13; §102(a) (only ~10 weeks before the 2011-12-22 priority). Examiner-flagged.
• §102 mapping: power reduction by core-count/state manipulation in a multi-core processor. It is the closest-in-time of the US publications to the priority date; relevance is to claims 5/13/21 and 6/14/22. Not anticipatory of the independents on the face record. Full text not retrieved in this session.

C-20. US 2012/0117403 A1 — IBM, Power management for processing capacity upgrade on demand

• Full citation: priority 2010-11-09; published 2012-05-10 — i.e., published after the '080 priority date.
• §102 category: §102(e) only, and only as of its 2010-11-09 filing date (published US application, "by another"). This is the one citation where the publication date alone would not qualify it; do not treat it as §102(a)/(b) art.
• §102 mapping: "capacity upgrade on demand" (CUoD) = enabling processing capacity on demand and releasing it when unneeded. Bears on claims 8/16/24 (enabling cores on demand increase) and 5/13/21 (disabling on decrease). Silent on same-ISA asymmetry and OS control. Not anticipatory. Full text not retrieved in this session.

C-21. US 2012/0260258 A1 — E. Regini, Method and system for dynamically controlling power to multiple cores in a multicore processor of a portable computing device ★

• Full citation: priority 2011-04-05; published 2012-10-11 — after the priority date.
• §102 category: §102(e) only, as of the 2011-04-05 filing date. Another citation whose publication date is not its prior-art date.
• §102 mapping: dynamic per-core power control in a portable multicore device — i.e., thresholded, demand-responsive control of a core population (claims 1(c)/9/17 element (c), claims 5/13/21). Examiner-flagged. Silent (title record) on same-ISA asymmetric groups and OS control. Not anticipatory. Full text not retrieved in this session.

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TIER 3 — peripheral / non-analogous (listed for completeness)

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3. Art not on the face of the '080 but actually used to attack it (essential context)

The front-page list is not the art that mattered. The two IPRs used references the examiner never substantively considered:

Ground structure (all §103): Sutardja alone (claims 1–4, 7–12, 15–20, 23–24); Sutardja + Rychlik (5/6, 13/14, 21/22); Sutardja + Carmack (7/15/23); Mathieson + Sutardja (1–4, 7–12, 15–20, 23–24); Mathieson/Sutardja/Rychlik (5/6, 13/14, 21/22). (Institution/Petition record; DocketAlarm docket)

Family-level citations that also bear on §102/§103 (from "Family Cites Families," 14 entries) — these were cited in the '080's family members, not on the '080's own face, but they are the art most likely to be pulled in a future challenge: US 2007/0083785 A1 (Sutardja, high/low power processors + thread transfer); US 2006/0112226 A1 (Hady — heterogeneous processors sharing a common cache); WO 2006/074024 A2 (Intel — instruction-set-based thread execution on a plurality of instruction sequencers); US 8,615,647 B2 (Intel — migrating execution of a thread between cores of different ISA); US 8,543,857 B2 (Intel — low-power operation of multi-core processors); US 2011/0213935 A1 (ARM — switching a workload between first and second processing circuitry); US 7,490,254 B2 (AMD); US 6,804,632 B2 (Intel — distribution of processing activity across processing hardware based on power consumption). Several of these are closer to the claims' architecture than most of the front-page Tier 2/3 art; any of them should be retrieved in full before relying on the front-page list alone.

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4. Consolidated §102 map by claim

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5. Ranked "most relevant prior art" — bottom line

1. US 2006/0095807 A1 (Grochowski, Intel) — the only front-page reference that (a) is about a mixed population of differently-powered cores on one die, (b) is driven by a demand proxy the examiner equated with the claimed "demand," and (c) contains an express OS-scheduler embodiment — i.e., it touches every element of claim 1, even if its taught direction of reconfiguration and its OS-control story are contestable. §102(b).
2. US 2008/0263324 A1 and US 2008/0288748 A1 (Sutardja, Marvell) — the architectural parent of the claims' dependent limitations (same/compatible ISA, HP-as-superset, narrower/lower-leakage transistors, lower max frequency, thresholded core-mix transitions, hypervisor-resident switching). §102(b). Fails only on the "both enabled" and "OS control" elements of 1/9/17.
3. US 2010/0153954 A1 (Qualcomm, asymmetric MP thread scheduling) — the front-page reference most directly on the asymmetric, scheduler-driven predicate. §102(b). Full-text verification needed.
4. US 2009/0271646 A1 (Talwar, HP) — the cleanest disclosure of thresholded, policy-driven power management hardware in a multi-core chip; strong §103 material, and notable because its control entity is a hypervisor (not the claimed OS). §102(b).
5. US 2009/0328055 A1 (Bose, IBM) — core turn-off as a function of workload; the closest front-page analogue to successive core disabling down to one. §102(b).

Plus the off-face art in §3 — Sutardja '785, Mathieson, Rychlik, Carmack — which is, on the litigation record, more probative than most of the face list.

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6. Explicit caveats and uncertainties

1. Anticipation vs. obviousness. I have not labelled any reference a §102 anticipation of independent claims 1/9/17 because each misses at least one element, and where I say "suggestive" I mean the reference teaches the substance of a dependent limitation, which may be enough if that limitation is the only difference. This mirrors the actual IPR, where every ground was §103.
2. Pre-AIA §102(e) is the sole basis for C-20 (US 2012/0117403, filed 2010-11-09) and C-21 (US 2012/0260258, filed 2011-04-05) — both publish after the 2011-12-22 priority. Any invalidity contention built on them must be pled under §102(e)/§103 with the filing date as the critical date.
3. Several Tier-2/3 descriptions are drawn from titles, assignees and dates on the '080's own face, not from full text. I retrieved full text for Grochowski, Sutardja '324/'748, Talwar, and the IPR record; I did not retrieve the bodies of Qualcomm '954, LG '692/'152, Capps '192, Bernstein '826, Xilinx '020, Bose '055, Hallym '086, Hitachi '011, Memon '781, Kruglick '733, and the IBM '015/'260/'403 references. Element-level mappings for those are provisional. Flagged inline.
4. The '080's own IPR outcome is not fully resolved here. The PTAB record shows a Final Written Decision terminating IPR2023-01333 on 2025-01-08 and an IPR certificate (K1) issued 2025-04-21. Certificates of that kind normally issue under 35 U.S.C. §318(b) to cancel claims held unpatentable, and IPR2023-00567 (Samsung/Qualcomm et al.) terminated by settlement. I could not retrieve the FWD text identifying which of claims 1–24 were cancelled, so I do not state as fact that any claim was cancelled. If some or all claims were cancelled, the §102 analysis above becomes historical as to those claims. (PTAB case page; IPVerse case record)
5. Specification defect worth noting for claim construction (carried forward from the earlier sections, not a new finding): the FIG. 8 discussion says the low-power netlist is synthesized with libraries "corresponding to a lower power/performance design (such as logic circuits having wider drive transistors)" — the opposite of what claims 2/10/18 recite ("narrower"), and it appears twice. Any §102/§103 reading of the "narrower drive transistor" limitations should be anchored to the claims and to the FIG. 3/FIG. 4 discussion, not to that passage.
6. Date discrepancy (already flagged in the earlier summary and still unresolved): the working context timestamp is 2026-09-23, while the task header says 2026-04-26. I have treated all reference dates as given on the documents themselves, which is unaffected by the discrepancy.
7. Assignee/title disclaimers on the source page are Google boilerplate; the recorded owner remains Daedalus Prime LLC (assignment effective 2022-06-03, Reel/Frame 060392/0594), with the 8th-year maintenance fee paid 2026-02-03 and anticipated expiration 2031-12-22.

One-line answer: for US 10,049,080 the most relevant prior art is Grochowski (US 2006/0095807 A1) against independent claims 1/9/17 (low confidence for §102, high for §103) and Sutardja '324/'748 against dependent claims 2–7, 10–15 and 18–23 — with the off-face references Sutardja '785, Mathieson, Rychlik and Carmack being more probative than most of the citations printed on the patent's face.

I'll ground the obviousness analysis in the prior-art references listed on the patent page and in the PTAB record before drafting.

Let me pin down the Final Written Decision outcome and identify the Rychlik and Carmack references.

Let me identify the Rychlik/Carmack references and try to confirm the Final Written Decision outcome.

Obviousness Analysis — U.S. Patent No. 10,049,080 under 35 U.S.C. § 103

Scope note. I treat the identifier literally as US 10,049,080 B2. This section builds on, and does not repeat, the prior-generated patent summary and litigation summary. Where the research below contradicts or refines those sections, I flag it explicitly at the end.

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1. Governing law, effective date, and PHOSITA

Effective filing date. Priority runs to December 22, 2011 (App. 13/335,257 → US 9,569,278 B2); the '080 is a continuation filed 2017-02-13. Because the application's claims never contained subject matter with an effective filing date on or after March 16, 2013, pre-AIA §§ 102/103 govern (AIA § 3(n)(1)). In practice this changes nothing here: every reference relied on below published well before December 22, 2011, so each qualifies under pre-AIA § 102(b) (or § 102(a)/(e) for the later-published items), and § 103 permits combination of § 102(a) art as well as § 102(b) art.

Graham/KSR framework. Obviousness is assessed from the perspective of a PHOSITA at the time of invention, considering (1) scope and content of the prior art, (2) differences between the prior art and the claims, (3) level of ordinary skill, and (4) secondary considerations. KSR Int'l Co. v. Teleflex Inc., 550 U.S. 398 (2007), supplies the rationales used below: known technique to improve similar devices in the same way; combination of familiar elements according to known methods yielding predictable results; design incentives and market forces; and "obvious to try" where the design space is small and the results predictable.

PHOSITA. A person with at least a bachelor's degree in electrical/computer engineering (or equivalent) plus roughly 3–5 years of experience in processor architecture and power management, or a master's degree with fewer years. (This is the level the Board implicitly applied in IPR2023-01333; Patent Owner's expert, Dr. Brogioli, noted a dispute over the petition's proposed "at least" qualifier for the skill level.)

The critical structural fact. The '080's own specification admits that the power-management strategy itself (enable/disable cores as workload scales; scale supply voltage and frequency) is prior art: FIG. 2 and its accompanying text describe a maximum-performance state (all cores enabled, max V/f) and a minimum state (one core, min V/f). The patent's asserted novelty therefore reduces to two things: (a) an asymmetric core mix that uses the same ISA and differs only by implementation/library (narrower drive transistors), and (b) an operating system that monitors demand and controls power-management hardware. That framing sharply narrows the § 103 inquiry.

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2. Construction of the dispositive limitations

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3. The prior art on the face of the '080 — and the IPR art

3(a) References cited on the face of the patent (Google Patents "Citations" / "Patent Citations" / "Family Cites Families")

3(b) The IPR art (verified from the IPR2023-01333 record)

⚠️ Accuracy flag. Mathieson (US 2011/0213950) and Carmack (US 2009/0309243) do not appear anywhere in the '080's face-of-patent citation lists. They entered the public prior-art record only through IPR2023-00567 and IPR2023-01333. Conversely, the Sutardja dynamic-core-switching family is on the face of the '080 — the examiner cited US 2008/0263324 A1 and US 2008/0288748 A1. That is a significant fact for any § 103 analysis: the applicant had the primary IPR art in front of it during prosecution but the claims issued over it.

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4. Claim 1 — element-by-element (Combination A: Sutardja '748 + '785)

Assessment. Every element of claim 1 is disclosed or rendered obvious by Sutardja '748/'785 alone. The only genuine gap is plurality of LP cores (Sutardja's disclosed embodiment shows one LP core with optional multiple HP cores). That gap is closed either by (i) KSR's "known technique to improve similar devices in the same way" — adding a second low-power core to a design that already contemplates multiple cores, where Mathieson expressly teaches multiple slow cores, or (ii) Carmack, which discloses first and second sets of asymmetric cores 110/120.

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5. Claim 1 — Combination B (Mathieson + Carmack)

• Mathieson '950: CPU 102 has "fast" cores 130 and "shadow"/slow cores 140 (Fig. 1); ¶28 — fast cores are "manufactured using faster transistors that have significant static leakage" and "at slower clock speeds, the static leakage of the fast transistors can dominate the overall power consumption"; Fig. 6 plots power vs. operating frequency showing the slow cores (blue) consuming less power than the fast cores (red) across a wide frequency range; ¶¶30–31, 37 discuss "operating characteristics" including frequency and voltage; resource unit 230 is a shared L2 cache; ¶43 — processing state is transferred between the core sets.
• Carmack '243: cores 110, 120 are "different implementation[s] of substantially the same function," expressly including the case where "the first core 110 may be implemented using a high threshold voltage (Vt) transistor and the second core 120 may be implemented using a low threshold voltage (Vt) transistor"; core control circuit 130 sequences core utilization against a performance parameter (workload, frequency, power, temperature); Fig. 3 shows transitions between (a) first core only, (b) second core only, and (c) both cores, based on measured workload ranges.

Assessment. Mathieson + Carmack supplies the asymmetric-core groups, the same-functionality requirement, the transistor-difference mechanism, the shared cache, and the enable-both-on-rising-workload behaviour of claim 8. The same-ISA element is the one thing Mathieson/Carmack do not state in so many words; that gap is why the petitioner paired them with Sutardja (Grounds 4–5), which expressly teaches same-or-subset ISA for "dynamic compatibility." This is the strongest single combination in the record: it is the one the Board instituted on, and it maps to all three independent claims.

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6. Motivation to combine (KSR rationales, applied)

1. Same field, same problem. Sutardja '748, Mathieson '950, and Carmack '243 all address power consumption in multi-core processors, several expressly in mobile/battery-powered devices (Mathieson ¶¶5–7; Sutardja ¶¶212–215). KSR rationale: familiar elements from the same technical field.
2. Explicit incorporation by reference. Mathieson '950 is a continuation-in-part of App. 12/137,053 — the very application that published as Carmack '243 — and the petition (and Patent Owner's own expert, at Ex. 2006 n.5) treats Mathieson as incorporating Carmack. Motivation to combine is therefore not merely inferable; it is documented.
3. Express teaching of the missing element. Sutardja teaches that the LP and HP cores may use the same ISA "to achieve dynamic compatibility" and that "both may use the same ISA's." Adding that teaching to Mathieson/Carmack is using a known technique to improve a similar device in the same way, with predictable results.
4. Predictable, mechanistic result. The '080's own specification explains the mechanism as ordinary circuit physics: narrower drive transistors → less current sourced/sunk → slower transitions → lower power at the same V and f, at the cost of a lower maximum operating frequency. Sutardja and Mathieson independently teach the same transistor-level mechanism. A PHOSITA would predict the outcome with confidence; this is not an "obvious to try" case in the weak sense — it is an "obvious because the physics is known" case.
5. Design incentive / market force. The patent itself frames the problem as an industry-wide concern with power consumption in computing systems; the references uniformly motivate lowering minimum-power operating points.
6. Small, finite design space. Governing the core mix from the OS rather than from an embedded controller is a binary design choice with well-known tradeoffs (the '080's own specification lists both: "the hardware/machine readable firmware can monitor and control the core mix; or … the hardware can relinquish control to the Operating system"). Where the specification presents both alternatives without asserting a criticality or unexpected result, the choice between them is a routine design decision. KSR; In re Venner; In re Kuhle.

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7. Claims 9 and 17

Claims 9 (method) and 17 (non-transitory machine-readable medium) recite the same substantive limitations as claim 1 in different statutory categories. They rise and fall with claim 1. For claim 17 specifically, the program-code-on-medium format is met by any of the references that store power-management code in a memory accessible to the processor; there is nothing in claim 17 that adds patentable weight. Note also that the § 101/§ 112 dimension of claim 17 was not raised in the IPR.

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8. Dependent claims

No dependent claim contains a limitation that would survive the primary combinations: none adds a structural or algorithmic feature (e.g., a specific threshold-computation, migration protocol, or coherency mechanism) that is absent from the art.

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9. Foreseeable rebuttals and how they fare

(a) "Sutardja's controller is not an operating system; the OS merely makes a system call." This was Patent Owner's core argument and the one the Board pressed hardest at the November 13, 2024 oral argument. It has real force, and it is the limitation most likely to decide the case at the margin. Counter-arguments available to a challenger: (i) the '080's specification itself does not distinguish sharply between hardware, firmware, and software implementations of the power-management function, describing a "power management process flow [that] can be executed entirely in hardware … or by some combination of such hardware and software"; (ii) Sutardja ¶249–253 places the demand-monitoring PMS module 242 and kernel module 220 within the OS; (iii) a POSITA would understand firmware/microcode resident in the processor to be "power management hardware." Patent Owner's rejoinder — that the actual switching authority sits in the core switching module/hypervisor, which is not the OS, and that Mathieson's controller operates "transparently to the operating system" (i.e., below it) — is a genuine claim-construction fight, not a merits certainty.

(b) "Mathieson's Fig. 6 says nothing about supply voltage." Patent Owner argued Fig. 6 plots power only against frequency, so it cannot establish "a same applied operating frequency and supply voltage." Rebuttal: Mathieson ¶¶30–31, 37 expressly frame the comparison in terms of "operating characteristics, including operating frequency [and] voltage," and ¶28 attributes the difference to transistor design (leakage), which is frequency- and voltage-independent as a mechanism. Still, this is the second-most contestable limitation, and a challenger should support it with a POSITA declaration rather than Fig. 6 alone.

(c) Teaching away. I found no evidence in the record of an express teaching away. The closest is Sutardja ¶213 ("An instruction set architecture (ISA) of the LP core 12 may differ from the ISA of the HP core 16 … Alternately, both may use the same ISA's") — but two embodiments in the alternative is not a teaching away from the same-ISA embodiment; Sutardja affirmatively discloses it. The '080's prosecution history (three rounds of US Office Actions and four rounds of Chinese Office Actions on the parent) does not appear to contain a disavowal.

(d) Secondary considerations. No nexus-bearing evidence of unexpected results, commercial success, long-felt need, or industry praise appears in the record I retrieved. The '080's alleged advantage — "even lower power consumption" at the lowest state — is exactly what the mechanistic combination predicts, and the patent's own specification attributes it to known transistor-width physics rather than to an unexpected discovery. Absent unexpected results, this weighs toward obviousness.

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10. Bottom line

• Claims 1–4, 7–12, 15–20, 23–24 are strongly obvious over Sutardja '748 incorporating '785, and independently over Mathieson '950 in view of Sutardja '748 — the same grounds on which the Board instituted IPR2023-01333 (Grounds 1 and 4). The same-ISA limitation is the only element not literally in Sutardja's primary embodiment, and Sutardja supplies it expressly.
• Claims 5–6, 13–14, 21–22 are obvious over Sutardja + Rychlik (Ground 2), reinforced by the '080's own admission in FIG. 2 that sequential core disablement with V/f scaling was known.
• Claims 7, 15, 23 are obvious over Sutardja + Carmack (Ground 3).
• The central vulnerability of the patent is not the asymmetric same-ISA architecture — that was squarely in the art, and the applicant even cited Sutardja's dynamic-core-switching family during prosecution. It is the "operating system … control[s] the power management hardware" limitation, which requires a claim-construction ruling on whether an OS that issues system calls to a switching module "controls" that module, and whether the switching module itself qualifies as power-management hardware. That is the dispositive issue, and it was joined at the Board's oral argument.

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11. Contradictions, corrections, and unverified items (flagged per instructions)

1. No contradiction found with the prior-generated sections' description of IPR2023-01333 (instituted 2024-02-13; grounds 1–5; FWD terminating the case 2025-01-08; K1 certificate 2025-04-21). This research confirms those entries and adds the verified reference identities and the actual trial disputes.
2. Correction to the prior sections' wording. The earlier sections described the grounds as "Sutardja (Ground 1), Sutardja + Rychlik (Ground 2), Sutardja + Carmack (Ground 3), Mathieson + Sutardja (Ground 4), Mathieson + Sutardja + Rychlik (Ground 5)." That is confirmed. However, the earlier sections referred to "Sutardja (US 2008/0288748)" as a single reference; in the record, Sutardja '748 (US 2008/0288748) is treated as a combined disclosure with Sutardja '785 (US 2007/0083785), which '748 incorporates by reference. The Board's papers are internally inconsistent about which publication is labeled '748 vs. '785 (see Patent Owner's Ex. 2006 n.1, which repeats 2008/0288748 for both), so I report the petition's labeling while noting the inconsistency.
3. Unverified — which claims were cancelled. I confirmed a Final Written Decision (Jan. 8, 2025) and an IPR certificate (K1, Apr. 21, 2025), but I could not retrieve the operative FWD text or the certificate to determine which of claims 1–24 were held unpatentable or cancelled. § 318(b) certificates typically accompany cancellation of claims held unpatentable, but I do not assert that any specific claim was cancelled. This remains the single most important open item; the FWD paper and the certificate should be pulled directly from PTAB E2E / USPTO PatentCenter.
4. Unverified — Rychlik identity. I inferred Rychlik = US 2011/0145615 A1 from the footnote ordering in Patent Owner's Ex. 2006 (footnote 1). I did not independently confirm the publication number or its content.
5. Not on the face of the patent. Mathieson (US 2011/0213950) and Carmack (US 2009/0309243) are not in the '080's citation lists; they are IPR art only. Any § 103 theory built on them is not "applicant-cited art." Conversely, the Sutardja dynamic-core-switching family is applicant-cited art (US 2008/0263324 and US 2008/0288748 appear in the '080's citation lists) — a point that materially strengthens an inequitable-conduct-free but foreseeability-based obviousness narrative.
6. Characterizations from general knowledge, not verified text. My descriptions of the face-cited references US 2009/0271646 (Talwar), US 2010/0153954 (Qualcomm), US 2011/0252260 (IBM), US 2006/0095807 (Intel), US 2009/0328055 (Bose), and US 2011/0093733 (Kruglick) are drawn from the titles and my general knowledge of those documents. I did not retrieve and read their texts in this session, so those rows in § 3(a) should be treated as leads to be verified paragraph-by-paragraph before being relied on in a brief or petition.
7. Live status divergence. Google Patents still lists US 10,049,080 B2 as "Active" with the 8th-year maintenance fee paid (event dated 2026-02-03) and anticipated expiration 2031-12-22. Maintenance-fee status and post-IPR claim status can diverge; the two must be checked separately (see item 3).
8. Single-ISA heterogeneous multicore literature is absent from the page. The well-known academic literature on single-ISA heterogeneous (asymmetric) multicore architectures is not in the '080's Non-Patent Citations list (which consists only of office actions, ISRs, and the Aruj EE Times article). If a challenger wishes to use that literature, it must be independently authenticated in an IPR petition; it is outside the page's Prior Art section and I have not relied on it above.