Invalidity dossier
US 9831306
Current assignee: Daedalus Prime LLC
Added 9/23/2026, 6:49:19 PM
Active provider: DeepSeek · deepseek-flash
Patent summary
Title, assignee, inventors, filing/issue dates, abstract, and a plain-language overview of the claims.
Patent Overview — US 9,831,306 B2
Title: Self-aligned gate edge and local interconnect and method to fabricate same
Patent number: US 9,831,306 B2 (application US 15/024,750; pre-grant publication US 2016/0233298 A1)
Inventors: Milton Clair Webb; Mark Bohr; Tahir Ghani; Szuya S. Liao
Original assignee: Intel Corp. Current assignee (as listed): MediaTek Inc. (the source notes listed assignees may be inaccurate and that no legal analysis was performed.)
Key dates: Priority/filing date 2013-12-19; publication of application 2016-08-11; grant 2017-11-28; anticipated expiration 2033-12-19. Legal status listed as Active.
Purpose and plain-language scope (from the supplied text): The patent concerns semiconductor device fabrication, specifically forming a self-aligned gate edge and a local interconnect, and a method of making the same. The classification data places it in the field of inorganic electric semiconductor devices, including insulated-gate field-effect transistors (IGFETs) and fin field-effect transistors (FinFETs), with manufacture or treatment of such devices. The reclassification entries further tie it to FinFET source/drain electrode structures, replacement-gate (dummy-gate) processes where final gates are self-aligned to dummy gates, gate electrodes for field-effect devices, and integration of multiple components such as IGFETs on a semiconductor substrate.
Prior-art keywords listed: gate, semiconductor, edge isolation, pair, disposed.
Source: https://patents.google.com/patent/US9831306/en
What the excerpt does not establish: The supplied text is a Google Patents bibliographic/classification page and does not include the abstract, claims, written description, or drawings. Therefore it does not establish the specific claim limitations, the precise structural or process scope, the number or content of claims, embodiments, or the actual technical details of how the self-aligned gate edge and local interconnect are formed. Classification entries indicate a general technical field but are not claim scope. No assertion is made here about validity, prior art, litigation, or ownership transfers.
Generated 10/1/2026, 9:42:30 PM
Cases on file (1)
Group view →Specific litigation cases in our database that name US patent 9831306. The free-form analysis below may also discuss cases beyond this list.
- Daedalus Prime LLC v. Samsung Electronics Co., Ltd. et al.filed Sep 12, 20222:22-cv-00352U.S. District Court for the Eastern District of Texasstayed
Defendants: Samsung Electronics Co., Ltd., Samsung Electronics America, Inc., Taiwan Semiconductor Manufacturing Co., Ltd. (TSMC)
Other patents asserted: 10049080, 8775833, 8898494, 10319812, 10700178, 11251281, 10705588
Litigation summary
Past and pending lawsuits — plaintiffs, defendants, jurisdictions, outcomes, and notable rulings.
Proceedings on file (0)
All PTAB activity →AIA trial proceedings (IPR / PGR / CBM) filed at the USPTO Patent Trial and Appeal Board against this patent. Sourced from the USPTO Open Data Portal and refreshed every six hours; each proceeding number deep-links to the PTAB E2E docket.
Current assignee: Daedalus Prime LLC
No PTAB proceedings on file. This patent has not been challenged via IPR, PGR, or CBM. The absence is itself a signal — well-asserted patents eventually attract IPRs. The LLM analysis below may surface filings the ODP feed hasn’t indexed yet.
PTAB challenges
AIA trial proceedings at the USPTO Patent Trial and Appeal Board — IPR, PGR, and CBM. Petitioners, judge panels, claim-level invalidation outcomes from Final Written Decisions, and Federal Circuit appeals. The single most important defensive datapoint after litigation history.
Assignment history
Inventors, original assignee, and the chain of ownership recorded with the USPTO — including the correspondent attorney who recorded each assignment, since shell-LLC chains often share one repeat-player attorney even when the entity names look unrelated. Surfaces NPE / patent-troll patterns: shell-entity transfers, known asserters in the chain, repeat correspondent fingerprints, pre-litigation assignments, and bankruptcy fire-sales.
Prior art
Earlier patents, publications, and products that may anticipate or render the claims unpatentable.
Obviousness
Combinations of prior art that suggest the claimed invention would have been obvious under 35 U.S.C. § 103.
Extensions
Patent term adjustments, term extensions, continuations, divisionals, family members, and expiration dates.
Derivative works
Defensive disclosure: derivative variations of each claim designed to render future incremental improvements obvious or non-novel.
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This patent in court (1)
1 tracked lawsuit name US 9831306.