US 8775833

Patent Overview — US8775833B2

Title: Dynamically allocating a power budget over multiple domains of a processor

Patent number / application: US8775833B2; Application US13/780,066; publication US20130179704A1

Inventors: Avinash N. Ananthakrishnan; Efraim Rotem; Doron Rajwan; Eliezer Weissmann; Nadav Shulman

Assignee: Original assignee Intel Corp; current assignee listed as Daedalus Prime LLC

Key dates: Priority date 2011-09-06; filing date 2013-02-28; publication date 2014-07-08; anticipated expiration 2031-09-06. Legal status listed as Active.

Purpose: Processors now incorporate ever-increasing amounts of circuitry, evolving from independent integrated circuits to multicore processors with multiple cores plus other functional units (e.g., graphics engines, fixed-function units, accelerators). Different circuitry consumes differing power based on workload, and suitable mechanisms to ensure these units have sufficient power did not previously exist.

Plain-language scope: The patent describes dynamically apportioning a processor's power budget at run time across multiple domains. A "domain" is a collection of hardware and/or logic operating at the same voltage and frequency point. In an example, a multicore processor has at least a core domain and a graphics domain that collectively share a single power budget—so higher core-domain frequency leaves less power for the graphics domain, and vice versa. Embodiments dynamically re-partition the package power budget between domains, providing a power-balancing mechanism. Additional domains are contemplated, including per-core domains, domains of fixed-function units or accelerators, and a domain for certain management agents receiving a fixed portion of the total budget. A power budget management (PBM) algorithm may be executed by logic such as a power control unit (PCU) to control the power of an entire processor or an individual domain to a configured power limit, based partly on parameters such as a guaranteed frequency (P1). The excerpt names FIGS. 1–8 covering methods, graphical illustrations, and block diagrams.

Not established by this excerpt: The full claim language, the complete algorithm details, and the omitted portions of the specification. Nothing here should be read as a validity, infringement, or prior-art conclusion.

Source: https://patents.google.com/patent/[US8775833](/patent/US8775833)/en