What the patent actually claims, in plain language. Title, assignee, inventors, filing dates, and a claim-by-claim plain-text overview — grounded in the patent's full text from Google Patents, not a hallucinated guess.
Here's a concise summary of US patent US8307116B2, "Scalable bus-based on-chip interconnection networks": Patent US8307116B2 Summary Title: Scalable bus-based on-chip interconnection networks Inventors: Stephen W. Keckler and Boris Grot Filing Date: 2009-06-19 Issue Date: 2012-11-06 Current Assignee: EMPIRE TECHNOLOGY…
On-file cases involving the patent, plus a free-form narrative of plaintiffs, defendants, jurisdictions, key rulings, and outcomes. Linked to specific case detail pages from our database.
Known litigation involving US patent US8307116B2: The patent document itself notes a US case filed in the Texas Western District Court, case number 1:26-cv-00989. This is also consistent with the previously generated summary. As of April 26, 2026, a direct search for US8307116B2 on publicly accessible litigation…
AIA trial proceedings at the USPTO Patent Trial and Appeal Board — IPR, PGR, CBM. Petitioners, judge panels, claim-level invalidation outcomes from Final Written Decisions, and Federal Circuit appeals. The single most important defensive datapoint after litigation history.
Proceedings overview There are no AIA trial proceedings on file for US8307116B2 as of the most recent data ingest and current web searches. Strategic summary As of June 11, 2026, all claims of US8307116B2 (claims 1-15) remain untested by AIA trial proceedings. There is no estoppel landscape to consider from PTAB…
The chain of ownership recorded at the USPTO — including the correspondent attorney who filed each recording, since shell LLCs swap names but the lawyer running them usually doesn't. Inventors, original assignee, every transfer, and an explicit NPE-pattern verdict: shell-entity LLCs, known asserters, repeat correspondent fingerprints, pre-litigation transfers, bankruptcy fire-sales.
Inventors Stephen W. Keckler Boris Grot At the time of filing, both inventors were affiliated with the University of Texas System. There is no information to suggest an unusual pattern of inventors departing the original assignee within 12 months of filing. Original assignee The entity named on the issued patent is…
References (patents, publications, products) that may anticipate or render the claims unpatentable under § 102. For each: citation, date, and which claims it potentially anticipates.
toolcode print(googlesearch.search(queries=["US8307116B2 USPTO patent citation list", "US8307116B2 most relevant prior art", "US8307116B2 prior art US20070180183A1", "US8307116B2 prior art US20050262270A1", "US8307116B2 prior art US20070014316A1", "US8307116B2 prior art US7499997B2", "US8307116B2 prior art…
Prior-art combinations that render the claims obvious under § 103, including the motivation a person of ordinary skill would have had to combine them. The argument the defense lawyer would build.
Obviousness Analysis of US8307116B2 under 35 U.S.C. § 103 This analysis assesses the obviousness of US patent US8307116B2, "Scalable bus-based on-chip interconnection networks," under 35 U.S.C. § 103, using the explicit prior art disclosed within the patent itself. The analysis considers the perspective of a Person…
Patent term adjustments, term extensions, continuations, divisionals, family members, and projected expiration date — what's still enforceable, and for how long.
To provide the most accurate information regarding US8307116B2's patent term adjustments (PTA), extensions (PTE), application types, family members, and expiration date, I need to access the official USPTO Patent Center or Public Search tools. The current search results indicate that the USPTO does not calculate…
A defensive disclosure: 5–10 derivative variations per claim across material substitution, scale, cross-domain application, emerging tech, and failure-mode designs — with Mermaid diagrams. Once published, this is prior art against any troll trying to patent the same idea later.
Defensive Disclosure: Scalable Bus-Based On-Chip Interconnection Networks (US8307116B2) This defensive disclosure outlines derivative variations of the scalable bus-based on-chip interconnection networks described in US8307116B2. The aim is to preemptively establish prior art for potential incremental improvements…