US 9575895

Patent Overview: US9575895B2

Title: Providing common caching agent for core and integrated input/output (IO) module

Patent number / application: US9575895B2; Application US14/609,620; earlier publication US20150143051A1

Assignee: Original assignee Intel Corp; current assignee listed as Daedalus Prime LLC

Key dates: Prior art date 2011-12-13; filing date 2015-01-30; publication date 2017-02-21; adjusted expiration listed as 2032-02-20

Purpose: The patent addresses integrating an IO component (such as an Input/Output Hub, IOH) into a CPU die to reduce bill-of-material cost, enable small form factors, and reduce power consumption. The stated problem is that an IO agent integrated into a multiprocessor socket (e.g., a multicore processor for an MP server) can cause scaling issues. The proposed solution configures a CPU caching agent to support both CPU traffic and IO traffic, resolving the scaling issue and improving performance by bringing the IO agent and CPU core(s) closer.

Plain-language scope (from the excerpt): A processor socket includes multiple cores coupled to a shared cache memory, which may be a last level cache (LLC) containing a caching agent that may be combined for both the CPU and an integrated IO (IIO) module. The IIO module acts as an interface to off-chip peripheral/IO devices, e.g., via PCIe links, potentially replacing a separate chipset component such as an IOH. The caching agent sits between the cores and the LLC and also interfaces with the IIO module, including an ingress port with multiple ingress queues, an arbiter, a table of requests (TOR) with a dedicated resource for posted transactions, and ingress/egress queues for a ring interconnect. Sockets may couple via a point-to-point QPI link; an integrated memory controller (IMC) interfaces to system memory. Figures 1–7 depict system, caching agent, method flows, a deadlock scenario, and multicore/multiprocessor arrangements. Classification includes G06F12/084 (shared cache), G06F12/0815 (cache consistency protocols), and G06F2212/621 (coherency for peripheral/DMA or I/O device access).

Source: https://patents.google.com/patent/[US9575895](/patent/US9575895)/en

What the excerpt does not establish: The full claim text and precise claim scope; details of several figures (e.g., the deadlock-avoidance scenario); embodiments beyond those summarized; the complete specification and omitted description; and any legal conclusions about validity, infringement, or enforceability. The excerpt also does not establish the accuracy of assignee/litigation metadata, which the source itself labels as non-legal assumptions.