US 10319812

Patent Overview — US10319812B2

Title: Self-aligned gate edge and local interconnect and method to fabricate same

Patent number: US10319812B2
Application number: US15/789,315
Publication: US20180047808A1 (published 2018-02-15); granted as US10319812B2 on 2019-06-11
Filing date: 2017-10-20
Priority date: 2013-12-19
Anticipated expiration: 2033-12-19
Original assignee: Intel Corp
Current assignee (as listed): MediaTek Inc
Inventors: Milton Clair Webb; Mark Bohr; Tahir Ghani; Szuya S. LIAO
Status: Active
Source: https://patents.google.com/patent/[US10319812](/patent/US10319812)/en

Purpose and plain-language scope: The supplied excerpt establishes only that the patent concerns a "self-aligned gate edge and local interconnect and method to fabricate same." Based on the listed prior-art keywords (gate, gate structure, edge, edge isolation, fin), it relates to transistor gate structures, gate edges, edge isolation, and fins. The classifications mention fin field-effect transistors (FinFETs), replacement-gate processes, gate electrodes, and internal dielectric isolations in semiconductor bodies. The excerpt does not state a problem being solved, an embodiment, or a claimed method step in prose; the scope must therefore be read from the claims, which are not included in the supplied text.

What the excerpt does not establish: It contains no claim language, no abstract, no specification text, no figures, and no detailed description. It therefore cannot support any statement about the specific claimed structure or fabrication sequence, the number or scope of claims, the preferred materials or process conditions, or the relationship between this patent and any family member. The reassignment entries and the "Family has litigation" field are recorded in the supplied data but are not described, and no document details are provided (see the excerpt's caveats that legal status and assignees are assumptions, not legal conclusions). This overview deliberately relies only on the supplied text.