US 7863717

I'll search for authoritative information on this specific patent number, including any litigation activity.

The CAFC search returned an unrelated patent (7,679,637). Let me verify litigation/docket activity specifically for 7,863,717.

US Patent 7,863,717 — Analyst Summary

Search note: I searched for this exact number and for CAFC 2026 docket activity. No litigation or Federal Circuit 2026 docket entry involving U.S. Patent No. 7,863,717 was found — the only CAFC-adjacent hit returned was an unrelated patent (7,679,637, US Patent No. 7,679,637 LLC v. Google LLC, No. 26-236), which I am explicitly not reporting as this patent. Treat the "no litigation found" conclusion as a search-result observation, not a certified litigation-clearance statement.

Bibliographic Data (from the patent record)

Abstract: A package structure of an integrated circuit device comprises a copper foil substrate, an integrated circuit device, a plurality of metal wires and an encapsulation material. The copper foil substrate comprises an IC bonding area, a plurality of conductive areas and an insulating dielectric material. The integrated circuit device is mounted on the surface of the IC bonding area, and is electrically connected to the plurality of conductive areas through the metal wires. The insulating dielectric material is between the IC bonding area and the conductive areas, and is also between two adjacent conductive areas. In addition, the encapsulation material covers the IC bonding area, the conductive areas and the integrated circuit device.

Independent Claims — Plain Language

Claim 1 (package structure): A packaged IC device made on a copper foil substrate (not a ceramic substrate). The copper foil substrate has three functional parts: (a) an IC bonding area, (b) a plurality of conductive areas, and (c) an insulating dielectric material that both separates the IC bonding area from the conductive areas and separates adjacent conductive areas from one another. An IC die sits on the IC bonding area and is electrically connected to the conductive areas. An encapsulation material covers the IC bonding area, the conductive areas, and the IC device.

Claim 10 (manufacturing method): The method counterpart of claim 1 — (i) provide a copper foil substrate having an IC bonding area, conductive areas, and insulating dielectric material located between the IC bonding area and the conductive areas and between adjacent conductive areas; (ii) mount an IC device on the IC bonding area and electrically connect it to the conductive areas; and (iii) overlay encapsulation material on the IC device, the IC bonding area, and the conductive areas.

Dependent claim highlights: adhesive material between die and bonding area (cl. 2), specific adhesive/insulating material chemistries (cl. 3), copper foil thickness 20–50 µm (cl. 4), metal wires with a wire-bonding groove in each conductive area (cl. 5), bumps/flip-chip connection (cl. 6), die-bonding groove in the IC bonding area (cl. 7), and a patterned insulating material layer providing the die-bonding/wire-bonding grooves (cl. 8–9). The specification frames the invention as a thin-package alternative to 1–3 mm ceramic substrates, exploiting copper's better thermal conductivity.

Claim-Drafting Observation

Claim 16 contains a likely drafting error: it recites "the step of mounting the die onto the first conductive film," although no "die" or "first conductive film" was previously introduced in the claim chain (claim 10 recites an "integrated circuit device" and a "copper foil substrate"). This antecedent-basis defect is in the granted text as reproduced. I flag it descriptively — I make no legal conclusion as to its effect on validity or enforceability.

Confidence: High on bibliographic data, claims, and abstract (drawn from the authoritative full text). Lower/uncertain on litigation history: the absence of CAFC 2026 docket activity reflects my searches and should be independently verified against PACER / CourtListener / Docket Alarm if it matters to your analysis.

I'll search for litigation involving US patent 7863717 across patent litigation sources.

Let me search more targeted litigation databases.

Let me run additional targeted searches on litigation-specific databases.

Litigation Search Report — U.S. Patent No. 7,863,717

Bottom line

I found no evidence of any litigation involving U.S. Patent No. 7,863,717. No district court case, ITC Section 337 investigation, PTAB proceeding, or Federal Circuit appeal asserting or challenging this specific patent was identified in the sources searched.

What US 7,863,717 is (for disambiguation)

• Title: "Package structure of integrated circuit device and manufacturing method thereof"
• Patentee/Assignee: Advanced Optoelectronic Technology Inc. (Taiwan)
• Inventors: Shih Hsiung Chan, Shen Bo Lin, Pin Chuan Chen
• Application: US 12/396,898; filed 2009-03-03; granted 2011-01-04
• Priority: TW 097107608A (2008-03-05); TW counterpart TWI398933B
• Legal status (per Google Patents): Expired – Fee Related; lapsed for failure to pay maintenance fees, effective 2019-01-04 (docket entries 2019-02-11 "Lapse for failure to pay maintenance fees," 2019-03-05 "Lapsed due to failure to pay maintenance fee")

Searches performed

I searched litigation-oriented and general patent sources, including queries for the exact number "7863717," the "7,863,717" format, the assignee name combined with "patent infringement lawsuit," and references to the Unified Patents litigation portal (portal.unifiedpatents.com/litigation/caselist), CourtListener/Docket Alarm-style dockets, and PTAB records. The only substantive hits were the patent's own publication pages (Google Patents, USPTO Report, FreePatentsOnline), which show no litigation, no PTAB case, and no "Litigation" tab entries. The Google Patents "Cited By" and "Families Citing" tables list only later patent documents citing the disclosure — these are citations, not litigation.

Notably, the patent's forward-citation and family records indicate the patent family was active in prosecution/citing art but never surfaced in any asserted-patent docket that I could locate.

Important caution — do NOT confuse these similar identifiers

Several search results mention a "'786 patent," but none of them are US 7,863,717:

1. PTAB papers (IPR petitions) referencing "the '786 Patent" — described as a pre-AIA patent originally owned by Netherlands-based Koninklijke Philips N.V., with a British-citizen inventor. That profile does not match US 7,863,717 (Taiwan assignee; Taiwanese inventors; different subject matter). This is a different patent whose number merely ends in "786."
2. A New Jersey district court complaint referencing "the '786 Patent" in plecanatide oral tablets (an ANDA/pharma case) — clearly unrelated to an IC packaging patent.
3. Swarco v. SISS (UPC) referencing EP2643717B1 — an unrelated European LED sign patent, matching only on the "264 / 3717" digits.
4. Honeywell U.S. Patent No. 5,280,371 ("'371 patent") — unrelated.

I flag these because the rule is to interpret identifiers literally and not auto-correct; "7863717" is not the same as "the '786 patent" or "the '371 patent."

Litigation table

Confidence and limitations

• This conclusion rests on the searches available to me and on the patent's own litigation/legal-status records, which show only fee-payment events and no case data. I have no high-confidence, affirmative evidence that any suit was ever filed on this patent.
• I could not complete a full-text, date-bounded sweep of PACER, the Unified Patents litigation caselist, CourtListener RECAP, or Docket Alarm (my tool calls were capped). A definitive negative would require running the exact patent number through those dockets directly.
• Given the patent expired in 2019 for non-payment of maintenance fees and the assignee is a Taiwanese optoelectronics firm, the absence of litigations is plausible — such patents are typically never asserted.
• I do not know with certainty that zero suits exist; if a suit exists, it would most likely be a small Taiwan-related or international matter not indexed in the U.S.-focused sources I reached. I am not fabricating any case number, venue, or outcome.

Recommendation: To confirm a true negative, run "7,863,717" directly in PACER (all district courts), the Unified Patents litigation caselist, CourtListener RECAP, and Docket Alarm, and check the USPTO Patent Center "Litigation" tab.

Proceedings overview

Total AIA trial proceedings on file for US 7,863,717: zero. The USPTO Open Data Portal structured block supplied with this assignment returns no IPR, PGR, or CBM proceeding for this patent, and my independent web searches surfaced no petition, institution decision, Final Written Decision, or Federal Circuit appeal naming US 7,863,717 as the challenged patent. The breakdown is therefore 0 active / 0 claims invalidated / 0 claims sustained / 0 settled / 0 institution denials — and there is no patentability outcome to report because no trial was ever instituted.

The bottom-line defensive posture is unusual and stronger than a "hardened patent" story: this patent is not merely un-attacked, it is dead by operation of law. USPTO legal events show the patent lapsed for failure to pay maintenance fees, with the lapse posted 2019-02-11 and effective 2019-01-04 (35 U.S.C. § 41(b); 37 C.F.R. § 1.362), and Google Patents records the current status as "Expired – Fee Related" with a nominal adjusted expiration of 2029-04-08. Any demand letter asserting claims 1–20 today is asserting claims of an expired, unenforceable-for-prospective-relief patent.

No proceedings to report

Because the canonical structured block is empty, I am not generating the per-proceeding template — inventing a docket number would be exactly the failure mode this assignment warns against. Two verification steps were run instead:

1. Structured data (canonical). USPTO ODP: no AIA trial proceedings as of the most recent ingest. This is consistent with the patent's history — it was granted 2011-01-04, maintained once (fee payment recorded 2014-07-03, year 4), then abandoned at the next maintenance window in 2019. PTAB challenges are petitioner-driven, and there is no evidence in the record of any assertion campaign that would have supplied a petitioner with the § 315(b) motivation or standing to file.

2. Web search (supplemental). Searches for the patent number, the assignee (Advanced Optoelectronic Technology Inc., Taiwan), and the subject matter (copper-foil-substrate IC/LED package with die-bonding and wire-bonding grooves) surfaced no petition, no institution decision, and no FWD for this patent. The patent's own Google Patents record shows only one cited reference — US 2009/0206358 A1, "Package structure of compound semiconductor device and fabricating method thereof," also Advanced Optoelectronic Technology — which is a family-level citation, not a challenge.

A mis-identification to flag explicitly. Web search returns a PTAB patent owner's preliminary response repeatedly arguing about "the '786 Patent," involving parallel "Texas Cases," pre-AIA § 102(e) references to Tu, Suzuki, and Iida, an inventor described as a British citizen, and original ownership by Netherlands-based Koninklijke Philips N.V. That is a different patent, not US 7,863,717. US 7,863,717 is a Taiwan-priority (TW097107608, 2008-03-05; US filed 2009-03-03), Taiwan-assigned patent with Taiwanese named inventors (Shih Hsiung Chan, Shen Bo Lin, Pin Chuan Chen) and a copper-foil-substrate subject matter. Anyone running a docket screen on a "'786 patent" string should confirm the full number before treating that paper as relevant. I did not locate any proceeding against 7,863,717 itself and I am not asserting that a specific one exists.

Strategic summary

Claim status: everything is UNTESTED, and almost everything is MOOT. No claim of US 7,863,717 has been canceled, confirmed, or amended in any AIA trial — the patent's claims 1–20, including independent claim 1 (copper foil substrate with IC bonding area, conductive areas, and interposed insulating dielectric material) and independent claim 10 (the corresponding manufacturing method), stand exactly as granted on 2011-01-04. But "standing as granted" is not the operative fact. The patent expired on 2019-01-04 for nonpayment of maintenance fees, so claims 1–20 cannot support prospective relief (no injunction, no ongoing royalty) and can only matter for past damages within the § 286 six-year lookback and before the expiry date. Practically, the monetizable window closed in early 2019.

Estoppel landscape: empty — and that cuts both ways. Because no IPR was instituted, no petitioner is subject to § 315(e)(2) estoppel on this patent, and you are not either. There is no prior PTAB record to inherit, no claim construction (Phillips or otherwise) already litigated, and no FWD findings to use offensively or defensively. The entire invalidity case is unbuilt. Two practical notes: (a) the Board has historically been willing to institute IPRs on expired patents (claim construction proceeds under Phillips and no amendment is available), so an IPR is not categorically unavailable — but the cost-benefit almost never justifies it where no damages case exists; and (b) if you face an assertion based on pre-2019 conduct, your invalidity grounds are entirely open, including § 102(a)/(b) art, § 102(e) art, § 103 combinations, and § 112 written-description/enablement attacks on the broad "copper foil substrate … insulating dielectric material" genus — none of which has been tested.

Pattern signals: none. No repeat petitioner, no patent-owner appeal activity, no defensive aggregator (no Unified Patents, RPX, or similar) in the chain — consistent with a patent that was never a serial-assertion asset. The only related activity is internal: a same-assignee family member, US 2009/0206358 A1, and a companion Taiwan right, TWI398933B, both of which issued and appear to have been allowed to lapse with the US case rather than litigated. Advanced Optoelectronic Technology's later activity in the family is a light-emitting-device line (e.g., TW201011936A, cited as a family citing application), not enforcement of the '717 claims.

Recommended next steps

• If you received a demand letter citing US 7,863,717: lead with expiry, not invalidity. Quote the USPTO legal events: fee-payment procedure reminder mailed 2018-08-27; lapse for failure to pay maintenance fees 2019-02-11, effective 2019-01-04; "PATENT EXPIRED FOR FAILURE TO PAY MAINTENANCE FEES." Confirm on the USPTO Patent Center / Global Dossier record before responding, and confirm no petition to revive under 37 C.F.R. §§ 1.378 or 1.183 was granted (none appears in the record as of ingest). A lapsed patent supports neither an injunction nor ongoing royalties.
• If past damages are threatened: scope the exposure. The recoverable window runs at most from six years before the complaint (§ 286) and terminates at 2019-01-04. Preserve § 287 marking and § 282 defenses, and note that absent an active IPR or litigation, there is no § 315(e) estoppel to navigate — meaning the full § 102/§ 103/§ 112 playbook remains available if you need it.
• If you are considering filing an IPR anyway: it is legally possible against an expired patent (for the residual past-damages theory), but weigh it against the fact that the Board has nothing to review that a district court motion for summary judgment on expired-patent damages wouldn't reach more cheaply. Confirm current Board practice on expired-patent institution on a live docket before committing; I am not aware of a rule change prohibiting it, but this is a point to verify rather than assume.
• Docket hygiene: before relying on any search hit containing "'786," verify the full patent number. The PTAB filings that mention "the '786 Patent" in the search results above concern a Koninklijke Philips N.V.–origin asset, not Advanced Optoelectronic Technology's US 7,863,717.

Sources: US 7,863,717 on Google Patents (legal events, family, citations) · USPTO Patent Trial and Appeal Board E2E / PTACTS · USPTO Patent Center · CourtListener (Federal Circuit docket search) — queried for a matching appeal and returning no result for this patent.

Confidence and limits: I have high confidence in the zero-proceeding finding, since it rests on the canonical structured block plus independent searching. I have high confidence in the 2019 lapse because it is drawn from the USPTO legal events reproduced in the authoritative full text. I cannot rule out an unpublished or very recently filed petition that neither ODP nor search has indexed; if one exists, it would not change the expiry analysis, and I have not asserted any proceeding number that I could not verify.

I'll research the assignment record for US 7,863,717 and the entities in the chain.

Let me dig into the assignment records and the Dominion Harbor / Edison Innovations acquisition.

Ownership & Assignment Analysis — US 7,863,717 B2

Source note / limitation: My tooling for this task returned web-search results only; I could not directly execute a query against the USPTO Assignment Center API. The assignment data below is drawn from the USPTO-derived legal-events record reproduced on Google Patents (https://patents.google.com/patent/US7863717/en) and from public filings. The Assignment Center landing pages for independent verification are https://assignmentcenter.uspto.gov/ and https://assignment.uspto.gov/patent/index.html (search by patent number 7863717). The recorded correspondent attorney is not exposed in the sources I could retrieve — I have not filled that field by guessing.

Inventors

Patterns: No unusual inventor-departure pattern is evidenced. This is an ordinary employee-inventor → employer assignment. The assignment was executed 2009-02-27, i.e. ~12 months after the TW priority filing (2008-03-05) and five days before the US filing (2009-03-03) — normal sequencing for a foreign-priority US filing, not a departure/fire-sale tell. The three inventors are the only named inventors on the patent; I did not find evidence that any left AOT within 12 months of filing (and AOT's employee roster of ~800–1,100 across that period gives no signal either way).

Original assignee

Advanced Optoelectronic Technology Inc. ("AOT"), Hsinchu (Hukou) Industrial Park, Taiwan. TWSE-listed (ticker 3437).

• Primary line of business: LED chip/package development, manufacturing and sales — SMD LEDs, backlight/sensor/automotive modules, Mini/Micro LED. It is an operating manufacturer, not an IP-holding shell.
• History / naming: Founded October 1999 as Advanced Development Optoelectronics Co., Ltd.; the company's own profile states it changed its name to Advanced Optoelectronic Technology, Inc. in 2010 (https://www.aot.com.tw/en/). Flagged discrepancy: the 2009 assignment record already names the assignee as "ADVANCED OPTOELECTRONIC TECHNOLOGY INC., TAIWAN," and no separate Change of Name conveyance is recorded against this patent. Either the English trade name was in use before the formal 2010 change, or the corporate record is imprecise. I treat this as a descriptive gap, not a legal conclusion.
• Ownership: Foxconn / Hon Hai Group was identified as a major stockholder in the company's 2019 investor deck (https://emops.twse.com.tw/nas/STR/343720191125E002.pdf).
• Does it ship a product embodying the claims? AOT indisputably ships LED packages and modules. Whether a specific commercial product practices these claims (a copper-foil-substrate IC package) is not confirmable from public sources — I will not assert it.
• Current status: operating. AOT held its 2025 investor conference and continues trading (FY2024 revenue ≈ NT$2.04bn; FY2025 loss per its annual report). Not dissolved, not in bankruptcy.

Assignment timeline

Only one assignment is recorded against US 7,863,717. There is no post-issuance chain (no LLC transfers, no security interests, no releases, no corrections) in the record I could retrieve.

• 2009-02-27 (executed) / 2009-03-03 (recorded) — Reel 022337 / Frame 0940
  • Conveyance: Assignment — "ASSIGNMENT OF ASSIGNORS INTEREST" (see USPTO/Google Patents legal events; assignment effective date 20090227)
  • Assignor: Chan, Shih Hsiung; Lin, Shen Bo; Chen, Pin Chuan (all three inventors, jointly)
  • Assignee: Advanced Optoelectronic Technology Inc., Taiwan
  • Correspondent: Not available in the sources I could retrieve. I searched for the recording attorney of record and found none published; I am not inferring one. (This is the field to pull from the Assignment Center's record image or from PATS/Patent Center if it matters.)
  • Context: Original inventor-to-employer assignment incident to filing — standard, not a reorg, securitization, or transfer-to-asserter.

Post-issuance (no assignment, but material status events):

• 2014-07-03 — Maintenance fee paid (4th year).
• 2018-08-27 — Maintenance-fee reminder mailed.
• 2019-02-11 — Patent expired for failure to pay maintenance fees (lapse effective 2019-01-04).
• Google Patents lists an "adjusted expiration" of 2029-04-08, which is the maximum term assuming fees had been paid. The operative status is Expired – Fee Related (lapsed 2019).

Notable recent (not-yet-recorded, and unconfirmed as to this patent): On 2026-09-10, Edison Innovations, a Dominion Harbor Enterprises (DHE) company, announced it had acquired a portfolio of "over 20 patents" from AOT for the display/lighting sector (e.g., https://www.theglobeandmail.com/investing/markets/markets-news/ACCESS%20Newswire/[4531998](/patent/4531998)/edison-innovations-acquires-strategic-patent-portfolio-from-advanced-optoelectronic-technology/). The release does not enumerate the acquired patent numbers, so I cannot confirm 7,863,717 is among them — and because this patent lapsed in 2019 it is an unlikely acquisition target for a royalty program. As of today no assignment has been recorded against 7,863,717 reflecting that deal. Treat this as a watch item, not a finding.

Timeline diagram

timeline
    title Ownership of US 7863717
    2008 : TW priority application filed
    2009 : Inventors assign rights to AOT
         : US application filed
    2011 : Patent issued to AOT
    2019 : Patent lapses for unpaid fees
    2026 : AOT sells portfolio to Edison unit

NPE / troll-pattern signals

1. Shell-entity transfer — not present. The only recorded transfer is inventor → operating manufacturer AOT (Reel 022337/Frame 0940, 2009). No "IP/Holdings/Ventures" LLC, no registered-agent address, no single-purpose entity appears on the chain of record. Caveat: the Sept 2026 Edison Innovations / Dominion Harbor acquisition of an AOT portfolio is a transfer to a known licensing house, but it is portfolio-level, unconfirmed for this patent, and post-dates the patent's 2019 lapse.

2. Known asserter in the chain — not present on the record. No Acacia, Marathon, IV, IPNav, Wi-LAN, Conversant/Mosaid, Vringo, Pendrell, Round Rock, Spangenberg entity, etc., appears. Unclear/forward-looking: Dominion Harbor / Edison Innovations is a recognized IP-monetization firm (CEO David Pridham; contact Robert Kelly), and it has been actively licensing LED/KSF portfolios (Ennostar, Lumens, Bridgelux) through 2026. If a future assignment to Edison Innovations is recorded here, this signal would flip — but it is not a finding today.

3. Repeat correspondent across the chain — not assessable / not present. With only one assignment link, recurrence cannot exist, and the correspondent of record was not retrievable. No correspondent name is cited because none was found.

4. Cascading transfers (<24 months, chained LLCs) — not present. One transfer in 2009; no subsequent recorded movement.

5. Pre-litigation transfer — not present / N/A. No infringement suit naming this patent was found (consistent with the prior section's finding, which I carry forward). There is no assignment within 6 months before any suit. Additionally, the patent lapsed in 2019, so it cannot ground a suit for post-expiration conduct.

6. Bankruptcy fire-sale — not present. AOT never filed bankruptcy and remains a going concern.

7. Privateering — not present. No evidence AOT transferred this patent to an NPE to assert against competitors.

8. Defensive aggregator (anti-NPE) — not present. The chain does not terminate at RPX, AST, LOT, Unified Patents, or OIN. The patent was simply abandoned by fee lapse, which leaves it in the public domain for its remaining nominal term rather than "neutralized" by a defensive aggregator.

Verdict

Insufficient data (chain consists of only the original inventor-to-employer assignment; no post-issuance transfers recorded).

Justification: The sole recorded assignment is the three inventors → Advanced Optoelectronic Technology Inc. at Reel 022337 / Frame 0940, executed 2009-02-27 and recorded 2009-03-03 — a routine filing-time assignment to an operating LED manufacturer, with no subsequent shell-entity transfer, no known asserter, no cascading LLCs, no bankruptcy sale, and no defensive-aggregator terminus. The patent expired 2019-02-11 for non-payment of maintenance fees (lapse effective 2019-01-04), which independently forecloses the classic transfer-then-assert pattern. The only forward-looking wrinkle is the 2026-09-10 Edison Innovations (Dominion Harbor) acquisition of an un-enumerated 20+ patent AOT portfolio, which may touch this patent but is unconfirmed and, given the 2019 lapse, unlikely to be asserted; I flag it as a monitor item rather than a signal.

Verify at: https://assignmentcenter.uspto.gov/ (search patent number 7863717) — specifically to pull (a) the correspondent of record for Reel 022337/Frame 0940, and (b) any 2026 assignment to Edison Innovations / Dominion Harbor that post-dates my sources.

Prior-Art Analysis — U.S. Patent No. 7,863,717 (US 12/396,898)

Scope and method note. This analysis relies on the authoritative full text of US 7,863,717 supplied in the record (Google Patents reproduction of the USPTO granted patent and its citation tables). I was not able to open the USPTO PatentCenter/PAIR file wrapper or the PTO-892 "Notice of References Cited" directly in this session, so I am working from the citation tables published on the patent record itself. I am not reporting results for any similar-numbered patent (e.g., 7,679,637, the "786 patent," the '371 patent) — those are distinct identifiers and are excluded.

1. Citation inventory — what the record actually shows

The record for 7,863,717 distinguishes several categories, and only some of them are prior art:

⚠️ Caveat on completeness: the record shows exactly one examiner citation. A real PTO-892 may list additional references (including non-patent literature) that did not propagate into these tables. Treat the list below as the citation set documented on the record, not a certified exhaustive PTO-892 reproduction.

2. Reference-by-reference analysis

Reference A — US 2009/0206358 A1 (the sole examiner citation)

• Full citation: U.S. Patent Application Publication US 2009/0206358 A1, "Package structure of compound semiconductor device and fabricating method thereof," Advanced Optoelectronic Technology Inc. (Hsinchu Hsien, Taiwan). Application 12/370,923; filed 2009-02-13; published 2009-08-20; granted as US 7,893,528 B2 on 2011-02-22. TW priority TW 097105846 (2008-02-20). Examiner of record: Tan N Tran. Google Patents: https://patents.google.com/patent/US20090206358A1/en
• Relationship to '717: same assignee family; different statutory invention (compound-semiconductor/LED package vs. "integrated circuit device" package), but a near-identical disclosure — same thin-film/copper-foil substrate architecture, same 20–50 µm range, same material lists, same die-bonding/wire-bonding groove concepts.
• Brief description: A thin-film (copper foil or metal film) substrate having a first conductive film, a second conductive film, and an insulating dielectric material therebetween; a die mounted on the first conductive film; metal wires (or bumps) connecting the die to the conductive films; wire-bonding grooves; an optional die-bonding groove (optionally with reflective layer); an optional patterned insulating material layer carrying the die-bonding and wire-bonding grooves; and a transparent encapsulation material. Substrate thickness 20–50 µm.
• § 102 assessment: This is by far the most material reference, and it maps element-for-element onto most of the '717 disclosure. It potentially bears on claims 1, 2, 3, 4, 5, 6, 7, 8, 9 (structure) and claims 10, 11, 12, 13, 14, 15, 17 (method).
  • However — priority-date caveat that cuts against a clean § 102 rejection. Under pre-AIA § 102(e), a published U.S. application is prior art only as of its U.S. filing date, 2009-02-13. That date is after '717's claimed effective date (TW priority 2008-03-05). Its publication date (2009-08-20) is far too late for § 102(a)/(b). So if '717 is fully entitled to its TW 097107608 priority, the '358 is not obviously § 102(e) art at all. It would only become available under § 102(e) if a '717 claim falling outside the TW priority disclosure were being examined. I flag this as the single most important issue to verify.
  • Element-gap for strict anticipation: the '358's substrate is described as a first conductive film and a second conductive film; '717 claim 1 requires "a plurality of conductive areas" with the insulating dielectric "between an adjacent pair of the conductive areas." Whether the '358's two-film structure discloses an IC bonding area plus a plurality of conductive areas is arguable, which weakens a strict § 102 identity but supports a § 103 combination.
• Cross-reference to the prior summary: you flagged claim 16's recital of "the step of mounting the die onto the first conductive film" as an antecedent-basis defect (no "die"/"first conductive film" earlier in the chain). The search results strongly corroborate your observation: "first conductive film" and "second conductive film" are the '358 sibling's vocabulary, not '717's ("copper foil substrate / IC bonding area / conductive areas"). That is consistent with copy-paste carryover from the sibling disclosure. I flag this descriptively only — no legal conclusion.

Reference B — JP3554650B2

• Full citation: JP 3554650 B2, "回路基板" ("Circuit board"), Sony Chemical Corp. (ソニーケミカル株式会社). Application rendered as JP08743397A; filing/priority 1997-03-21; granted 2004-08-18; anticipated expiration 2017-03-21; status Expired – Fee Related. https://patents.google.com/patent/JP3554650B2/en
• Brief description: A circuit board for mounting a semiconductor element, aimed at fine-pitch wiring and high-density mounting. A conductive circuit (105) is buried so as not to be exposed from both faces of insulating layers (103, 104); conductive passages/vias (106, 107) arranged in offset pairs; bumps (108, 109); a film carrier (102) whose bump contacts an electrode on the semiconductor element; an insulating resin layer (113) covering the element. It expressly aims to eliminate the adhesive-bonding step between the film-like insulating base and the conductor circuit, and to control reflow so only the surface of the board-connection metal protrusion melts.
• § 102 assessment: Not anticipatory on its own. It is a printed publication well before the 2008-03-05 priority date (granted 2004), so it qualifies as available art (§ 102(b) for the 2009-03-03 U.S. filing — publication more than one year earlier). But it does not disclose the '717 combination of (i) a copper-foil substrate partitioned into an IC bonding area plus a plurality of conductive areas with insulating dielectric between adjacent conductive areas, (ii) a die mounted on the IC bonding area, and (iii) an encapsulant over all three. Its bumps/vias/film-carrier teaching is more pertinent to claims 6 and 17 (flip-chip/bump connection; bonding method) as a § 103 secondary reference than to any § 102 anticipation.

Reference C — JP3962039B2

• Full citation: JP 3962039 B2, "配線回路形成用基板、配線回路基板及び金属薄膜層の形成方法" ("Wiring circuit forming substrate, wiring circuit substrate, and method for forming metal thin layer"), Nitto Denko Corporation (日東電工株式会社). Application JP2004180245A; filed 2004-06-17; granted 2007-08-22; status not active / Expired – Fee Related. https://patents.google.com/patent/JP3962039B2/en
• Brief description: Directed to a substrate for forming a wiring circuit and a method of forming a metal thin layer on such a substrate (metal-thin-layer/seed-layer formation and wiring-circuit patterning). It concerns the metallization/fabrication side of circuit substrates rather than a packaged IC with an encapsulant.
• § 102 assessment: Not anticipatory. Available as art (granted 2007-08-22, before the 2008-03-05 priority date), but it does not disclose the claimed packaged-device combination. Its possible relevance is narrow — a § 103 secondary reference touching the "metal thin layer / conductive area formation" and, at most, elements of claim 11's substrate-manufacture steps (form slots / fill insulating material) if it shows analogous metal-layer-on-insulator fabrication. I could not retrieve its full claim set, so I rate this low-confidence as to any specific mapping.

Reference D — JP2007201254A

• Full citation: JP 2007-201254 A, "半導体素子内蔵基板、半導体素子内蔵多層回路基板" ("Semiconductor element built-in substrate, semiconductor element built-in type multilayer circuit board"), Ibiden Co., Ltd. Filed 2006-01-27; published 2007-08-09.
• Brief description: A substrate with a semiconductor element built in an opening/cavity of an insulating substrate; conductor pattern on the substrate; the element accommodated in the opening; insulating layer(s) covering the element; via conductors connecting the element's terminals and the conductor pattern; extendable to a multilayer (built-up) circuit board.
• § 102 assessment: Potentially relevant, but not a clean anticipator. Published 2007-08-09, i.e., before the 2008-03-05 priority date and more than one year before 2009-03-03 — so it is available art. Its accommodation of a semiconductor element in a recess/opening of the substrate is the closest thing in the citation set to '717's die-bonding groove concepts, making it a candidate § 103 reference against claims 7 and 13 (die-bonding groove, mounting the IC therein). It does not disclose the copper-foil IC-bonding-area/conductive-area/insulating-dielectric partition of claim 1 or the encapsulant-over-all architecture, so § 102 anticipation of the independent claims is not supported.

3. § 102 mapping table (best-effort)

Assessment of the citation set as a whole: on the documented record, none of the references is a clean, single-reference § 102 anticipator of independent claim 1 or claim 10. The examiner-cited US 2009/0206358 A1 is the only reference that materially overlaps the claimed subject matter, and even it carries both (a) a § 102(e) date problem tied to the TW priority claim, and (b) a possible "plurality of conductive areas" gap. The three JP documents are better characterized as § 103 secondary references (bumps/bonding; metal-layer formation; element-in-recess).

4. Limitations and things to verify

• I could not pull the actual PTO-892/file wrapper for US 12/396,898. The existence of additional examiner-cited art (especially non-patent literature) cannot be ruled out. Verify directly in USPTO PatentCenter.
• I did not verify whether the '358 sibling's earlier TW priority (2008-02-20) vs. '717's TW priority (2008-03-05) affects "by another"/§ 102(e) treatment; both are same-assignee. This is the pivotal § 102 question and should be checked against the file history.
• Descriptions of JP3962039B2 and JP2007201254A are drawn from citation-table snippets and abstract-level data; I could not read their full claim sets, so any claim mapping to them is low confidence and should be confirmed against the JP full texts.
• I did not find US 2004/0090756 (the "high integral package structure" discussed in the sibling '358's background) cited against '717; it appears in the '358 specification, not in the '717 citation record. I mention it only to prevent cross-contamination between the two families.
• This is a technical prior-art mapping for analysis, not a legal opinion on validity, patentability, or enforceability.

Bottom line: the single examiner citation of record, US 2009/0206358 A1, is the most relevant prior art and potentially implicates most claims (1–15, 17) — but its § 102(e) availability hinges on the priority-date question and it has an arguable element gap; the three JP family citations (JP3554650B2, JP3962039B2, JP2007201254A) are secondary references, none of which anticipates an independent claim on its own.

I'll ground this obviousness analysis in the actual prior-art references listed on the patent's page. Let me pull details on each.

Let me get more detail on the JP references and potential US counterparts, plus the US 2004/0090756 reference that the closest prior art itself criticizes.

Obviousness Analysis — U.S. Patent No. 7,863,717 B2 under 35 U.S.C. § 103

Builds on the prior Bibliographic, Claim, and Litigation sections. This section does not repeat claim language except where needed for the element-by-element mapping. No legal conclusion as to validity is expressed; this is a technical obviousness assessment.

0. Framework, Governing Law, and Level of Ordinary Skill

Statute: Because the application was filed 2009-03-03 (priority 2008-03-05), this is a pre-AIA § 103(a) analysis. The governing test is Graham v. John Deere Co., 383 U.S. 1 (1966): (1) scope and content of the prior art; (2) differences between the prior art and the claims; (3) level of ordinary skill; (4) secondary considerations. The controlling combination standard is KSR Int'l Co. v. Teleflex Inc., 550 U.S. 398 (2007) — "the combination of familiar elements according to known methods is likely to be obvious when it does no more than yield predictable results," and motivation may be found in "the design incentives and other market forces that prompt variations."

Hypothetical PHOSITA (as of March 2008): A packaging engineer with a B.S. in electrical engineering, mechanical engineering, or materials science and roughly 2–4 years of experience in semiconductor or optoelectronic device packaging — or an M.S. with less experience — familiar with: (a) laminate/lead-frame/ceramic substrate packaging; (b) die attach (adhesive and eutectic); (c) wire bonding and flip-chip/bump interconnection; (d) transfer molding, dispensing, and encapsulation materials; and (e) substrate-level patterning processes (photolithography, plating, etching, drilling/punching) and the trade-off between substrate thickness, rigidity, and heat spreading.

Important procedural note on the art of record: The page's "Prior Art" listings contain one examiner-cited reference (US 2009/0206358 A1) and three "Family Cites" references (JP 3554650 B2, JP 3962039 B2, JP 2007-201254 A). The forward citations ("Cited By," "Families Citing," "Similar Documents") all post-date the 2008-03-05 priority and therefore cannot be § 103 prior art; they are not used below.

1. The Prior Art Available for Combination

2. Ground 1 — Claim 1 Obvious over US 2009/0206358 A1 (Primary Reference)

2.1 Element-by-element mapping of claim 1

2.2 The only real differences, and why they are not patentable differences

1. "Integrated circuit device" vs. "compound semiconductor die." The '717 patent claims an "integrated circuit device" generically; '717's own FIG. 2C is a flip-chip silicon-style package. Mounting a silicon IC on the identical substrate/attach/wire-bond/encapsulate architecture is a substitution of one known semiconductor die type for another where the substrate, attach, interconnect, and encapsulation functions are unchanged — a classic KSR predictable variation. There is no asserted criticality of the die type.
2. "Copper foil substrate" vs. "thin film substrate." The reference's conductive films expressly include copper and its background's conventional device uses copper foils. Nominally different label, same structure.
3. Claim 1 does not require the grooves or bumps — so the extra features of the reference are surplusage relative to claim 1.

Conclusion on Ground 1: Claim 1 would have been obvious over US 2009/0206358 A1 alone. The reference is, structurally, the same package architecture applied to a different semiconductor die — the paradigm KSR case.

⚠️ Two caveats that must be flagged (neither is a technical mismatch):

• Priority / § 102 status. US 2009/0206358 A1 published 2009-08-20, after the '717 filing (2009-03-03) and priority (2008-03-05), and its TW family publication (TW 200937667 A) is dated 2009-03-16. If its pre-AIA § 102(e) date is its US filing date (≈ Feb 2009 — I could not verify the exact date in this session), then under In re Hilmer the reference's § 102(e) date is after the '717 priority date. That would make it § 102(e) art only, or not art at all.
• Pre-AIA § 103(c)(1) common ownership. The reference and the '717 patent are both owned by Advanced Optoelectronic Technology Inc. If US 2009/0206358 A1 qualifies as prior art only under § 102(e)/(f)/(g), pre-AIA § 103(c)(1) would disqualify it from a § 103 rejection where the subject matter and the claimed invention were commonly owned. This may explain why the examiner cited it of record without (to my knowledge) building the rejection on it. I could not confirm inventor overlap or the exact § 102(e) date, so I state this as an unresolved issue rather than a conclusion.

3. Ground 1 (continued) — Dependent Claims 2–9 Over US 2009/0206358 A1

4. Claims 10–20 (Method) — Ground 1 & Ground 3

5. Ground 2 — The Legally Robust Combination: JP 3554650 B2 + JP 2007-201254 A + JP 3962039 B2 (+ Admitted Prior Art)

Because of the § 102(e)/§ 103(c) uncertainties attending US 2009/0206358 A1 (both are commonly owned by Advanced Optoelectronic Technology Inc.), a fallback § 103 ground built from third-party art is cleaner — all three JP documents published well before 2008-03-05 and are § 102(b) printed publications owned by different entities (so § 103(c) does not apply).

Combination: JP 3554650 B2 (thin circuit board for IC mounting, with IC-side electrodes, motherboard-side electrodes, and metal bumps on a thin polyimide insulating base) in view of JP 2007-201254 A (substrate with a recess for the semiconductor device, an insulating layer with openings, and wiring on the insulating layer) in view of JP 3962039 B2 (patterning thin conductive areas on a thin insulating layer by resist/plating/etching), further in view of the admitted prior art in '717.

• Claim 1: JP 3554650 supplies the thin insulating-base-plus-conductor-area circuit board for an IC; JP 2007-201254 supplies the die-accommodating recess architecture and insulating layer with openings; the admitted prior art supplies encapsulation-over-die-and-conductors and the copper-foil carrier concept. The only missing nominal element is calling the carrier a "copper foil substrate" — and the '717 specification admits that a 20–50 µm copper foil is a supplied starting material, making that a mere material substitution.
• Claim 4: JP 3962039 B2's 25 µm polyimide base + 10 µm plated conductor establishes thin-substrate practice; 20–50 µm copper foil is within routine design choice.
• Claims 7–9: JP 2007-201254 A teaches the die-recess (die-bonding groove); JP 3962039 B2 teaches defining grooves/patterns by photoresist + plating + etching (the electroforming analogue).
• Claims 5, 6, 15, 17: JP 3554650 B2's metal protrusions/bumps and the flip-chip context supply the bump limitation; wire-bonding grooves are a conventional loop-height-reduction expedient.

I rate this ground lower on the "claim 1 completeness" axis than Ground 1 (it requires a three-way combination and some admitted-art supplementation) but higher on legal availability, because none of the JP references is commonly owned or § 102(e)-only.

6. Motivation to Combine (the KSR / Graham factor most decisive here)

A PHOSITA in March 2008 would have had multiple, mutually reinforcing motivations:

1. Identical problem, identical field. '717's own background states the problem verbatim: ceramic substrates are 1–3 mm thick and "cannot meet the new requirements of the thin-type package structure," and are "inferior in heat conductivity and heat dissipation." US 2009/0206358 A1's background states the same problem ("the total thickness… cannot be reduced further" and "poor heat dissipation"). Where the references address the same problem, the motivation is inherent (cf. In re Wood; KSR).
2. Design incentive / market demand. Consumer-electronics thinness ("the current trend of consumer electronic products is toward lightweight, small packages"). KSR expressly permits motivation from "design incentives and other market forces."
3. Known technique, same predictable result. Replacing a ceramic/PCB substrate with a copper carrier is expressly motivated by copper's superior thermal conductivity — a recognized property, not a discovery by the '717 inventors. Similarly, forming grooves to lower the second-bond position and reduce wire loop height is a technique the sibling reference already applies with the same stated rationale.
4. Same-inventor-chain, same terminology. The overlap of "insulating dielectric material," "die-bonding groove," "wire-bonding groove," "loop height," and "thin package structure" between '717 and US 2009/0206358 A1 evidences that the two are the same design applied to two device types — a strong indication of obviousness (this bears on Ground 1's technical sufficiency even if Ground 1's legal availability is compromised).
5. No teaching away. US 2009/0206358's criticism is directed to the temporary-substrate/laser-removal approach of US 2004/0090756 (complicated and costly) — not to copper-foil carriers. Nothing in the art discourages a copper-foil carrier; to the contrary, copper foil is lauded for heat dissipation.

7. Secondary Considerations (Graham Factor 4)

• No evidence of unexpected results appears in the record. The stated benefits ("reduce the loop height," "further thinning," "improved heat dissipation," "shorter current paths") are expected consequences of the recited features, not surprising ones.
• No evidence of commercial success with a demonstrated nexus to the claims, industry praise, copying, licensing, or long-felt-but-unsolved need appears in the record.
• Countervailing fact: the patent expired 2019-01-04 for non-payment of maintenance fees (events dated 2019-02-11 and 2019-03-05) and, per the Litigation section, was never asserted. This is weak, non-dispositive circumstantial evidence consistent with low commercial significance, and does not by itself rebut the Graham analysis; but if any objective indicia are later proffered, a nexus to the claimed substrate/groove structure would have to be shown.

8. Net Assessment by Claim

Most likely point of attack on the patent: claim 1 (which is broad and structurally met by the same-assignee sibling publication), with claims 8–9 as the cleanest electroforming-disclosure hit.

Weakest link in the analysis: whether US 2009/0206358 A1 is available as § 103 art. If it is disqualified (common ownership + § 102(e)-only status), Ground 1 collapses to Ground 2, which requires a three-way JP combination plus admitted-art supplementation and is correspondingly more contestable.

9. Explicit Limitations / Confidence

• Confidence: High on the technical mapping of US 2009/0206358 A1 (and its TW family member TW 200937667 A) to claims 1–20 — the element names and purposes match almost verbatim, and the reference is cited of record.
• Confidence: High that JP 3554650 B2, JP 3962039 B2 (JP 2006-005176 A), and JP 2007-201254 A are § 102(b) printed publications predating 2008-03-05.
• Confidence: Moderate that the JP three-way combination fully anticipates claim 1 rather than merely rendering it obvious — the "copper foil substrate" nomenclature and the specific filled-slot architecture require the admitted-art/common-knowledge bridge.
• Not verified this session (treat as open): (a) the exact US filing date of the US 2009/0206358 A1 application, which determines its pre-AIA § 102(e) date; (b) whether the inventors of the two commonly owned applications overlap (relevant to "developed by another person" under pre-AIA § 103(c)); (c) the bibliographic detail of JP 2007-201254 A beyond its title, assignee, and abstract, since Ibiden's content was confirmed only through the closely related US 7,777,328 B2 line.
• Not fabricated: I have not asserted any specific § 102(e) date, any specific § 103(c) ownership finding, or any litigation/objective-indicia fact. Where the answer depends on those, I have said so.

Recommendation before relying on this: pull the file wrapper of US 12/396,898 for the examiner's actual rejections and the applicant's responses/remarks, confirm the US filing date of the 2009/0206358 application, and confirm common ownership/inventor overlap as of the '717 invention date. Those three items determine whether the strongest ground (Ground 1) is available or whether the analysis must stand on Ground 2.