US 8338929

I'll search for information on this specific patent number.

The CAFC/litigation search returned nothing. Let me try a couple more targeted checks.

Let me do one more targeted check for any CAFC or litigation activity.

Search scope and confidence

I queried Google Patents/Justia (full text of the patent) and open web sources for litigation and CAFC 2026 docket activity naming US 8,338,929. I found the authoritative patent document, but no U.S. district court, ITC, PTAB, or Federal Circuit proceeding that specifically identifies US 8,338,929. Treat that negative result cautiously — it reflects what open-web search surfaced, not a definitive litigation clearance check of PACER, CourtListener docket-by-docket, or Docket Navigator.

⚠️ Number-confusion warning: my searches surfaced several other patents informally called the "′929 patent" — e.g., a Data Scape licensing patent, a Pacific Biosciences "Nucleic Acid Sequence Analysis" patent (issued Aug. 22, 2017), Qualcomm's 8,838,949, and Touchstream's 8,904,289. None of these is US 8,338,929. I have not attributed any of that activity to this patent.

Bibliographic summary (from the patent document)

Abstract

A stacked-type chip package structure in which stacked chips and stacked flexible circuit boards are disposed on a substrate. A plurality of spacer layers is respectively sandwiched between two adjacent chips and stacked on top of each other. In addition, conductive bumps are disposed on the substrate and between the stacked flexible circuit boards, such that the stacked flexible circuit boards are electrically connected to the substrate. Besides, conductive wires are electrically connected between the flexible circuit boards and the chips, so as to form a package structure with multi-layer chips on the substrate. Thereby, electrical performance and reliability of the chips are improved.

Plain-language overview of the independent claims

Claim 1 — Apparatus (the "smallest" independent claim):
A stacked chip package on a substrate, built as two parallel vertical "towers" beside a stack of chips:

• A first chip is mounted back-side-down on the substrate's top surface, with a spacer layer sitting directly on its active (upper) face.
• A second chip is mounted back-side-down directly on that spacer, so the spacer physically touches both the first chip's active surface and the second chip's back surface.
• Off to the sides: two first conductive bumps sit directly on the substrate, and two first flexible circuit boards sit on and directly touch those bumps. Each first flex board is wire-bonded to the first chip, but the first chip is not touching the flex boards — there is a horizontal first gap.
• Above that: two second conductive bumps on the first flex boards, and two second flexible circuit boards on those bumps, each wire-bonded to the second chip, again separated from the second chip by a horizontal second gap.

Claim 15 — Apparatus (system-level framing): Essentially the same structure expressed as two separate sub-assemblies on the substrate: a chip stack (first chip → spacer → second chip, spacer touching both chips) and a flexible circuit board stack (first bumps → first flex boards → second bumps → second flex boards, sequentially stacked and directly contacting the substrate). Key added limit: the projection area of the flex stack on the substrate does not overlap the projection area of the chip stack, and the two stacks are separated horizontally by a gap, with conductive wires bridging them.

Claim 17 — Method of fabrication (steps a–i):
(a) place the first chip on the substrate; (b) form two first conductive bumps on the substrate by a stud-bump bonding process, positioned on two sides of the chip and not physically contacting it; (c) place two first flexible circuit boards on those bumps; (d) wire-bond two first conductive wires from the chip to each first flex board; (e) form two second conductive bumps on the first flex boards by stud-bump bonding; (f) place a first spacer layer on the first chip; (g) place the second chip on the spacer; (h) place two second flexible circuit boards on the two second bumps; (i) wire-bond two second conductive wires from the second chip to each second flex board — yielding a two-layer stacked structure on the substrate.

Dependent claims in brief: Claims 2–14 refine claim 1 (bonding pads on upper/lower flex-board surfaces; pad split into a wire-bond portion and a bump-mount portion, with the wire-bond portion smaller and the pad "spoon"-shaped; vias filled with conductor whose size tapers from upper to lower surface; the non-overlapping projection-area limitation; a single sealant fully encapsulating everything). Claim 16 mirrors claim 14's flex-board construction for claim 15. Claims 18–20 add: forming a sealant over the two-layer stack (18), generalizing to N layers where N ≥ 3 (19), and the iterative repeat steps for stacking additional chip/flex layers (20).

Analytical notes and uncertainties

1. Claim scope is markedly narrower than the specification. The specification and pre-grant publication describe the invention broadly (a generic "plurality of stacked flexible circuit boards" with conductive pillars). The granted independent claims instead hard-code very specific structural limits — "two" first bumps/flex boards, "two" second bumps/flex boards, a spacer directly contacting both chips, and explicit horizontal gap and non-overlapping projection area limitations. This pattern is characteristic of narrowing during prosecution (the record shows office actions in the Chinese, German, and Taiwanese counterparts, and cited prior art including US 6,180,881; US 2003/0162326; US 2003/0222344; CN 2726111; CN 1355566). I cannot reconstruct the exact U.S. prosecution history from the material available, so the reason for the narrowing is inference, not established fact.

2. "Stud-bump bonding on the flexible substrate" is the technical hook. The stated advantage is avoiding high-aspect-ratio through-silicon vias (TSVs) and their cost/reliability penalties — the pillars are formed on low-aspect-ratio vias in a polyimide flex substrate, and flex boards offer reworkability.

3. The adjusted expiration date (2028-10-08) is longer than the nominal 20-year term from the 2008-03-07 filing (which would be 2028-03-07). The difference is presumably patent term adjustment, but I have not independently verified the PTA certificate.

4. Maintenance-fee status: the record I retrieved shows fees through the 8th-year payment (2020-06-25) but no entry for the 12th-year payment (which for this patent would have fallen around 2024). Google Patents labels it "Active," which implies fees are current, but I'd flag this as not fully verified and worth confirming directly at USPTO Patent Center if the fee status matters.

5. Litigation/CAFC: as noted, I found no CAFC 2026 docket or any other proceeding tied to this number. If your purpose is a freedom-to-operate or litigation check, please confirm against PACER/CourtListener and the USPTO assignment/reexamination records directly — open-web search is not authoritative for that.

I'll search litigation databases and other sources for US patent 8338929.

The first search returned results referencing a different patent — US 8,166,892 (the "892 Patent" in National Steel Car v. FreightCar America). That is not US 8,338,929, so I cannot treat it as relevant. Let me search more specifically.

Still no direct hits for US 8,338,929. Let me query litigation-specific databases and try more targeted phrasing.

Litigation search results for U.S. Patent No. 8,338,929

Bottom line: I found no known litigation — district court, ITC, or PTAB — asserting or otherwise involving U.S. Patent No. 8,338,929. I am reporting that as a negative finding rather than a confirmation, with the caveats below.

What I searched

I ran targeted queries against web-indexed litigation sources (Unified Patents‑style litigation portals, CourtListener/RECAP dockets, Justia/Docketbird dockets, PTAB/PTActs filings, and news sources) using the exact identifiers "8338929" and "8,338,929," as well as the patent's title ("Stacked-type chip package structure") and its owner (Nanya Technology Corp.). None returned a case in which the 8,338,929 patent was asserted, challenged, or otherwise at issue.

Important negative-finding caveats (please read)

1. Do not confuse this patent with U.S. Patent No. 8,166,892. Several results reference a "the '892 Patent" — but that is US 8,166,892, asserted in National Steel Car Ltd. v. FreightCar America, Inc. (e.g., N.D. Ill. Nos. 11‑cv‑08743, 15‑cv‑03418, 15‑cv‑08643) and subject to a later IPR. That is a different patent from 8,338,929 and I have not treated it as relevant. (I did not auto-correct either number.)

2. Nanya Technology is an active litigant, but not on this patent in the results I found. Nanya (the assignee of 8,338,929) has been sued/asserted in cases including:

   • Elpida Memory, Inc. v. Nanya Technology Corp. et al., No. 5:11‑cv‑04411 (N.D. Cal., filed Sept. 6, 2011), plus the related ITC § 337 investigation (Inv. No. 337‑TA‑819);
   • Lone Star Silicon Innovations LLC v. Nanya Technology Corp. et al., No. 5:17‑cv‑04032 / 3:17‑cv‑04033 (N.D. Cal., filed July 19, 2017) (Fed. Cir. appeal No. 2018‑1581, decided May 30, 2019);
   • Monterey Research, LLC v. Nanya Technology Corp., No. 1:19‑cv‑02090 (D. Del., filed Nov. 11, 2019);
   • Powerwatch Systems LLC v. Nanya Technology Corp., No. 2:26‑cv‑00871 (E.D. Tex.).

   In none of these does the record I retrieved identify U.S. 8,338,929 as an asserted patent. The patents-in-suit in those matters are different numbers (e.g., the Elpida '689, '918, '861, '571, '828, '453, '809 patents; the Monterey '031, '134, '516, '526, '993, '429 patents). These cases are therefore not evidence of litigation on 8,338,929.

3. Coverage limits. Non-frivolous but dismissed, settled, or sealed complaints, and cases not well-indexed by the sources I reached, may exist. Because the search tools returned a step/tool limit before I could exhaust every litigation-specific database (e.g., a completed Unified Patents caselist and full PACER sweep), my conclusion is a good-faith negative finding, not a certification that no suit exists.

Recommended next steps to confirm

• Unified Patents litigation caselist: https://portal.unifiedpatents.com/litigation — search by patent number 8338929.
• USPTO Patent Center / Global Dossier "litigation" and "assignment" tabs, and the USPTO Patent Assignment Search for any recordal of a security interest or license that might accompany a suit.
• PACER full-text/docket search for "8,338,929" and for Nanya as a party (Nanya Technology Corp.; Nanya Technology Corp. USA; Nanya Technology Corp. Delaware).
• PTAB/PTActs (https://ptacts.uspto.gov) for any IPR/PGR/CBM naming 8,338,929.
• CourtListener/RECAP and Justia Dockets free-text search.

If you want, I can run further targeted searches (e.g., specific years, or Nanya-as-plaintiff actions) to try to close out the remaining databases.

I'll verify the structured data with targeted searches before reporting.

Let me run additional targeted checks for litigation and any PTAB activity tied to this specific patent.

One more confirmation pass targeting the patent number directly and any litigation assertion.

All searches returned activity for other Nanya-related patents (the Monterey Research IPRs, IPR2021-00167/170/171/172) but nothing touching US 8,338,929. Reporting accordingly.

Proceedings overview

Total AIA trial proceedings on US 8,338,929: 0. The USPTO Open Data Portal structured block returns no AIA trial proceedings for this patent, and targeted web searches for 8,338,929 / 8338929 in the IPR/PGR/CBM context returned nothing — no instituted trials, no final written decisions, no settled or denied petitions. Bottom line for a defendant: there is no PTAB record to lean on. There are no canceled claims to point a court at, no claim-level FWD findings to import, and no § 315(e)(2) estoppel web binding any prior petitioner. The patent stands as issued on 2012-12-25, with all 20 claims untested at the Board. This is a "build your own record" posture, not a "the patent is already dead" posture.

Proceedings

None to report. Per the operating instruction, the default where the ODP returns nothing and search surfaces nothing is no PTAB activity on file, and that is the finding here. I found no proceeding number to list, and I will not invent one.

For completeness on what the record does show:

• Patent owner / assignee: Nanya Technology Corporation (Taiwan), per the assignment recorded 2008-03-26 (Reel/Frame 020700/0447; inventors Jen-Chun Chen and Wu-Der Yang). Nanya is therefore the patent owner of 8,338,929 — it is the entity a defendant would face, not a petitioner.
• Family / foreign counterparts: TW096146571A → TWI355061B; JP2008139275A → JP5002533B2; DE102008022352A1 (noted as Ceased). None of these is an AIA trial.
• Related but distinct matters: Nanya entities appear as petitioners in IPR2021-00167, IPR2021-00170, IPR2021-00171 and IPR2021-00172 against Monterey Research, LLC patents (e.g., 7,158,429; 6,651,134; 7,158,429's family). Those proceedings are unrelated to 8,338,929 and do not touch its claims. Do not conflate them — the "Nanya" appearing in those filings is on the offensive side against a different NPE's portfolio.

Strategic summary

Claim status. All of claims 1–20 of US 8,338,929 are untested. Nothing has been canceled, nothing sustained, nothing narrowed by certificate of correction or reexamination that I can confirm. That cuts both ways. On the one hand, a defendant gets no free kill: there is no FWD holding claim 1 unpatentable, so you cannot tell a court "the PTAB already invalidated this." On the other hand, the claims are also un-hardened — the patent owner has not had to survive an IPR, so its claims have never been construed by the Board and its validity has never been stress-tested against a well-funded petitioner's best art.

Estoppel landscape. With zero prior petitions, § 315(e)(2) estoppel is empty. No petitioner (or privy) has raised anything, so nothing is foreclosed. A defendant today faces no estoppel constraint and may raise any § 102/§ 103 ground based on patents and printed publications, subject only to the usual § 315(b) one-year bar running from service of an infringement complaint and § 325(d) discretion at the Board. Practically, that means the full prior-art universe is available — including the references already cited on the face of the patent and in its foreign prosecution, plus anything else you can find.

Pattern signals. No defensive aggregator (Unified Patents or similar) appears in the chain for this patent. The patent owner, Nanya, has shown itself willing to litigate (it has been an active petitioner in the Monterey Research disputes and a respondent in ITC investigations), which signals sophistication and resources rather than a passive troll posture. Notably, the patent's claims were narrowed at prosecution rather than at the Board: the granted claims 1, 15 and 17 are markedly more specific than the published application's broad summary language (e.g., claim 1's negative limitations that the chip is "not in direct contact with" the flexible circuit boards, and the explicit first/second gap limitations). That prosecution-history narrowing is itself useful prior-art-estoppel and § 112 fodder that no PTAB proceeding has yet explored.

Recommended next steps

This is not a "no PTAB activity" case where the absence is a strong signal of a weak patent. The reason there are no IPRs is most likely that 8,338,929 has never been asserted in a way that forced a defendant's hand — you are likely early. The absence of PTAB activity is a genuinely neutral signal here, and I want to flag that I am inferring the reason, not stating it as fact.

• If you are a defendant now receiving an assertion letter citing 8,338,929: you are, on the current record, the first mover. There is no FWD to link to, so build the invalidity case from scratch. Prioritize the file history — the December 2007 Taiwan priority application and the U.S. prosecution that produced the "not in direct contact" and "first gap / second gap" limitations are where the narrowing happened, and that narrowing is your best § 112 and estoppel argument.
• IPR timing: § 315(b) gives you one year from service of a complaint alleging infringement to file. Because no other petitioner has filed on this patent, you face no § 315(e)(2) estoppel and, absent a parallel-trial Fintiv problem, should expect an institution decision roughly six months after filing and a statutory FWD deadline one year from institution (35 U.S.C. § 316(a)(11)).
• Do not cite the Monterey IPRs as if they concern this patent. Any demand letter or pre-motion correspondence that conflates IPR2021-00167/170/171/172 (Monterey's patents) with 8,338,929 would be wrong and easily rebutted.
• Verify before relying: I could not access the Google Patents "PTAB proceedings" tab content or the Unified Patents portal for this specific patent (the last query hit a tool step limit). If the stakes are high, confirm directly at PTAB E2E (https://ptacts.uspto.gov) and via the Google Patents "US8338929B2" page's PTAB tab before finalizing any position. I found no proceedings, but a final ingest-freshness check is cheap insurance.

Caveat on sourcing. My conclusion rests on the ODP structured block (which reports no AIA trials) plus three web-search rounds that surfaced no proceeding number for this patent. I did not retrieve a PTAB E2E docket page for 8,338,929 itself. If one exists and is unindexed, I did not see it.

I'll research this patent's assignment record before writing. Let me start with the sources I can reach.

Ownership analysis — US 8,338,929 B2

Data provenance note: I could not query assignmentcenter.uspto.gov programmatically in this session (no direct API/browse access), and repeated web searches surfaced no Assignment Center record page for this patent. The assignment facts below come from the legal-events block rendered on the Google Patents record for US8338929B2 (fetched 2026-10-01), which mirrors the USPTO assignment index, plus the patent's own front-page data in the authoritative text supplied. Where a field was not exposed in any source I could reach — notably the correspondent of record — I say so rather than guess. Verify against USPTO Assignment Search / Assignment Center before relying on this.

Inventors

Pattern check: Both inventors assigned to the corporate applicant before the US filing date (2008-03-07), which is the normal Taiwan-industry "assignment-on-filing" convention, not a distress pattern. I found no evidence that either inventor departed Nanya within 12 months of filing, and no evidence of either inventor surfacing later as an assignor, assignee, or principal in any NPE-family entity. I could not verify their continued employment or current whereabouts — treat that as unverified, not as a clean bill of health.

Original assignee

Nanya Technology Corporation (Taiwan; TWSE-listed, historically part of the Formosa Plastics Group orbit).

• Primary line of business: DRAM design and manufacturing — the patent's claimed subject matter (stacked chips on a substrate with stacked flexible circuit boards carrying conductive pillars/bumps, wire-bonded to the chips, forming a memory module) sits squarely inside Nanya's core DRAM/module packaging line. The specification itself frames the invention around memory modules for desktop/notebook/industrial computers.
• Product embodiment: I can state the claimed architecture is consistent with Nanya's DRAM module packaging business, but I have no product-level evidence of a specific commercial part practicing the claims, and I will not assert one.
• Current status: Operating. No bankruptcy, dissolution, or acquisition event is reflected in any source I retrieved. The patent's US legal status is Active, adjusted expiration 2028-10-08, with maintenance fees paid at the 4th year (2016-02-16) and 8th year (2020-06-25) — ongoing, deliberate upkeep by the original owner.
• Family status: TW sibling TWI355061B (granted 2011-12-21, active), JP sibling JP5002533B2 (granted 2012-08-15, active), DE sibling DE102008022352A1 (not active / ceased).
• Notable context: Nanya appears repeatedly on the defendant side of NPE suits (Monterey Research, Lone Star Silicon Innovations, PLL Technologies, North Star Innovations), i.e. it is a target of the assertion industry, not a participant in it.

Assignment timeline

• 2008-03-03 (executed) / recorded 2008-03-26 — Reel 020700/0447

  • Conveyance: Assignment
  • Assignor: Jen-Chun Chen; Wu-Der Yang (joint inventors)
  • Assignee: Nanya Technology Corporation (Taiwan)
  • Correspondent: Not determinable. The correspondent of record was not exposed in any source I could retrieve for this entry. I will not supply a name by inference.
  • Context: Routine invention-capture / employment assignment recorded pre-issuance; the entire right, title and interest passed to the corporate applicant before the US application was examined.

• No further recorded assignments. The only post-2008 entries in the legal-events record are administrative, not conveyances:

  • 2012-12-05 — STCF, information on status: patent grant
  • 2016-02-16 — FPAY, 4th-year maintenance fee
  • 2020-06-25 — MAFP, 8th-year maintenance fee, large entity

There is no security agreement, merger, change of name, license, release, correction, or transfer-to-asserter of any kind on record. The chain has one link only.

Timeline diagram

timeline
    title Ownership of US 8338929
    2007 : TW priority filed Dec 6
    2008 : US application filed Mar 7
         : Inventors assign to Nanya
         : Recorded reel 020700 frame 0447
    2012 : Patent issues Dec 25
    2016 : 4th year maintenance fee paid
    2020 : 8th year maintenance fee paid
    2028 : Adjusted expiration Oct 8

NPE / troll-pattern signals

1. Shell-entity transfer — not present. The only recorded assignee is Nanya Technology Corporation, an operating DRAM manufacturer. No "IP / Patents / Licensing / Holdings / Ventures" transferee appears at any point; the last legal event affecting title is still Reel 020700/0447 (2008).

2. Known asserter in the chain — not present. Nanya Technology Corporation does not appear on any of the enumerated NPE lists (Acacia, Marathon, IV, IPNav, Wi-LAN, Mosaid/Conversant, Vringo, Pendrell, Innovatio, MPHJ, Lumen View, Round Rock, Document Generation, Spangenberg entities), and the search results show Nanya exclusively as an NPE defendant. The nearby NPE-linked suits I surfaced (Monterey Research, Lone Star Silicon Innovations / Longhorn IP, PLL Technologies, North Star Innovations) concern other patents — Cypress, AMD, Intel, and third-party portfolios — and do not name US 8,338,929.

3. Repeat correspondent across the chain — not present / unclear. With exactly one recorded assignment, there is no chain on which a correspondent could recur. The single entry's correspondent could not be read from my sources, so the "same lawyer, different shell" test cannot even be run. This is a data gap, not a finding — a single appearance would not be probative anyway.

4. Cascading transfers — not present. Zero post-issuance transfers; the <24-month chained-LLC pattern does not exist here. Nine years of ownership by the same Taiwanese corporation.

5. Pre-litigation transfer — not present. No assignment within 6 months of any infringement suit naming this patent, because no suit naming this patent has been identified, and the sole assignment predates issuance by more than four years.

6. Bankruptcy fire-sale — not present. Nanya Technology continued as a going concern through the 2008–09 DRAM downturn and is still operating; no Chapter 7/11 filing, §363 sale, or court-supervised patent auction involving this patent appears in any source retrieved. Note that Nanya-adjacent monetization deals I encountered (e.g. Monterey Research's Cypress/AMD-derived portfolio) are unrelated to this patent's chain.

7. Privateering — not present. No evidence in SEC filings, IAM, or Patent Progress coverage of Nanya placing this patent with an assertion vehicle to sue competitors. The legal-events record shows no transfer at all.

8. Defensive aggregator — not present. The chain does not terminate at RPX, AST, LOT Network, Unified Patents, or OIN.

Verdict

Insufficient data (the rubric's "only the original assignment" case).

The complete recorded title history of US 8,338,929 B2 is a single invention-capture assignment from inventors Jen-Chun Chen and Wu-Der Yang to Nanya Technology Corporation, executed 2008-03-03 and recorded 2008-03-26 at Reel 020700/0447 — with no security interest, merger, name change, or transfer of any kind thereafter. Ownership therefore remains with the original operating assignee, whose continued fee payments in 2016 and 2020 (legal events FPAY/MAFP) and Active status through 2028-10-08 confirm the patent was never abandoned, monetized, or pushed into an assertion vehicle. All eight NPE-pattern signals resolve to not present, and the only real caveat is evidential: I could not retrieve the correspondent of record or query Assignment Center directly, so the negative findings rest on the Google Patents legal-events mirror rather than a first-hand Assignment Center pull.

Verify at: https://assignment.uspto.gov/patent/index.html (search 8338929) or https://assignmentcenter.uspto.gov/

Bottom line for a surveillance watchlist: this patent is a non-event — no NPE exposure. If a future filing shows Reel 020700/0447 being followed by any second reel/frame, that single event would flip the verdict, because it would be the first ownership change in the patent's 18-year life.

I'll research the prior art references cited on the face of US 8,338,929, verifying each against USPTO/Google Patents records.

Now let me verify the remaining cited references and the family-cited (foreign) art.

Prior-Art Analysis — U.S. Patent No. 8,338,929

0. Scope, sources, and caveats (read first)

• I confirmed the target patent before analyzing its citations. U.S. 8,338,929 B2, "Stacked-type chip package structure and fabrication method thereof," Appl. No. 12/043,962, filed 2008-03-07, granted 2012-12-25, inventors Jen-Chun Chen / Wu-Der Yang, assignee Nanya Technology Corp., earliest priority TW 96146571, filed 2007-12-06. I did not substitute any similar number (e.g., the litigation summary's US 8,166,892) for it.
• The citation list below is taken from the authoritative front page of US 8,338,929 furnished in the full patent text. Where my searches retrieved the cited document's own text, I have said so; where retrieval failed or the reference is a foreign document I could not fully open, I flag the mapping as unverified.
• § 102 caveat: a strict anticipation finding requires element-by-element comparison of a single reference's disclosure against each claim. What follows identifies potential § 102 relevance and the claims each reference bears on; it is not a legal conclusion. Several mappings are, at most, § 103 (obviousness) material rather than § 102.
• All cited references predate the 2007-12-06 priority date (their publication/grant dates run 1997–2007), so each qualifies as § 102(a)/(b) art. None is an "intervening" reference.

1. U.S. patent documents cited on the face of US 8,338,929

2. Family-cited (foreign) art — "Family Cites Families (5)"

These were cited during prosecution of the TW/JP/DE counterparts (not necessarily on the U.S. face), and are part of the same extended citation set:

3. Which references are "most relevant" — ranked

Ranked by how much of the independent claims 1, 15 and 17 they potentially reach:

1. US 6,180,881 B1 (Isaak) — the closest overall. It is the only verified reference that expressly builds a stackable carrier from flex-circuit (Kapton) material, stacks chips/carriers vertically, provides vertical conductive elements between layers, and (claim 7) contemplates wire-bonding the chip to the carrier's bonding pads. It maps well onto claim 15 and onto claims 1/14/16 (flex substrate + via/pillar), but its ball-in-aperture interconnect and chip-in-frame-opening architecture differ from the claimed stud-bump-on-flex-board architecture with the flex stack displaced laterally from the die stack.
2. US 2007/0176275 A1 (Singleton) — the closest on the spacer-between-stacked-face-up-chips + wire bonding feature of claims 1/15/17; no flexible circuit boards.
3. US 6,188,127 B1 (NEC) — closest on the flexible tape-film carrier with wiring and vertical inter-layer connection.
4. US 5,656,856 A (Samsung) — stacked packages with frames bearing vertical through-interconnects.
5. US 2007/0145548 A1 (Amkor) and US 7,291,925 B2 (Samsung) — general stacked-package backdrop.
6. CN 2 726 111 Y / CN 1 355 556 A — stacked-package assembly and encapsulation, examiner-cited in China.

Why the patent issued: none of the references above appears to disclose, in a single disclosure, the full claim-1 combination — (i) stacked flexible circuit boards carried on stud-type conductive bumps and displaced laterally from, not contacting, the chips (the claimed "gap"), (ii) a discrete spacer layer in direct contact with both the lower chip's active surface and the upper chip's back surface, and (iii) per-layer wire bonds from each chip to the flex boards of the same layer. The closest art supplies these features only piecemeal, which points to § 103 rather than § 102 as the operative rejection theory.

4. References that are NOT prior art (flagging to prevent miscitation)

• The "Cited By" / "Similar Documents" entries on the Google Patents page — e.g., US 9,704,843 B2 / US 10,224,317 B2 (Infineon), US 11,189,563 B2 (Nanya), US 11,574,820 B2 / US 11,990,350 B2 / US 12,400,877 B2 (Micron, "Semiconductor devices with flexible reinforcement structure"), CN 101,465,341 B — all post-date the 2007-12-06 priority date and therefore are not § 102 prior art against US 8,338,929. (The Micron flexible-reinforcement family is thematically parallel but later.)
• The family members JP 2009-141312 A, TW 200926387 A, TWI355061B, DE 10 2008 022 352 A1, US 2009/0146283 A1, JP 5002533 B2 are the same invention, not prior art.

5. Non-patent citations on the face (office actions and what they cited)

These are prosecution documents, not prior art, but they identify which references the examiners actually relied on:

• 1st Office Action of China counterpart — issued 2009-10-16.
• 1st Office Action of German counterpart — issued 2010-08-31, citing US 6,180,881, US 2003/0222344 and US 2003/0162326.
• 2nd Office Action of China counterpart — issued 2010-11-30, citing CN 2 726 111 and CN 1 355 556.
• Office Action of Taiwan counterpart — issued 2011-07-14.

The German citation trio (US 6,180,881 + US 2003/0222344 + US 2003/0162326) is the most probative signal of what the examiners regarded as the closest art; it should be the starting point for any validity challenge.

6. Conflicts / honesty notes

• No conflict with the earlier litigation section: it correctly kept US 8,166,892 separate from US 8,338,929, and I have done the same.
• Unverified mappings: I could not retrieve the full text of US 2003/0162326 A1 (Tsubosaki) or of the Japanese/Spanish/TW references (JP 3798597, JP 2002-208656, JP 3941654, JP 3693057, KR 100521279, TW 310082, TW 200721432). For those, the "potentially anticipates" column is inferred from title, assignee, date and the counterpart-office-action citation record only — not from an element-by-element reading. I am flagging this rather than overstating certainty.
• Tool limit: my search budget was exhausted before I could open the full text of every foreign reference or run USPTO Patent Center / Global Dossier confirmation of each citation. The bibliographic data and the verified descriptions are drawn from the authoritative patent text plus the Google Patents / FreePatentsOnline / USPTO-report pages cited above.

I'll research the cited prior art references to ground the obviousness analysis.

Based on the patent document and the references cited on its face (the "Prior Art" section of the page), here is a § 103 obviousness analysis of US 8,338,929. I did not have access to the full text of every cited reference (I note verification status below), so I flag where an assertion is grounded in retrieved text versus title/subject-matter only.

1. Legal framework and the person of ordinary skill

Governing standard: The application has a U.S. filing date of 2008-03-07 and a Taiwanese priority date of 2007-12-06, so pre-AIA 35 U.S.C. § 103 applies, and the Graham v. John Deere factors control: scope/content of the prior art, differences between the prior art and the claims, level of ordinary skill, and secondary considerations. KSR Int'l Co. v. Teleflex Inc., 550 U.S. 398 (2007), supplies the rationales for combining.

Level of ordinary skill: A person with a bachelor's degree in electrical/mechanical engineering or materials science and roughly 2–4 years of experience in semiconductor packaging (wire bonding, BGA/leadframe assembly, flex substrates), or equivalent. The claimed technology — wire bonding, stud bumps, polyimide flex carriers, spacer-based die stacking — was mature by 2007.

Prior-art dates: All thirteen cited references predate the 2007-12-06 priority date, so each is available as prior art (several are also § 102(e) art via their own earlier filings).

KSR rationales available to an examiner/petitioner:

1. Combining prior-art elements according to known methods to yield predictable results;
2. Simple substitution of one known element for another to obtain predictable results;
3. Use of a known technique to improve similar devices in the same way;
4. Applying a known technique to a known, improvement-ready device.

2. The inventive core, reduced to its elements

Stripped of the claim language, the granted claims cover a package with two side-by-side vertical "towers": a central chip stack (chip → spacer → chip, spacer touching both) and, beside it, a stacked flexible-circuit-board tower (substrate → first stud bumps → first flex boards → second stud bumps → second flex boards), where each chip layer is wire-bonded to its corresponding flex layer, and the chip stack and flex tower are physically separate (horizontal gaps; non-overlapping footprint). This is essentially the specification's FIGS. 4–5 embodiment.

3. Claim 1 — element-by-element mapping and combinations

Suggested primary combination for Claim 1:
US 2007/0176275 (Singleton) + US 6,180,881 (Isaak) + US 6,188,127 (NEC), optionally + US 7,291,925 (Samsung) for bump/ACF interconnection.

Why a PHOSITA would combine them:

• The ′929 patent's own stated problem — high-aspect-ratio TSVs are costly and degrade chip reliability — was already a recognized motivation to migrate to flex-carrier stacking. Isaak explicitly emphasizes using "available materials and known process techniques, including particularly flex circuit technology" and Kapton/polyimide bases with sputtered copper traces to route die connections to the package periphery. A PHOSITA seeking to avoid silicon vias would look directly to Isaak.
• Singleton supplies the spacer-to-create-wire-bond-clearance teaching for identical-size chips (and cites US 2003/0015803 for a "spacer of smaller dimensions" between chips). The ′929 spacer performs the identical function (its stated purpose is "sufficient wire bonding height… preventing the conductive wires from being cracked").
• NEC supplies the vertical bump interconnection of stacked carriers with through-holes in a film substrate (NEC's claim 10 expressly lists "a flexible film" among carrier types), i.e., the flex tower's stacked, bumped architecture.
• Every element is a known packaging building block combined "according to known methods" with a predictable result — a valid KSR combination.

4. Claim 15 — chip stack / flex stack with non-overlapping projection areas

Claim 15 restates Claim 1 as two sub-assemblies and adds the non-overlapping projection area and horizontal gap limitations.

• The non-overlap/gap limitations are simply the physical consequence of placing a component tower beside a die stack — the arrangement in the ′929 spec's own FIGS. 4–5 and in Isaak/NEC where the flex carrier and chips occupy distinct lateral regions. Placing components side-by-side rather than overlapping is a routine design choice with a predictable result (KSR rationale 4).
• The "sequential stacking of first bumps → first flex boards → second bumps → second flex boards" tracks NEC's stacked-carrier-with-bumps architecture and Isaak's wrapped-flex stacking.

Conclusion: Obvious over the same primary combination; the "projection area does not overlap" wording adds no structural element beyond the side-by-side placement already disclosed/rendered obvious.

5. Claim 17 — the method (steps a–i, stud-bump bonding)

Motivation: Step (b)'s stud-bump process is explicitly praised in the ′929 spec as "reliable and cost effective" and "able to comply with the requirement of mass production" — i.e., it is a known, off-the-shelf technique. Substituting stud bumps for solder balls or the balls/apertures of Isaak/NEC is a simple substitution of a known element for a known purpose with predictable results (KSR rationale 2). Combining wire bonding (Isaak/Singleton) with flex carriers (Isaak/NEC) and spacers (Singleton) follows the ordinary, sequential build of a stacked package.

6. Dependent claims

• Claims 2, 3, 5, 7, 8, 10 (bonding pads on upper/lower flex-board surfaces; pad split into a wire-bond portion and a bump-mount portion): Isaak's flex circuit has a conductive pattern terminated at exposed pads used both for wire bonding and for stacked interconnections — the dual-purpose pad is inherent in his design. Predictable result.
• Claim 13 / 18 (single sealant entirely encapsulating the structure): NEC teaches "seal resin… filled between each LSI chip… and an associated carrier"; Amkor (US 2007/0145548) teaches a hardened insulative material layer covering the die/substrate/interconnects. Full overmolding by transfer molding is a standard step; Isaak encapsulates the die and wire bonds with epoxy. Obvious.
• Claim 19 / 20 (generalize to N layers; repeat steps): plainly an obvious extension — NEC and Isaak both disclose extending stacks beyond two layers; Singleton and Isaak discuss "any number" of chips/packages.
• Claim 12 / 15 gap + non-overlap: addressed above.
• Hardest limitations — claims 4, 6, 9, 11, 14, 16 ("spoon"-shaped bonding pad; pad portions of different sizes; tapered filled vias whose size decreases from upper to lower surface; conductive pillars that increase in size away from the substrate): these are fine structural/geometric features tied to FIGS. 3A–3B and the laser-drilled polyimide via process. They are not clearly met by the on-face references I retrieved, and an obviousness challenge on these specific claims would likely need either (i) additional art on tapered/plated flex vias and teardrop ("spoon") pads, or (ii) a design-choice / obvious-to-try argument (via taper is a natural consequence of laser-drilling and metal-fill; pad shape is cosmetic/functional routing geometry). I'd rate these claims as the strongest non-obviousness positions in the patent, though still vulnerable.

7. Rebuttal-side considerations (secondary indicia and weaknesses of the obviousness case)

1. Teaching away: I found none. The cited art is consistent with, and in Isaak's case explicitly embraces, flex-based stacking; none disparages placing a flex tower beside the die stack.
2. Unexpected results: The ′929 patent asserts (a) improved IC electrical performance/reliability because vias are formed on flex rather than silicon, and (b) reworkability. Both results are inherent/predictable from Isaak's own stated rationale and would carry little patentable weight absent a demonstrated, unexpected magnitude.
3. Nexus problem: The claimed advance is essentially architectural (side towers vs. TSV stack). Commercial-success or licensing evidence, if any, would need a nexus to the claimed structure, not to the general trend toward 3D memory.
4. Prosecution-driven narrowing: As my earlier sections noted, the granted independent claims added the "two bumps / two flex boards," "direct contact," "gap," and "non-overlapping projection area" limitations — a strong signal that the examiner had a § 103 rejection on a broad version of the claims. The issued claim set is narrow; the obviousness attack therefore must target the narrow features (the side-tower geometry and the gaps), each of which is arguably a routine placement/design choice.

8. Bottom line

• Claims 1, 15, 17 and their "architecture" dependents (2, 3, 5, 7, 8, 10, 12, 13, 18, 19, 20) are, in my assessment, reasonably likely to be held obvious over Singleton (US 2007/0176275) + Isaak (US 6,180,881) + NEC (US 6,188,127), with Amkor (US 2007/0145548) and/or Samsung (US 7,291,925) supplying the sealant/second-level interconnect and stud-bump/ACF details. The side-by-side flex tower with interleaved spacer-stacked chips and wire bonds is a combination of well-known packaging elements producing a predictable result.
• Claims 4, 6, 9, 11, 14, 16 (spoon-shaped split pads, tapered vias, tapered/increasing-size conductive pillars) present meaningfully stronger non-obviousness positions and would likely require additional prior art or a design-choice argument.
• The "exactly two" limitations in Claims 1/15/17 are count limitations that a PHOSITA would treat as an arbitrary selection among one-or-more side towers.

9. Confidence and caveats (please read)

• Verified full/partial text: US 6,180,881 (Isaak) — full text retrieved; US 6,188,127 (NEC) — claims and description excerpt retrieved; US 2007/0176275 (Singleton) and its US 7,667,333 family member — abstract/summary/claims retrieved; US 2007/0145548 (Amkor) — abstract and specification excerpt retrieved. These ground the specific citations above.
• Title/subject-matter only (could not retrieve full text before tool limit): US 5,656,856 (Samsung), TW 310082U (Samsung), US 2003/0162326 (Tsubosaki), CN 1355566A (Siliconware), US 2003/0222344 / US 7,193,320 (Fujitsu heat spreader), CN 2726111Y (胜开科技), US 7,291,925 (Samsung ACF), TW 200721432A (Spansion). My characterizations of these are based on their titles and general subject matter; any element mapping relying on them should be re-verified against the actual documents before being used formally.
• Several of these (the Fujitsu heat-spreader pair, the Siliconware QFN, and possibly the Spansion film-fabrication reference) appear peripheral to the flex-tower architecture and would more likely be cited for sealant/heat-spreader/film-process details than for the core combination.
• This is an analyst's technical assessment, not a legal opinion or a validity determination; the actual result depends on claim construction, the full prosecution history, and any additional art a challenger locates. Counterpart Office Actions cited US 6,180,881, US 2003/0162326, US 2003/0222344, CN 2726111, and CN 1355566 — which strongly suggests the examiner and foreign examiners already viewed several of these references as material to the same subject matter.

Primary sources retrieved:

• US 8,338,929 (Google Patents) — https://patents.google.com/patent/US8338929/en
• US 6,180,881 (Isaak) — https://patents.google.com/patent/US6180881
• US 6,188,127 (NEC) — https://uspto.report/patent/grant/[6188127](/patent/6188127)
• US 2007/0176275 (Singleton) — https://patents.google.com/patent/US20070176275 ; https://www.patents-review.com/a/20070176275-stack-semiconductor-chips.html
• US 2007/0145548 (Amkor) — https://patents.google.com/patent/US20070145548