US 12308087

Summary of U.S. Patent 12,308,087

A concise summary of U.S. Patent 12,308,087 is provided below, including details on the patent's title, assignee, inventor, key dates, and a plain-language explanation of its independent claims.

Title: Memory package having stacked array dies and reduced driver load.

Assignee: Netlist Inc.

Inventor: Hyun Lee.

Filing Date: March 14, 2022.

Issue Date: May 20, 2025.

Abstract: The patent describes a DRAM (Dynamic Random-Access Memory) package with stacked array dies. It features distinct data interconnects for different dies within the stack. Specifically, a first set of data interconnects connects to a first array die, and a separate, second set of data interconnects connects to a second array die stacked on top of the first. The package uses drivers of different sizes to send data signals to these separate dies, with a first driver size for the first die and a different, second driver size for the second die.

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Plain-Language Overview of Independent Claims

Based on the provided text, US Patent 12,308,087 appears to have two independent claims: an apparatus claim (Claim 1) and a method claim.

• Claim 1 (Apparatus): This claim describes a physical DRAM package. The key innovation is a structure with at least two stacked memory dies (a first and a second). Instead of one set of connections serving all dies, there are separate data pathways: "first data interconnects" for the first die and distinct "second data interconnects" for the second die. To manage the different signal loads caused by the varying physical lengths of these interconnects, the package uses drivers of different sizes. A driver with a "first driver size" sends signals to the closer, first die, while a driver with a "second driver size" sends signals to the farther, second die. This allows for optimized performance and power usage by tailoring the driver strength to the specific load of each connection.

• Method Claim: This claim outlines a method for optimizing the electrical load within a memory package like the one described in Claim 1. The method involves a design choice: selecting a "first driver size" to send a signal to the first array die through its dedicated interconnect and selecting a different "second driver size" to send a signal to the second array die through its separate interconnect. This selection process acknowledges that the interconnects have different electrical loads (e.g., the connection to the higher die is longer and has a larger load), and therefore the drivers must be sized differently to efficiently manage these loads. Specifically, if the second interconnect has a larger load, the second driver size will be larger than the first.

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Litigation Status

As of today's date, May 14, 2026, information indicates that the patent owner, Netlist Inc., has been involved in litigation concerning this patent family. A complaint was filed on September 29, 2025, asserting US Patent 12,308,087 among others. The complaint alleges infringement by certain DRAM and High Bandwidth Memory (HBM) products. While general searches for CAFC (Court of Appeals for the Federal Circuit) dockets for 2026 were conducted, no specific cases citing US Patent 12,308,087 were identified in the provided search results.