Prior art — US Patent 12308087

Based on the file history of U.S. Patent 12,308,087, the following patents were cited as prior art during prosecution. An analysis of the most relevant references is provided below.

Prior Art Analysis for US 12,308,087

1. U.S. Patent 7,633,165 B2

Full Citation: U.S. Patent 7,633,165 B2, "Semiconductor device and method of fabricating the same," assigned to Samsung Electronics Co., Ltd.
Dates: Filed: October 26, 2007; Published: December 15, 2009.
Brief Description: This patent describes a method for creating stacked semiconductor packages using Through-Silicon Vias (TSVs). It focuses on the physical structure of forming conductive paths that pass through multiple stacked chips. The invention details how to create these vertical interconnects to connect different layers of chips in a 3D package, enabling communication between them.
Potential Anticipation of Claims: This reference is relevant background for the physical structure of stacked dies with TSVs, as mentioned in the specification of '087 (see col. 8, lines 5-11). However, U.S. Patent 7,633,165 B2 does not appear to anticipate the independent claims of US 12,308,087. The disclosure in '165 is centered on the fabrication and structure of the TSV interconnects themselves. It does not disclose or suggest the use of drivers, let alone drivers of different sizes configured to drive signals along these interconnects based on their load characteristics. The '087 patent's novelty lies in the electrical system (differently sized drivers for distinct interconnects), not just the physical stacking structure. Therefore, '165 fails to teach the key limitations of the claims.

2. U.S. Patent 8,787,060 B2

Full Citation: U.S. Patent 8,787,060 B2, "Memory package having stacked array dies and reduced driver load," assigned to Netlist, Inc.
Dates: Filed: November 3, 2011; Published: July 22, 2014.
Brief Description: This patent is an earlier patent in the same family as US 12,308,087 and shares the same title and inventor. It discloses a memory package with stacked dies where the driver load is reduced by splitting the interconnects. For example, instead of one interconnect driving four dies, the patent teaches using two separate interconnects, each driving two dies (see '060 patent, FIG. 2; '087 patent, col. 7, lines 24-30). The goal is to balance the load on the drivers to reduce power and increase speed.
Potential Anticipation of Claims: As a parent patent in the same family, this reference is highly relevant. It discloses the core concept of splitting the data interconnects to reduce driver load. The '060 patent explicitly describes balancing the load on different data conduits, stating "the length of each die interconnect...and the number of array dies...in electrical communication with each die interconnect may be selected to maintain the difference between the load...to be at or below a threshold load difference" ('087 patent, col. 7, lines 42-49, describing the invention).

However, a careful reading shows that U.S. Patent 8,787,060 B2 does not fully anticipate the independent claims of US 12,308,087. The '060 patent focuses on balancing the loads so that the drivers can be of a substantially similar size (see '087 patent, col. 10, lines 20-21). The key limitation in the independent claims of US 12,308,087 is the use of drivers having a "second driver size different from the first driver size" to compensate for interconnects with different loads. While the '060 patent mentions as a possibility that drivers "may vary in size based on the total capacitive load" ('087 patent, col. 10, lines 22-23), the core teaching is load balancing for uniform drivers. The '087 patent claims the specific implementation where the loads are unbalanced by design (e.g., one driver for a near die, another for a far die) and are compensated for with differently sized drivers. This distinction appears to be the novel step claimed in '087.

3. U.S. Patent 9,659,601 B2

Full Citation: U.S. Patent 9,659,601 B2, "Memory package having stacked array dies and reduced driver load," assigned to Netlist, Inc.
Dates: Filed: April 11, 2016; Published: May 23, 2017.
Brief Description: This patent is also part of the same patent family as US 12,308,087. It further develops the concepts from the '060 patent, describing the architecture for reducing and balancing driver load in a 3D stacked memory package. It provides detailed examples of calculating capacitive load based on the number of array dies and the number of interconnect segments ('087 patent, col. 10, lines 34-45).
Potential Anticipation of Claims: Similar to the '060 patent, this reference teaches the foundational concepts but does not explicitly claim the core novelty of US 12,308,087. The focus remains on partitioning the array dies among multiple interconnects to balance the loads. The Summary of the Invention in the '087 patent points directly to the claimed distinction: "a respective signal of the first data signals being driven by one or more drivers having a first driver size, a respective signal of the second data signals being driven by one or more drivers having a second driver size different from the first driver size." This explicit requirement for different driver sizes corresponding to different loads (e.g., a larger driver size for a larger interconnect load) is the specific configuration claimed in '087 and is not the central teaching of '601. Therefore, U.S. Patent 9,659,601 B2 does not anticipate the independent claims of US 12,308,087.