Derivative works

Defensive Disclosure and Prior Art Generation for U.S. Patent 12,308,087

Publication Date: May 14, 2026
Reference Patent: U.S. Patent 12,308,087 ("the '087 patent")
Subject Matter: Memory package architecture with stacked dies, utilizing distinct interconnects and differently-sized drivers to compensate for variable signal loads.

This document discloses a series of derivative inventions and improvements upon the core concepts described in the '087 patent. The intent of this disclosure is to place these concepts into the public domain, thereby establishing them as prior art for any future patent applications in this domain.

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Derivative Variations

1. Material & Component Substitution

1.1. Optical Waveguide Interconnects with Modulated Micro-LED Drivers

• Enabling Description: This variation replaces the electrical Through-Silicon Vias (TSVs) with vertically aligned optical waveguides fabricated from a doped polymer or silicon nitride (SiN). The electrical drivers are substituted with Gallium Nitride (GaN) micro-LEDs integrated onto the control die. The "first driver size" corresponds to a micro-LED with a specific junction area and quantum efficiency optimized for the short optical path to the first photodetector on the first array die. The "second driver size" is a physically larger micro-LED, or an array of micro-LEDs, providing higher optical power (more photons per second) to compensate for attenuation and coupling losses over the longer path to the photodetector on the second, higher array die. The receiving dies incorporate integrated silicon photodetectors in place of electrical pads. This substitution eliminates electrical load (capacitance, inductance) issues and EMI/crosstalk, replacing them with challenges of optical alignment, attenuation, and thermal management of the micro-LEDs.

• Mermaid Diagram:

  graph TD
      subgraph Control Die
          A[Input Signal] --> D1(GaN Micro-LED - Size 1);
          A --> D2(GaN Micro-LED - Size 2);
      end
      subgraph Stacked Array Dies
          PD1(Photodetector on Die 1);
          PD2(Photodetector on Die 2);
      end
      D1 -- Optical Waveguide 1 (Short Path) --> PD1;
      D2 -- Optical Waveguide 2 (Long Path) --> PD2;
  

1.2. Carbon Nanotube (CNT) Interconnects with Memristive Adaptive Drivers

• Enabling Description: The TSVs are replaced with bundles of vertically aligned carbon nanotubes (CNTs), which offer superior electrical and thermal conductivity compared to copper. The drivers are not of a fixed size but are composed of memristive crossbar arrays. A calibration routine during device power-on measures the signal integrity (e.g., rise time, eye opening) for each interconnect. A control logic circuit then adjusts the resistance state of the memristors in the corresponding driver to dynamically tune its output impedance and drive strength. The "first driver size" is functionally achieved by setting the memristive driver to a lower-power state, while the "second driver size" is achieved by configuring its corresponding driver to a higher-power, lower-impedance state. This allows for post-fabrication tuning to account for process variations.

• Mermaid Diagram:

  sequenceDiagram
      participant C as Control Logic
      participant D1 as Memristive Driver 1
      participant I1 as CNT Interconnect 1
      participant D2 as Memristive Driver 2
      participant I2 as CNT Interconnect 2
  
      C->>D1: Initiate Calibration Pulse
      I1-->>C: Return Signal Integrity Data
      C->>D1: Set Low-Power State
      C->>D2: Initiate Calibration Pulse
      I2-->>C: Return Signal Integrity Data
      C->>D2: Set High-Power State
  

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2. Operational Parameter Expansion

2.1. Cryogenic Operation for Quantum Computing Interfaces

• Enabling Description: This variation adapts the architecture for operation at cryogenic temperatures (e.g., < 4 Kelvin) as required for interfacing with quantum computing hardware. The stacked dies are superconducting integrated circuits (e.g., using Niobium). The interconnects are superconducting Nb or NbN TSVs. The "drivers" are Josephson Junction-based amplifiers. The load difference between interconnects is manifested as a variation in the quantum capacitance and kinetic inductance. The "first driver" is a Josephson Junction amplifier with a specific critical current (Ic) designed for the lower load of the shorter interconnect. The "second driver" is a larger SQUID (Superconducting Quantum Interference Device) array with a higher aggregate critical current to drive the longer, higher-inductance interconnect path without signal reflection or phase distortion, which is critical for preserving quantum state information.

• Mermaid Diagram:

  graph TD
      subgraph Control Die (4K)
          A[Quantum Signal] --> DR1(Josephson Amplifier - Ic1);
          A --> DR2(SQUID Array - Ic2 > Ic1);
      end
      subgraph Array Dies (4K)
          Q1(Qubit Interface on Die 1);
          Q2(Qubit Interface on Die 2);
      end
      DR1 -- Superconducting TSV 1 --> Q1;
      DR2 -- Superconducting TSV 2 --> Q2;
  

2.2. High-Frequency Terahertz (THz) Band Operation

• Enabling Description: The technology is scaled to operate in the 0.1-1.0 THz frequency band for ultra-high-speed data transfer. At these frequencies, conventional TSVs act as inefficient antennas. They are replaced by plasmonic waveguides. The drivers are resonant tunneling diodes (RTDs) or high-electron-mobility transistors (HEMTs) integrated on a III-V semiconductor control die (e.g., InP or GaN). The "first driver size" corresponds to an RTD oscillator tuned to a specific frequency and power level sufficient for the short-distance plasmonic channel to the first die. The "second driver size" is a more powerful HEMT-based amplifier or a phase-locked array of RTDs, required to overcome the significant signal absorption and dispersion in the plasmonic waveguide over the longer path to the second die.

• Mermaid Diagram:

  classDiagram
      class ControlDie {
          +driveSignal(data)
      }
      class Driver {
          <<interface>>
          +transmit()
      }
      class RtdDriver {
          -powerLevel: float
          +transmit()
      }
      class HemtAmplifierDriver {
          -gain: float
          +transmit()
      }
      class Interconnect {
          <<interface>>
          +propagate()
      }
      class PlasmonicWaveguide {
          -length: float
          -attenuation: float
          +propagate()
      }
      ControlDie --> "2" Driver
      Driver <|-- RtdDriver : realizes
      Driver <|-- HemtAmplifierDriver : realizes
      Driver --> "1" Interconnect
      Interconnect <|-- PlasmonicWaveguide : realizes
  

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3. Cross-Domain Application

3.1. Aerospace: Stacked Focal-Plane Sensor Array

• Enabling Description: The invention is applied to a focal-plane array for satellite imaging. The package consists of a stack of sensor dies, each sensitive to a different light spectrum (e.g., Die 1: Visible, Die 2: NIR, Die 3: SWIR). The bottom-most die is a radiation-hardened control and processing ASIC. Data from each sensor die must be read out at high speed. The interconnects are radiation-hardened TSVs shielded with a tantalum (Ta) layer. The driver for the first (Visible) sensor die is sized for nominal operation. The driver for the higher (SWIR) sensor die is made significantly larger not only to account for the longer path but also to overcome anticipated radiation-induced increases in interconnect resistance and transistor threshold voltage shifts over the mission lifetime.

• Mermaid Diagram:

  graph LR
      subgraph Readout & Processing ASIC
          D1(Driver 1 - Rad-Hard);
          D2(Driver 2 - Rad-Hard, Oversized);
      end
      subgraph Sensor Stack
          S1(Visible Sensor Die 1);
          S2(SWIR Sensor Die 2);
      end
      S1 -- Data --> D1;
      S2 -- Data --> D2;
      D1 -- Rad-Hard TSV (Short) --> Output;
      D2 -- Rad-Hard TSV (Long) --> Output;
  

3.2. Medical Technology: Implantable Neural Interface

• Enabling Description: A brain-computer interface (BCI) uses a stacked package for signal acquisition and processing. The top die is a microelectrode array for sensing neural signals, and the bottom die is a low-power ASIC for signal processing and wireless transmission. The entire package is hermetically sealed in a biocompatible titanium casing. Power efficiency and minimizing heat dissipation are critical. The interconnects are fine-pitch TSVs. The driver sending control signals up to the microelectrode array (Die 1) is a minimal-size subthreshold CMOS driver to save power. A separate, larger driver is used for the high-speed data downlink from the sensor die. This application separates the concept by signal direction and purpose: an ultra-low power, small driver for the low-bandwidth control uplink, and a larger, higher-speed driver for the high-bandwidth data downlink on a separate interconnect.

• Mermaid Diagram:

  sequenceDiagram
      participant ASIC as Processing ASIC (Die 2)
      participant MEA as Microelectrode Array (Die 1)
      ASIC->>MEA: Control Signal (via Small Driver, Low-Power Interconnect)
      loop Neural Firing
          MEA->>ASIC: Neural Data (via Large Driver, High-Speed Interconnect)
      end
  

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4. Integration with Emerging Tech

4.1. AI-Driven Dynamic Driver Sizing

• Enabling Description: The control die incorporates a lightweight neural network (e.g., a TinyML model). This AI monitors real-time data from on-die thermal sensors, voltage droop monitors, and a bit-error rate (BER) test circuit. Based on these inputs, the AI dynamically adjusts the drive strength of the interconnect drivers. The drivers are not of a fixed physical size but are composed of multiple parallel transistor legs that can be individually enabled or disabled by the AI controller. For the shorter interconnect, the AI might only enable 2 of 8 legs for nominal operation. For the longer interconnect, it might enable 6 of 8 legs. If the BER increases on the long path due to temperature fluctuations, the AI can enable a 7th or 8th leg to increase drive strength, and then power it down when conditions stabilize, thus providing active power and performance optimization beyond a static design choice.

• Mermaid Diagram:

  stateDiagram-v2
      [*] --> Nominal
      Nominal: Drive_1=2/8, Drive_2=6/8
      Nominal --> HighTemp : Temp > Threshold
      HighTemp: Drive_2=7/8 to lower BER
      HighTemp --> Nominal : Temp < Threshold
      Nominal --> LowPower : Vdd < V_low
      LowPower: Drive_1=1/8, Drive_2=4/8
      LowPower --> Nominal : Vdd > V_low
  

4.2. IoT Monitoring and Blockchain-Verified Provenance

• Enabling Description: Each interconnect TSV is fabricated with an integrated ring oscillator whose frequency is sensitive to mechanical stress and temperature. This serves as an IoT sensor. The control die periodically reads these frequencies and reports them via a wireless channel, allowing for remote, real-time health monitoring of the package's structural integrity. Furthermore, during manufacturing and testing, the unique frequency signature of the interconnects for a given die, combined with the required drive strength settings from its AI controller, is hashed and recorded on a private blockchain. This creates an immutable record of the component's physical state and provenance, preventing counterfeiting and verifying that the memory module has not been physically tampered with.

• Mermaid Diagram:

  flowchart TD
      A(TSV with Ring Oscillator Sensor) --> B{Read Frequency};
      B --> C{Detect Stress/Temp Anomaly};
      C --> D[Transmit IoT Alert];
      B --> E{Combine Freq + Driver State};
      E --> F[Generate Hash];
      F --> G((Store on Blockchain));
  

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5. The "Inverse" or Failure Mode

5.1. Graceful Degradation and Safe-Fail Mode

• Enabling Description: The system is designed for high-reliability applications where failure is not an option. The control die actively monitors the integrity of all interconnects. If the BER on the longer, higher-load interconnect to the second die exceeds a critical threshold (indicating impending failure), the controller initiates a safe-fail protocol. It permanently disables the driver and receiver for that interconnect path. It then re-maps the memory address space of the second die to be accessed via a redundant, but slower, serial bus that is also connected to all dies. The system continues to operate with reduced performance, using only the first die at full speed and the second die at reduced speed, but avoids a catastrophic data loss. An error flag is raised to the host system indicating that the module is in a degraded state.

• Mermaid Diagram:

  stateDiagram-v2
      state "Full Performance" as Full
      state "Degraded Mode" as Degraded
      state "Failure" as Fail
  
      [*] --> Full
      Full --> Degraded : BER_2 > Threshold
      Degraded --> Fail : BER_1 > Threshold
      Full --> Fail : Catastrophic Event
  
      note right of Full
        Die 1: Fast TSV
        Die 2: Fast TSV
      end note
  
      note right of Degraded
        Die 1: Fast TSV
        Die 2: Slow Serial Bus
        Raise system flag
      end note
  

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Combination Prior Art Scenarios

1. With JEDEC HBM (JESD235) Standard: The '087 patent's concept is applied to an HBM3-compliant memory stack. The TSVs connecting the base logic die to the first DRAM die (closest) are driven by standard-sized CMOS drivers as specified. However, the drivers for the TSVs connecting to the top-most (e.g., 8th) DRAM die are implemented with a 15% larger gate width and a separate, slightly elevated power rail (VDDH) to provide higher drive strength. This variation is explicitly disclosed as a method to improve signal margins and enable higher clock frequencies on fully-populated HBM stacks beyond the standard JEDEC specification.

2. With RISC-V Open ISA: A RISC-V SoC design integrates a memory controller on its main die, which serves as the control die for a 3D-stacked memory package. The RISC-V instruction set is extended with custom instructions (e.g., MEM.CFG.DRV). These instructions allow privileged software to directly configure the driver strength for different memory regions corresponding to different dies in the stack. For example, MEM.CFG.DRV x1, x2 could set the driver strength for the die specified in register x1 to the level specified in register x2. This enables the operating system to dynamically optimize the power/performance profile based on the application workload.

3. With AMBA AXI Bus Protocol: The control die of the '087 patent's memory package is designed as an AXI4 slave. The 64-bit AXI address space is partitioned. Addresses 0x0000_0000 to 0x3FFF_FFFF map to the first array die, while addresses 0x4000_0000 to 0x7FFF_FFFF map to the second array die. The AXI interconnect logic on the control die decodes the most significant address bits. If the address is in the first range, it enables the smaller driver set for the data bus. If the address is in the second range, it enables the larger, higher-power driver set. This links the selection of driver size directly to the system's memory-mapped I/O architecture via an open standard.