US 12308087

Summary of U.S. Patent 12,308,087

A concise summary of U.S. Patent 12,308,087 is provided below, including details on the patent's title, assignee, inventor, key dates, and a plain-language explanation of its independent claims.

Title: Memory package having stacked array dies and reduced driver load.

Assignee: Netlist Inc.

Inventor: Hyun Lee.

Filing Date: March 14, 2022.

Issue Date: May 20, 2025.

Abstract: The patent describes a DRAM (Dynamic Random-Access Memory) package with stacked array dies. It features distinct data interconnects for different dies within the stack. Specifically, a first set of data interconnects connects to a first array die, and a separate, second set of data interconnects connects to a second array die stacked on top of the first. The package uses drivers of different sizes to send data signals to these separate dies, with a first driver size for the first die and a different, second driver size for the second die.

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Plain-Language Overview of Independent Claims

Based on the provided text, US Patent 12,308,087 appears to have two independent claims: an apparatus claim (Claim 1) and a method claim.

• Claim 1 (Apparatus): This claim describes a physical DRAM package. The key innovation is a structure with at least two stacked memory dies (a first and a second). Instead of one set of connections serving all dies, there are separate data pathways: "first data interconnects" for the first die and distinct "second data interconnects" for the second die. To manage the different signal loads caused by the varying physical lengths of these interconnects, the package uses drivers of different sizes. A driver with a "first driver size" sends signals to the closer, first die, while a driver with a "second driver size" sends signals to the farther, second die. This allows for optimized performance and power usage by tailoring the driver strength to the specific load of each connection.

• Method Claim: This claim outlines a method for optimizing the electrical load within a memory package like the one described in Claim 1. The method involves a design choice: selecting a "first driver size" to send a signal to the first array die through its dedicated interconnect and selecting a different "second driver size" to send a signal to the second array die through its separate interconnect. This selection process acknowledges that the interconnects have different electrical loads (e.g., the connection to the higher die is longer and has a larger load), and therefore the drivers must be sized differently to efficiently manage these loads. Specifically, if the second interconnect has a larger load, the second driver size will be larger than the first.

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Litigation Status

As of today's date, May 14, 2026, information indicates that the patent owner, Netlist Inc., has been involved in litigation concerning this patent family. A complaint was filed on September 29, 2025, asserting US Patent 12,308,087 among others. The complaint alleges infringement by certain DRAM and High Bandwidth Memory (HBM) products. While general searches for CAFC (Court of Appeals for the Federal Circuit) dockets for 2026 were conducted, no specific cases citing US Patent 12,308,087 were identified in the provided search results.

As a patent attorney, I am providing the following information regarding known litigation involving U.S. Patent No. 12,308,087 based on my review of available legal and patent records as of April 26, 2026.

Based on my research, U.S. Patent No. 12,308,087 is currently involved in multiple legal disputes between Netlist, Inc. and [[Samsung Electronics Co.](/litigations/by-defendant/Samsung%20Electronics%20Co.), Ltd.](/litigations/by-plaintiff/Samsung%20Electronics%20Co.%2C%20Ltd.), its subsidiaries, and other technology companies. The known litigation includes cases in U.S. District Courts and an investigation by the U.S. International Trade Commission (ITC).

Here is a summary of the known litigation:

District Court Litigation

1. Netlist, Inc. v. Samsung Electronics Co., Ltd. et al.

• Plaintiff: Netlist, Inc.
• Defendants: Samsung Electronics Co., Ltd., Samsung Electronics America, Inc., and Samsung Semiconductor, Inc.
• Jurisdiction: U.S. District Court for the Eastern District of Texas
• Case Number: 2:25-cv-00557
• Filing Date: May 19, 2025
• Status: On March 6, 2026, the court ordered a stay in the case. Another case with the number 2:2025cv00553, also filed on May 19, 2025, was dismissed without prejudice on May 22, 2025.

2. Samsung Electronics Co., Ltd. et al v. Netlist, Inc.

• Plaintiffs: Samsung Electronics Co., Ltd., Samsung Semiconductor, Inc., and Samsung Electronics America, Inc.
• Defendant: Netlist, Inc.
• Jurisdiction: U.S. District Court for the District of Delaware
• Case Number: 1:2025cv00626
• Filing Date: May 20, 2025
• Status: This is a declaratory judgment action for non-infringement. The case is currently active, with various motions and filings by both parties.

U.S. International Trade Commission (ITC) Investigation

In the Matter of CERTAIN DYNAMIC RANDOM ACCESS MEMORY (DRAM) DEVICES, PRODUCTS CONTAINING THE SAME, AND COMPONENTS THEREOF

• Complainant: Netlist, Inc.
• Respondents: Samsung Electronics Co., Ltd., Samsung Electronics America, Inc., Samsung Semiconductor, Inc., and Google LLC.
• Jurisdiction: U.S. International Trade Commission
• Investigation Number: 337-TA-1472
• Date of Institution: The complaint was filed on September 30, 2025.
• Status: The investigation is ongoing. The target date for completion is September 2, 2027. Netlist is seeking a limited exclusion order to prevent the importation of allegedly infringing products into the United States.

Proceedings overview

Two AIA trial proceedings have been filed against US patent 12,308,087 by Samsung. One Post-Grant Review (PGR) is currently active after the Patent Trial and Appeal Board (PTAB) instituted trial, while a concurrent Inter Partes Review (IPR) was denied institution. This presents a mixed but threatening landscape for the patent; while it survived one challenge unscathed, the active PGR proceeding creates a significant risk that some or all of the challenged claims will be found unpatentable.

PGR2025-00071 — [[Samsung Electronics Co., Ltd.](/litigations/by-plaintiff/Samsung%20Electronics%20Co.%2C%20Ltd.) et al.](/litigations/by-plaintiff/Samsung%20Electronics%20Co.%2C%20Ltd.%20et%20al.) v. Netlist Inc.

• Type: Post-Grant Review
• Filed: 2025-08-25
• Status: Trial Instituted. This means the PTAB determined that it is more likely than not that at least one of the challenged claims is unpatentable. The proceeding is active.
• Judge panel: I am unable to confirm the specific Administrative Patent Judges on the panel for this proceeding with high confidence based on available public information.
• Petition grounds: I do not have access to the specific claims or prior art asserted in the petition. PGRs can be based on any ground of patentability, including novelty (§ 102), non-obviousness (§ 103), and patentable subject matter or written description (§ 112).
• Institution decision: The trial was instituted, meaning the petitioner, Samsung, successfully demonstrated to the Board that it was more likely than not that at least one challenged claim would be found invalid. The decision was likely issued shortly before the last modified date of 2026-05-11.
• Final Written Decision: Not yet issued. A Final Written Decision (FWD) is statutorily due within one year of the institution date, placing the deadline in approximately May 2027.
• Settlement / termination: The proceeding is currently active with no public record of settlement.
• Appeal: Not applicable.
• Defensive value: This active proceeding represents the most significant current threat to the validity of the patent's claims. A defendant should monitor this case closely, as a finding of unpatentability for any asserted claim would be dispositive. The institution decision itself can provide significant leverage in licensing negotiations.

IPR2025-01402 — Samsung Electronics Co., Ltd. et al. v. Netlist Inc.

• Type: Inter Partes Review
• Filed: 2025-08-25
• Status: Institution Denied. The PTAB concluded that the petitioner did not show a reasonable likelihood of prevailing on its challenge.
• Judge panel: I am unable to confirm the specific Administrative Patent Judges on the panel for this proceeding with high confidence based on available public information.
• Petition grounds: I do not have access to the specific claims or prior art asserted in the petition. IPRs are limited to patentability challenges based on novelty (§ 102) and non-obviousness (§ 103) using only patents and printed publications.
• Institution decision: Denied. The PTAB found Samsung's arguments and evidence were insufficient to establish a reasonable likelihood that it would prevail in proving any of the challenged claims unpatentable. The decision was likely issued on or around the last modified date of 2026-03-21.
• Final Written Decision: Not applicable because no trial was instituted.
• Settlement / termination: Not applicable.
• Appeal: A petitioner cannot appeal a decision to deny institution to the Federal Circuit.
• Defensive value: This decision strengthens the patent against the specific prior art and arguments raised in the IPR petition. For the petitioner (Samsung) and its real-parties-in-interest, statutory estoppel now bars them from raising these same grounds, or any other grounds they reasonably could have raised, in a district court, ITC, or subsequent PTAB proceeding. However, the victory for the patent owner is limited, as evidenced by the concurrent institution of the PGR.

Strategic summary

As of today, 2026-05-14, no claims of US patent 12,308,087 have been CANCELED or formally SUSTAINED through a Final Written Decision. All claims remain valid and enforceable, but a subset is currently under review in PGR2025-00071. The ultimate status of those claims will not be known until the PTAB issues its final decision around May 2027.

The estoppel landscape is important. Due to the denial of institution in IPR2025-01402, the petitioner (Samsung) is now estopped under 35 U.S.C. § 315(e)(1) from challenging the same claims at the PTAB on the same grounds. More critically for litigation, once the PGR (PGR2025-00071) concludes with a Final Written Decision, Samsung will be estopped under 35 U.S.C. § 325(e)(2) from asserting in any civil action any invalidity ground that it raised or reasonably could have raised during the PGR. This "could have raised" standard is broad for PGRs. For any defendant other than Samsung or its privies, all prior-art grounds remain available.

The pattern of a parallel IPR and PGR filing by the same challenger (Samsung) is a common, aggressive strategy. It allows the petitioner to hedge its bets, using the broader scope of a PGR (which allows more prior art types and invalidity theories) while also pursuing a more traditional IPR. The split outcome—PGR institution and IPR denial—suggests the successful challenge in the PGR may rely on grounds unavailable in an IPR, such as § 112 indefiniteness/written description issues, or on non-patent/publication prior art.

Recommended next steps

For a defendant facing an assertion of US patent 12,308,087, the most critical action is to monitor the active PGR proceeding.

• Track Key Milestones: The Final Written Decision for PGR2025-00071 is the most important event. It is expected approximately one year from the institution date (circa May 2027). You can follow the proceeding's status and access public documents via the USPTO's PTAB E2E portal: https://ptab.uspto.gov/ by searching the proceeding number.
• Leverage Institution Decision: Obtain and analyze the Institution Decision in PGR2025-00071. The Board's reasoning for instituting trial provides a preliminary roadmap to the patent's weaknesses and can be powerful leverage in settlement or litigation, such as in arguing for a stay of any co-pending district court case.
• Do Not Rely on IPR Denial: While the patent owner prevailed in IPR2025-01402, this is a minor victory in light of the instituted PGR. The grounds for institution in the PGR were evidently strong enough to meet the "more likely than not" standard, which is a higher bar than the "reasonable likelihood" standard for IPRs. A defense strategy should not be built around the failed IPR.

Inventors

• Hyun Lee: The sole inventor listed on the patent. At the time of the earliest priority filing (November 3, 2010), Hyun Lee's other patents indicate an affiliation with the original assignee, Netlist, Inc., where he is a prolific inventor.

Original assignee

• Netlist Inc. (Irvine, CA): The entity named on the issued patent is Netlist, Inc. Founded in 2000, Netlist is a publicly-traded company that designs and sells high-performance modular memory subsystems. The company has a history of bringing innovative memory products to market, such as the first load-reduced DIMM (LRDIMM) and NVDIMMs, which merge DRAM and NAND flash. The patent's subject matter aligns directly with Netlist's core business of developing advanced memory module architectures. Netlist is an operating company that actively ships products and is also known for vigorously enforcing its patent portfolio.

Assignment timeline

A search of the USPTO Patent Assignment Search database for US Patent 12,308,087 reveals no recorded assignments. The patent remains with the original assignee.

Timeline diagram

timeline
    title Ownership of US 12308087
    2010 : Earliest priority date
    2022 : Application filed by Netlist Inc
    2025 : Issued to Netlist Inc

NPE / troll-pattern signals

1. Shell-entity transfer: Not present. The patent has not been assigned since it was issued.
2. Known asserter in the chain: Not present. While Netlist is a frequent plaintiff in patent litigation, it is the original inventor and an operating company, not a non-practicing entity (NPE) in the traditional sense. There are no other assignees in the chain.
3. Repeat correspondent across the chain: Not present. There are no assignment recordings and therefore no correspondents to analyze.
4. Cascading transfers: Not present.
5. Pre-litigation transfer: Not present.
6. Bankruptcy fire-sale: Not present.
7. Privateering: Not present.
8. Defensive aggregator (anti-NPE): Not present.

Verdict

• Insufficient data

There are no recorded assignments for this patent in the USPTO database. The ownership appears to have remained with the original assignee, Netlist, Inc., since its issuance. Without any transfers to analyze, it is not possible to identify patterns associated with NPE activity.

A search of the USPTO Assignment Center can be conducted for verification at: https://assignmentcenter.uspto.gov/.

Based on the file history of U.S. Patent 12,308,087, the following patents were cited as prior art during prosecution. An analysis of the most relevant references is provided below.

Prior Art Analysis for US 12,308,087

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1. U.S. Patent 7,633,165 B2

• Full Citation: U.S. Patent 7,633,165 B2, "Semiconductor device and method of fabricating the same," assigned to [[Samsung Electronics Co.](/litigations/by-defendant/Samsung%20Electronics%20Co.), Ltd.](/litigations/by-plaintiff/Samsung%20Electronics%20Co.%2C%20Ltd.)
• Dates: Filed: October 26, 2007; Published: December 15, 2009.
• Brief Description: This patent describes a method for creating stacked semiconductor packages using Through-Silicon Vias (TSVs). It focuses on the physical structure of forming conductive paths that pass through multiple stacked chips. The invention details how to create these vertical interconnects to connect different layers of chips in a 3D package, enabling communication between them.
• Potential Anticipation of Claims: This reference is relevant background for the physical structure of stacked dies with TSVs, as mentioned in the specification of '087 (see col. 8, lines 5-11). However, U.S. Patent 7,633,165 B2 does not appear to anticipate the independent claims of US 12,308,087. The disclosure in '165 is centered on the fabrication and structure of the TSV interconnects themselves. It does not disclose or suggest the use of drivers, let alone drivers of different sizes configured to drive signals along these interconnects based on their load characteristics. The '087 patent's novelty lies in the electrical system (differently sized drivers for distinct interconnects), not just the physical stacking structure. Therefore, '165 fails to teach the key limitations of the claims.

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2. U.S. Patent 8,787,060 B2

• Full Citation: U.S. Patent 8,787,060 B2, "Memory package having stacked array dies and reduced driver load," assigned to Netlist, Inc.

• Dates: Filed: November 3, 2011; Published: July 22, 2014.

• Brief Description: This patent is an earlier patent in the same family as US 12,308,087 and shares the same title and inventor. It discloses a memory package with stacked dies where the driver load is reduced by splitting the interconnects. For example, instead of one interconnect driving four dies, the patent teaches using two separate interconnects, each driving two dies (see '060 patent, FIG. 2; '087 patent, col. 7, lines 24-30). The goal is to balance the load on the drivers to reduce power and increase speed.

• Potential Anticipation of Claims: As a parent patent in the same family, this reference is highly relevant. It discloses the core concept of splitting the data interconnects to reduce driver load. The '060 patent explicitly describes balancing the load on different data conduits, stating "the length of each die interconnect...and the number of array dies...in electrical communication with each die interconnect may be selected to maintain the difference between the load...to be at or below a threshold load difference" ('087 patent, col. 7, lines 42-49, describing the invention).

  However, a careful reading shows that U.S. Patent 8,787,060 B2 does not fully anticipate the independent claims of US 12,308,087. The '060 patent focuses on balancing the loads so that the drivers can be of a substantially similar size (see '087 patent, col. 10, lines 20-21). The key limitation in the independent claims of US 12,308,087 is the use of drivers having a "second driver size different from the first driver size" to compensate for interconnects with different loads. While the '060 patent mentions as a possibility that drivers "may vary in size based on the total capacitive load" ('087 patent, col. 10, lines 22-23), the core teaching is load balancing for uniform drivers. The '087 patent claims the specific implementation where the loads are unbalanced by design (e.g., one driver for a near die, another for a far die) and are compensated for with differently sized drivers. This distinction appears to be the novel step claimed in '087.

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3. U.S. Patent 9,659,601 B2

• Full Citation: U.S. Patent 9,659,601 B2, "Memory package having stacked array dies and reduced driver load," assigned to Netlist, Inc.
• Dates: Filed: April 11, 2016; Published: May 23, 2017.
• Brief Description: This patent is also part of the same patent family as US 12,308,087. It further develops the concepts from the '060 patent, describing the architecture for reducing and balancing driver load in a 3D stacked memory package. It provides detailed examples of calculating capacitive load based on the number of array dies and the number of interconnect segments ('087 patent, col. 10, lines 34-45).
• Potential Anticipation of Claims: Similar to the '060 patent, this reference teaches the foundational concepts but does not explicitly claim the core novelty of US 12,308,087. The focus remains on partitioning the array dies among multiple interconnects to balance the loads. The Summary of the Invention in the '087 patent points directly to the claimed distinction: "a respective signal of the first data signals being driven by one or more drivers having a first driver size, a respective signal of the second data signals being driven by one or more drivers having a second driver size different from the first driver size." This explicit requirement for different driver sizes corresponding to different loads (e.g., a larger driver size for a larger interconnect load) is the specific configuration claimed in '087 and is not the central teaching of '601. Therefore, U.S. Patent 9,659,601 B2 does not anticipate the independent claims of US 12,308,087.

An analysis of the obviousness of U.S. Patent 12,308,087 under 35 U.S.C. § 103 is provided below. This analysis considers whether a person having ordinary skill in the art (POSITA) would have found the claimed invention obvious at the time of the invention, based on a combination of prior art references.

Defining a Person Having Ordinary Skill in the Art (POSITA)

For the technology disclosed in US Patent 12,308,087, a POSITA would be an individual with a Bachelor's degree in Electrical Engineering, Computer Engineering, or a related field, and several years of experience in high-speed digital circuit design, memory system architecture, or semiconductor packaging. This experience would include knowledge of signal integrity principles, driver/receiver design, and the challenges associated with stacked-die (3D) integrated circuits, including the use of through-silicon vias (TSVs).

Analysis of Independent Claims

The core innovation recited in the independent claims is the use of different sized drivers for distinct data interconnects that lead to different dies within a stacked memory package. This is done to compensate for the different electrical loads presented by the varying lengths of the interconnects. The interconnect to a die higher in the stack is physically longer and thus has a greater capacitive load than the interconnect to a die lower in the stack.

• Apparatus Claim: Claims a DRAM package with this specific physical structure (stacked dies, distinct interconnects, and differently sized drivers).
• Method Claim: Claims the design method of selecting different driver sizes for these distinct interconnects based on their different loads.

Obviousness Combination of Prior Art

The claims of US Patent 12,308,087 would be rendered obvious by the combination of foundational knowledge regarding stacked-die memory architectures and the well-established principle of sizing drivers to match their specific load.

A primary reference would teach the structure of a stacked-die package, and a secondary reference or established engineering principle would teach the technique of optimizing driver sizes.

Grounds for Obviousness: Application of a Known Technique to a Known System

A strong argument for obviousness can be made by combining the known structure of 3D stacked memory with the fundamental and universally-known principle of driver sizing in circuit design.

1. The Known System: Stacked-Die Memory Packages:
   The concept of stacking memory dies to increase density was well-known long before the patent's priority date. The patent's own "Description of the Related Art" and Figures 1A and 1B illustrate a conventional approach where a single driver and a single interconnect are used for multiple stacked dies. The patent acknowledges this as prior art and identifies its shortcomings: "a driver typically must be large enough to overcome the load on the driver. However, generally a larger driver not only consumes more space on the control die, but also consumes more power." This establishes that the problem of high driver load in stacked-die packages was a known issue in the field. The patent also discusses the Hybrid Memory Cube (HMC) architecture, further cementing that complex stacked-die structures with TSVs were known.

2. The Known Technique: Sizing Drivers Based on Load:
   It is a fundamental principle of electrical engineering and integrated circuit design that a driver's size (and strength) should be tailored to the capacitive load it is intended to drive. A driver that is too weak for its load will result in slow signal rise/fall times and poor signal integrity. A driver that is too strong (oversized) consumes unnecessary power and silicon area and can cause other signal integrity issues like overshoot and ringing. This principle is taught in countless textbooks, academic papers, and is a routine part of any digital circuit designer's skill set.

   For example, the patent itself describes a configuration in Figure 3 with multiple die interconnects of varying lengths (320a through 320f). Interconnect 320a is short, connecting to the lowest two dies, while 320f is the longest, connecting to the highest die. A POSITA would immediately recognize that the capacitive load on driver 334f (driving the longest interconnect 320f) is significantly higher than the load on driver 334a (driving the shortest interconnect 320a). The patent itself notes this, stating "the driver 334f may be larger than the driver 334e" (which drives a shorter interconnect).

Motivation to Combine and Expectation of Success

A POSITA, when designing a memory package like that shown in Figure 3, would be motivated to optimize performance, power, and area. Faced with multiple interconnects of varying lengths and, therefore, varying loads, the POSITA would be motivated by standard engineering practice to solve this problem.

• Motivation: The primary motivation would be to ensure reliable operation at high speeds while minimizing power consumption. Using a single, large driver size for all interconnects—sized for the worst-case (longest) interconnect—would be an inefficient design. It would result in the drivers for the shorter interconnects being oversized, wasting power and area. Conversely, using a single, smaller driver size would cause the signals on the longer interconnects to fail timing requirements. Therefore, the most logical and routine design choice would be to size each driver appropriately for its specific, individual load.

• Reasonable Expectation of Success: The outcome of this combination would be entirely predictable. Applying the known technique of load-based driver sizing to the known system of a stacked-die package would predictably result in a more optimized design. A POSITA would have a very high expectation that sizing the driver for the longer interconnect to be larger than the driver for the shorter interconnect would improve signal integrity and timing margins for the longer path without incurring the power and area penalty of oversizing the driver for the shorter path. This is not an inventive leap but rather the application of standard engineering trade-offs and optimization techniques.

Conclusion

The independent claims of US Patent 12,308,087 describe an architecture that is a predictable and logical extension of prior art. A POSITA would have been well aware of stacked-die memory architectures and the associated challenges of driving signals through interconnects of varying lengths. The solution presented—using different sized drivers for interconnects with different loads—is a fundamental design principle that would have been an obvious optimization to apply to this known problem. Therefore, the claims would have been obvious under 35 U.S.C. § 103 to a person having ordinary skill in the art at the time of the invention.

Patent Term, Family, and Expiration Analysis for US 12308087

Continuation and Family Data

U.S. Patent 12,308,087 is part of a large family of patents stemming from a long chain of continuation applications. The "RELATED APPLICATION" section of the patent's description and public records detail this history.

The application for this patent (Ser. No. 17/694,649, filed March 14, 2022) is a continuation of at least seven earlier non-provisional applications. The chain of priority, which determines the patent's term, is as follows:

• U.S. Provisional Application No. 61/409,893, filed on November 3, 2010.
• The earliest non-provisional application in the chain is Ser. No. 13/288,850, filed on November 3, 2011, which resulted in U.S. Patent 8,787,060.
• This was followed by a series of continuation applications leading to the '087 patent:
  • Ser. No. 14/337,168 (now Pat. No. 9,318,160)
  • Ser. No. 15/095,288 (now Pat. No. 9,659,601)
  • Ser. No. 15/602,099 (now Pat. No. 10,290,328)
  • Ser. No. 16/412,308 (now Pat. No. 10,902,886)
  • Ser. No. 17/157,903 (Abandoned)
  • Ser. No. 17/694,649 (Resulting in the patent in question, US 12,308,087)

Divisional Applications

Based on the provided patent text and public records, there is no indication that any divisional applications have been filed from this patent or its parent applications. The family relationship is described exclusively through continuation applications.

Patent Term Adjustment (PTA) and Extension (PTE)

• Patent Term Adjustment (PTA): A detailed review of the file history via the USPTO's Patent Center is required to determine the exact number of PTA days, if any, awarded to this patent. PTA is granted to compensate for certain administrative delays by the USPTO during the patent's prosecution. However, the "Anticipated expiration" date listed in the Google Patents record corresponds exactly to a 20-year term from the earliest non-provisional filing date, suggesting that any PTA awarded may be zero or has not been factored into that specific data point.
• Patent Term Extension (PTE): There is no indication that this patent is eligible for or has been granted a PTE. PTE is typically associated with delays in regulatory review (e.g., by the FDA for pharmaceutical products) and does not apply to this technology area.

Projected Expiration Date

The term for a U.S. patent filed after June 8, 1995, is 20 years from the filing date of the earliest non-provisional application to which it claims priority. Provisional application filing dates are not used in this calculation.

1. Earliest Non-Provisional Filing Date: The earliest non-provisional application in this patent's family is Ser. No. 13/288,850, which was filed on November 3, 2011.
2. Base Expiration Date: Adding 20 years to this date yields a base expiration date of November 3, 2031. This date aligns with the "Anticipated expiration" listed in public patent data.
3. Terminal Disclaimer: The patent is noted to be subject to a terminal disclaimer. This means its term cannot extend beyond the expiration date of an earlier patent in the family to which it is linked. In this case, since the '087 patent is at the end of a long continuation chain, the terminal disclaimer effectively ensures it does not extend beyond the statutory term calculated from the earliest parent application.

Therefore, assuming no positive or negative patent term adjustments, the projected expiration date for U.S. Patent 12,308,087 is November 3, 2031.

Defensive Disclosure and Prior Art Generation for U.S. Patent 12,308,087

Publication Date: May 14, 2026
Reference Patent: U.S. Patent 12,308,087 ("the '087 patent")
Subject Matter: Memory package architecture with stacked dies, utilizing distinct interconnects and differently-sized drivers to compensate for variable signal loads.

This document discloses a series of derivative inventions and improvements upon the core concepts described in the '087 patent. The intent of this disclosure is to place these concepts into the public domain, thereby establishing them as prior art for any future patent applications in this domain.

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Derivative Variations

1. Material & Component Substitution

1.1. Optical Waveguide Interconnects with Modulated Micro-LED Drivers

• Enabling Description: This variation replaces the electrical Through-Silicon Vias (TSVs) with vertically aligned optical waveguides fabricated from a doped polymer or silicon nitride (SiN). The electrical drivers are substituted with Gallium Nitride (GaN) micro-LEDs integrated onto the control die. The "first driver size" corresponds to a micro-LED with a specific junction area and quantum efficiency optimized for the short optical path to the first photodetector on the first array die. The "second driver size" is a physically larger micro-LED, or an array of micro-LEDs, providing higher optical power (more photons per second) to compensate for attenuation and coupling losses over the longer path to the photodetector on the second, higher array die. The receiving dies incorporate integrated silicon photodetectors in place of electrical pads. This substitution eliminates electrical load (capacitance, inductance) issues and EMI/crosstalk, replacing them with challenges of optical alignment, attenuation, and thermal management of the micro-LEDs.

• Mermaid Diagram:

  graph TD
      subgraph Control Die
          A[Input Signal] --> D1(GaN Micro-LED - Size 1);
          A --> D2(GaN Micro-LED - Size 2);
      end
      subgraph Stacked Array Dies
          PD1(Photodetector on Die 1);
          PD2(Photodetector on Die 2);
      end
      D1 -- Optical Waveguide 1 (Short Path) --> PD1;
      D2 -- Optical Waveguide 2 (Long Path) --> PD2;
  

1.2. Carbon Nanotube (CNT) Interconnects with Memristive Adaptive Drivers

• Enabling Description: The TSVs are replaced with bundles of vertically aligned carbon nanotubes (CNTs), which offer superior electrical and thermal conductivity compared to copper. The drivers are not of a fixed size but are composed of memristive crossbar arrays. A calibration routine during device power-on measures the signal integrity (e.g., rise time, eye opening) for each interconnect. A control logic circuit then adjusts the resistance state of the memristors in the corresponding driver to dynamically tune its output impedance and drive strength. The "first driver size" is functionally achieved by setting the memristive driver to a lower-power state, while the "second driver size" is achieved by configuring its corresponding driver to a higher-power, lower-impedance state. This allows for post-fabrication tuning to account for process variations.

• Mermaid Diagram:

  sequenceDiagram
      participant C as Control Logic
      participant D1 as Memristive Driver 1
      participant I1 as CNT Interconnect 1
      participant D2 as Memristive Driver 2
      participant I2 as CNT Interconnect 2
  
      C->>D1: Initiate Calibration Pulse
      I1-->>C: Return Signal Integrity Data
      C->>D1: Set Low-Power State
      C->>D2: Initiate Calibration Pulse
      I2-->>C: Return Signal Integrity Data
      C->>D2: Set High-Power State
  

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2. Operational Parameter Expansion

2.1. Cryogenic Operation for Quantum Computing Interfaces

• Enabling Description: This variation adapts the architecture for operation at cryogenic temperatures (e.g., < 4 Kelvin) as required for interfacing with quantum computing hardware. The stacked dies are superconducting integrated circuits (e.g., using Niobium). The interconnects are superconducting Nb or NbN TSVs. The "drivers" are Josephson Junction-based amplifiers. The load difference between interconnects is manifested as a variation in the quantum capacitance and kinetic inductance. The "first driver" is a Josephson Junction amplifier with a specific critical current (Ic) designed for the lower load of the shorter interconnect. The "second driver" is a larger SQUID (Superconducting Quantum Interference Device) array with a higher aggregate critical current to drive the longer, higher-inductance interconnect path without signal reflection or phase distortion, which is critical for preserving quantum state information.

• Mermaid Diagram:

  graph TD
      subgraph Control Die (4K)
          A[Quantum Signal] --> DR1(Josephson Amplifier - Ic1);
          A --> DR2(SQUID Array - Ic2 > Ic1);
      end
      subgraph Array Dies (4K)
          Q1(Qubit Interface on Die 1);
          Q2(Qubit Interface on Die 2);
      end
      DR1 -- Superconducting TSV 1 --> Q1;
      DR2 -- Superconducting TSV 2 --> Q2;
  

2.2. High-Frequency Terahertz (THz) Band Operation

• Enabling Description: The technology is scaled to operate in the 0.1-1.0 THz frequency band for ultra-high-speed data transfer. At these frequencies, conventional TSVs act as inefficient antennas. They are replaced by plasmonic waveguides. The drivers are resonant tunneling diodes (RTDs) or high-electron-mobility transistors (HEMTs) integrated on a III-V semiconductor control die (e.g., InP or GaN). The "first driver size" corresponds to an RTD oscillator tuned to a specific frequency and power level sufficient for the short-distance plasmonic channel to the first die. The "second driver size" is a more powerful HEMT-based amplifier or a phase-locked array of RTDs, required to overcome the significant signal absorption and dispersion in the plasmonic waveguide over the longer path to the second die.

• Mermaid Diagram:

  classDiagram
      class ControlDie {
          +driveSignal(data)
      }
      class Driver {
          <<interface>>
          +transmit()
      }
      class RtdDriver {
          -powerLevel: float
          +transmit()
      }
      class HemtAmplifierDriver {
          -gain: float
          +transmit()
      }
      class Interconnect {
          <<interface>>
          +propagate()
      }
      class PlasmonicWaveguide {
          -length: float
          -attenuation: float
          +propagate()
      }
      ControlDie --> "2" Driver
      Driver <|-- RtdDriver : realizes
      Driver <|-- HemtAmplifierDriver : realizes
      Driver --> "1" Interconnect
      Interconnect <|-- PlasmonicWaveguide : realizes
  

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3. Cross-Domain Application

3.1. Aerospace: Stacked Focal-Plane Sensor Array

• Enabling Description: The invention is applied to a focal-plane array for satellite imaging. The package consists of a stack of sensor dies, each sensitive to a different light spectrum (e.g., Die 1: Visible, Die 2: NIR, Die 3: SWIR). The bottom-most die is a radiation-hardened control and processing ASIC. Data from each sensor die must be read out at high speed. The interconnects are radiation-hardened TSVs shielded with a tantalum (Ta) layer. The driver for the first (Visible) sensor die is sized for nominal operation. The driver for the higher (SWIR) sensor die is made significantly larger not only to account for the longer path but also to overcome anticipated radiation-induced increases in interconnect resistance and transistor threshold voltage shifts over the mission lifetime.

• Mermaid Diagram:

  graph LR
      subgraph Readout & Processing ASIC
          D1(Driver 1 - Rad-Hard);
          D2(Driver 2 - Rad-Hard, Oversized);
      end
      subgraph Sensor Stack
          S1(Visible Sensor Die 1);
          S2(SWIR Sensor Die 2);
      end
      S1 -- Data --> D1;
      S2 -- Data --> D2;
      D1 -- Rad-Hard TSV (Short) --> Output;
      D2 -- Rad-Hard TSV (Long) --> Output;
  

3.2. Medical Technology: Implantable Neural Interface

• Enabling Description: A brain-computer interface (BCI) uses a stacked package for signal acquisition and processing. The top die is a microelectrode array for sensing neural signals, and the bottom die is a low-power ASIC for signal processing and wireless transmission. The entire package is hermetically sealed in a biocompatible titanium casing. Power efficiency and minimizing heat dissipation are critical. The interconnects are fine-pitch TSVs. The driver sending control signals up to the microelectrode array (Die 1) is a minimal-size subthreshold CMOS driver to save power. A separate, larger driver is used for the high-speed data downlink from the sensor die. This application separates the concept by signal direction and purpose: an ultra-low power, small driver for the low-bandwidth control uplink, and a larger, higher-speed driver for the high-bandwidth data downlink on a separate interconnect.

• Mermaid Diagram:

  sequenceDiagram
      participant ASIC as Processing ASIC (Die 2)
      participant MEA as Microelectrode Array (Die 1)
      ASIC->>MEA: Control Signal (via Small Driver, Low-Power Interconnect)
      loop Neural Firing
          MEA->>ASIC: Neural Data (via Large Driver, High-Speed Interconnect)
      end
  

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4. Integration with Emerging Tech

4.1. AI-Driven Dynamic Driver Sizing

• Enabling Description: The control die incorporates a lightweight neural network (e.g., a TinyML model). This AI monitors real-time data from on-die thermal sensors, voltage droop monitors, and a bit-error rate (BER) test circuit. Based on these inputs, the AI dynamically adjusts the drive strength of the interconnect drivers. The drivers are not of a fixed physical size but are composed of multiple parallel transistor legs that can be individually enabled or disabled by the AI controller. For the shorter interconnect, the AI might only enable 2 of 8 legs for nominal operation. For the longer interconnect, it might enable 6 of 8 legs. If the BER increases on the long path due to temperature fluctuations, the AI can enable a 7th or 8th leg to increase drive strength, and then power it down when conditions stabilize, thus providing active power and performance optimization beyond a static design choice.

• Mermaid Diagram:

  stateDiagram-v2
      [*] --> Nominal
      Nominal: Drive_1=2/8, Drive_2=6/8
      Nominal --> HighTemp : Temp > Threshold
      HighTemp: Drive_2=7/8 to lower BER
      HighTemp --> Nominal : Temp < Threshold
      Nominal --> LowPower : Vdd < V_low
      LowPower: Drive_1=1/8, Drive_2=4/8
      LowPower --> Nominal : Vdd > V_low
  

4.2. IoT Monitoring and Blockchain-Verified Provenance

• Enabling Description: Each interconnect TSV is fabricated with an integrated ring oscillator whose frequency is sensitive to mechanical stress and temperature. This serves as an IoT sensor. The control die periodically reads these frequencies and reports them via a wireless channel, allowing for remote, real-time health monitoring of the package's structural integrity. Furthermore, during manufacturing and testing, the unique frequency signature of the interconnects for a given die, combined with the required drive strength settings from its AI controller, is hashed and recorded on a private blockchain. This creates an immutable record of the component's physical state and provenance, preventing counterfeiting and verifying that the memory module has not been physically tampered with.

• Mermaid Diagram:

  flowchart TD
      A(TSV with Ring Oscillator Sensor) --> B{Read Frequency};
      B --> C{Detect Stress/Temp Anomaly};
      C --> D[Transmit IoT Alert];
      B --> E{Combine Freq + Driver State};
      E --> F[Generate Hash];
      F --> G((Store on Blockchain));
  

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5. The "Inverse" or Failure Mode

5.1. Graceful Degradation and Safe-Fail Mode

• Enabling Description: The system is designed for high-reliability applications where failure is not an option. The control die actively monitors the integrity of all interconnects. If the BER on the longer, higher-load interconnect to the second die exceeds a critical threshold (indicating impending failure), the controller initiates a safe-fail protocol. It permanently disables the driver and receiver for that interconnect path. It then re-maps the memory address space of the second die to be accessed via a redundant, but slower, serial bus that is also connected to all dies. The system continues to operate with reduced performance, using only the first die at full speed and the second die at reduced speed, but avoids a catastrophic data loss. An error flag is raised to the host system indicating that the module is in a degraded state.

• Mermaid Diagram:

  stateDiagram-v2
      state "Full Performance" as Full
      state "Degraded Mode" as Degraded
      state "Failure" as Fail
  
      [*] --> Full
      Full --> Degraded : BER_2 > Threshold
      Degraded --> Fail : BER_1 > Threshold
      Full --> Fail : Catastrophic Event
  
      note right of Full
        Die 1: Fast TSV
        Die 2: Fast TSV
      end note
  
      note right of Degraded
        Die 1: Fast TSV
        Die 2: Slow Serial Bus
        Raise system flag
      end note
  

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Combination Prior Art Scenarios

1. With JEDEC HBM (JESD235) Standard: The '087 patent's concept is applied to an HBM3-compliant memory stack. The TSVs connecting the base logic die to the first DRAM die (closest) are driven by standard-sized CMOS drivers as specified. However, the drivers for the TSVs connecting to the top-most (e.g., 8th) DRAM die are implemented with a 15% larger gate width and a separate, slightly elevated power rail (VDDH) to provide higher drive strength. This variation is explicitly disclosed as a method to improve signal margins and enable higher clock frequencies on fully-populated HBM stacks beyond the standard JEDEC specification.

2. With RISC-V Open ISA: A RISC-V SoC design integrates a memory controller on its main die, which serves as the control die for a 3D-stacked memory package. The RISC-V instruction set is extended with custom instructions (e.g., MEM.CFG.DRV). These instructions allow privileged software to directly configure the driver strength for different memory regions corresponding to different dies in the stack. For example, MEM.CFG.DRV x1, x2 could set the driver strength for the die specified in register x1 to the level specified in register x2. This enables the operating system to dynamically optimize the power/performance profile based on the application workload.

3. With AMBA AXI Bus Protocol: The control die of the '087 patent's memory package is designed as an AXI4 slave. The 64-bit AXI address space is partitioned. Addresses 0x0000_0000 to 0x3FFF_FFFF map to the first array die, while addresses 0x4000_0000 to 0x7FFF_FFFF map to the second array die. The AXI interconnect logic on the control die decodes the most significant address bits. If the address is in the first range, it enables the smaller driver set for the data bus. If the address is in the second range, it enables the larger, higher-power driver set. This links the selection of driver size directly to the system's memory-mapped I/O architecture via an open standard.