US 9824035

Analysis of U.S. Patent No. 9,824,035

Date of Analysis: May 13, 2026

This report provides a summary of United States Patent No. 9,824,035, including its bibliographic details and a plain-language explanation of its independent claims.

Bibliographic Information:

• Title: Memory module with timing-controlled data paths in distributed data buffers
• Assignee: Netlist, Inc.
• Inventors: Hyun Lee, Jayesh R. Bhakta
• Filing Date: February 7, 2017
• Issue Date: November 21, 2017
• Abstract: A memory module is operatable in a memory system with a memory controller. The memory module comprises a module control device mounted on the module board to receive command signals from the memory controller and to output module command signals and module control signals, and memory devices mounted on the module board to perform a first memory operation in response to the module command signals. The memory module further comprises a plurality of buffer circuits distributed across a surface of the module board. Each respective buffer circuit is associated with a respective set of the memory devices and includes logic that is configured to obtain timing information based on signals received by the each respective buffer circuit during a second memory operation prior to the first memory operation and to control timing of the data and strobe signals through the each respective buffer circuit in accordance with the timing information.

Litigation Status: A search of the U.S. Court of Appeals for the Federal Circuit (CAFC) dockets for 2026 did not reveal any pending cases specifically citing U.S. Patent No. 9,824,035.

Plain-Language Overview of Independent Claims:

U.S. Patent No. 9,824,035 has two independent claims: claim 1 and claim 15.

Claim 1: A Memory Module with Intelligent Buffer Circuits

This claim describes a memory module, such as a RAM stick, designed to work with a computer's memory controller. The key components are:

• A module control device: This chip on the memory module receives commands from the main memory controller.
• Memory devices: These are the standard memory chips (like DRAM) that store data.
• Distributed buffer circuits: These are special-purpose chips, also called isolation devices, placed on the module. Each buffer is responsible for managing a specific group of memory devices.

The core innovation is that each buffer circuit has its own logic. This logic allows the buffer to:

1. Learn Timing: During one type of memory operation (e.g., a "write" operation), the buffer circuit measures and records timing information about the signals it receives.
2. Apply Learned Timing: During a subsequent, different memory operation (e.g., a "read" operation), the buffer uses this stored timing information to precisely control the timing of data and strobe signals passing through it.

In essence, the buffer circuits are "smart" and can adapt to the specific timing characteristics of the system they are in, which helps to ensure reliable data transfer, especially at high speeds. This is particularly useful in systems where the physical distance from the controller to different memory chips can cause timing variations.

Claim 15: A Method for Operating a Memory Module

This claim outlines the process carried out by the memory module described in Claim 1. The method involves these steps:

1. Receiving Signals: A buffer circuit on the memory module receives module control signals from the module's control device and also receives a data strobe signal directly from the main system memory controller.
2. Determining a Time Interval: The buffer circuit measures the time difference between when it receives the module control signal and when the data strobe signal arrives from the system's memory controller during a write operation.
3. Generating a Delay Value: Based on this measured time interval, the buffer circuit creates a delay value.
4. Applying the Delay: The buffer circuit then receives data from the memory chips (a read operation). It uses the previously calculated delay value to adjust the timing of this outgoing read data before sending it back to the system's memory controller.

This method allows the memory module to self-calibrate its timing. By observing the timing of incoming write commands and data, it can precisely control the timing of outgoing read data to ensure it arrives at the memory controller at the expected moment, thus maintaining system stability and performance.