Obviousness

Analysis of Obviousness for U.S. Patent No. 9,824,035

An analysis of U.S. Patent No. 9,824,035 ('035 patent) and the relevant prior art indicates that the independent claims would have been obvious to a Person Having Ordinary Skill in the Art (PHOSITA) at the time of the invention. The primary inventive concept—a memory module with distributed buffer circuits that self-calibrate read timing based on a prior write operation—represents a combination of known elements to solve a predictable problem. A strong case for obviousness can be made by combining the teachings of U.S. Patent Application Publication No. 2008/0126703 (Lee) and U.S. Patent No. 7,613,858 (Jeddeloh '858).

Summary of the Prior Art

• Lee (US 2008/0126703): This reference teaches a memory module architecture designed to improve signal integrity by using a buffer on the module's printed circuit board (PCB). The buffer is situated between the memory controller and the memory devices (DRAMs), effectively isolating the DRAMs from the main data bus. This reduces the electrical load on the memory controller, allowing for higher speeds and/or greater memory density. Lee's architecture is functionally analogous to the distributed "isolation devices" (118) described in the '035 patent, which serve the same load-reduction purpose. Lee provides the foundational hardware architecture of a buffered memory module.

• Jeddeloh '858 (US 7,613,858): This patent addresses the critical problem of timing skew on memory buses, which arises from unequal signal path lengths to different memory devices. Jeddeloh '858 discloses methods for "write leveling" and "read leveling" performed by the memory controller.

  • Write Leveling: The controller adjusts the timing of the data strobe (DQS) signal sent to each memory device to ensure it arrives synchronized with the system clock at the device's input.
  • Read Leveling: The controller initiates a read of a known data pattern from a memory device and then adjusts its own internal timing logic to correctly capture the incoming data and strobe.
    Jeddeloh '858 thus teaches the principle of measuring signal timing relationships and applying corrective delays to compensate for physical skews on the memory bus.

Obviousness of Independent Claim 1 (Apparatus Claim)

Claim 1 describes a memory module comprising memory devices, a module control device, and a plurality of distributed buffer circuits. The key limitation is that each buffer circuit includes logic to "obtain timing information based on signals received...during a second memory operation [e.g., a write]" and uses that information to "control timing of the data and strobe signals...in accordance with the timing information" during a "first memory operation [e.g., a read]."

A PHOSITA, starting with the buffered memory module architecture taught by Lee, would have recognized that while the buffers improve signal integrity by reducing electrical load, they do not solve—and may even highlight—the problem of timing skew. Signals originating from the system's memory controller (e.g., DQS) and signals from the on-module controller (e.g., command/control signals) would arrive at each physically distinct buffer at different times. This skew would make it difficult to precisely align the read data sent back from all buffers to the memory controller.

This is a well-known problem in the field. To solve it, a PHOSITA would have been motivated to look for existing solutions for timing calibration. Jeddeloh '858 provides such a solution by teaching write and read leveling. The motivation to combine the teachings would be to make the buffered module of Lee function reliably at high speeds.

It would have been obvious to a PHOSITA to implement the timing calibration function of Jeddeloh '858 within Lee's on-module buffers. Moving this intelligence from the main system controller (as in Jeddeloh) to the distributed buffers is a predictable design choice for several reasons:

1. Improved Granularity and Accuracy: Each buffer can perform a localized timing calibration for its specific data lines and memory devices, compensating for its unique signal flight time.
2. Reduced System Complexity: It offloads the complex task of per-buffer timing management from the main memory controller.
3. Solving a Known Problem: Applying a known timing solution (leveling) to a known architecture (buffered modules) to overcome a predictable problem (skew) is a classic example of obviousness as described in KSR Int'l Co. v. Teleflex Inc.

The specific implementation in the '035 patent—using a write operation to calibrate read timing—is a logical extension. The write strobe (DQS) arriving from the system controller provides a perfect timing reference for the path to each buffer. Using this known timing to adjust the launch time of the subsequent read data is a direct and obvious way to apply Jeddeloh's leveling principle within Lee's buffered architecture.

Obviousness of Independent Claim 15 (Method Claim)

Claim 15 recites a method of operating the memory module, which includes the steps of:

1. Receiving module control signals and a system data strobe (DQS) at a buffer during a write operation.
2. Determining the time interval between the arrival of these two signals.
3. Generating a delay value from this interval.
4. Using this delay value to adjust the timing of read data before transmitting it to the memory controller.

This method is the functional embodiment of the apparatus in Claim 1. The same rationale for combining Lee and Jeddeloh '858 applies.

• Lee provides the system in which the method operates (a module with buffers).
• Jeddeloh '858 teaches the core concept of the method: determining timing relationships during one operation (write or read training) and applying a corrective delay to subsequent operations.

A PHOSITA would be motivated to adapt Jeddeloh's '858 method to the Lee architecture. In the '035 patent's method, the buffer determines a time interval between receiving an enable signal from the on-module controller and receiving the write strobe from the system controller ('035 Patent, Col. 11, ll. 1-13; FIGS. 12A & 13). This interval (EWD) effectively measures the round-trip timing and skew for that specific buffer. Using this measurement to generate a delay value (DS) that is then applied to outgoing read data ('035 Patent, Col. 12, ll. 14-25; FIGS. 15 & 16) is a direct application of Jeddeloh's '858 principle of "leveling" to ensure the read data is correctly aligned when it reaches the system controller. It is a predictable implementation that a skilled artisan would devise to solve the timing skew inherent in the distributed buffer architecture of Lee.

Conclusion

The invention claimed in U.S. Patent No. 9,824,035 represents an obvious combination of prior art elements. The structural architecture of a buffered memory module was known from references like Lee. The functional concept of measuring timing relationships and applying corrective delays to compensate for signal skew was well-established by references like Jeddeloh '858. A person of ordinary skill in the art, seeking to improve the performance and reliability of high-density buffered memory modules, would have been motivated to implement the known timing calibration techniques within the known buffer architecture. This combination of established principles to achieve a predictable result renders the independent claims of the '035 patent obvious under 35 U.S.C. § 103.