Prior art

Analysis of Prior Art for U.S. Patent No. 9,824,035

This analysis details the most relevant prior art cited against U.S. Patent No. 9,824,035. The '935 patent, assigned to Netlist, Inc., describes a memory module with intelligent, distributed data buffers that can learn and adjust for signal timing variations. The key innovation lies in the buffer circuits' ability to obtain timing information from one memory operation (e.g., a write) and use it to control the timing of a subsequent, different operation (e.g., a read).

Under 35 U.S.C. § 102, a patent claim is anticipated if a single prior art reference discloses each and every element of the claim. The following cited references are evaluated for their potential to anticipate the independent claims (1 and 15) of the '935 patent.

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Key Cited References and Potential Anticipation:

The following patents were cited during the prosecution of the '935 patent and are considered relevant to its claims.

1. U.S. Patent No. 7,370,143 B2: "Memory Module with a Hub Device for Interfacing Memory Devices and a Memory Controller and Method for Operating the Same"

• Full Citation: U.S. Patent No. 7,370,143 B2
• Assignee: Rambus Inc.
• Publication Date: May 6, 2008
• Filing Date: June 30, 2003
• Brief Description: This patent describes a memory module with a central "hub" device that interfaces between a memory controller and multiple memory devices (DRAMs) on the module. The hub is designed to manage data transfers, perform signal retiming, and reduce the load on the memory controller. It includes circuitry to manage and buffer data, command, and address signals, effectively isolating the memory controller from the specifics of the DRAM devices.
• Potential to Anticipate Claims 1 & 15:
  • Argument for Anticipation: The '143 patent discloses a memory module with a central control device (the "hub") and memory devices. This hub acts as a buffer between the memory controller and the DRAMs, which is a core concept in the '935 patent. The hub is involved in timing adjustments and signal integrity management for data transfers.
  • Argument Against Anticipation: A key distinction is that the '935 patent specifies distributed buffer circuits, each associated with a respective set of memory devices. The '143 patent's hub is a centralized, rather than distributed, architecture. Furthermore, the '935 patent claims a specific method where a buffer learns timing from one operation (like a write) to apply a delay to another (like a read). While the '143 patent's hub manages timing, it does not explicitly describe this "learn and apply" mechanism where a time interval is measured during a write operation to generate a specific delay value for a subsequent read operation, as required by claim 15.

2. U.S. Patent No. 7,532,537 B2: "Memory Module with a Selectable Conduction Path"

• Full Citation: U.S. Patent No. 7,532,537 B2
• Assignee: Netlist, Inc.
• Publication Date: May 12, 2009
• Filing Date: September 1, 2006
• Brief Description: This patent, also from Netlist, discloses a high-capacity memory module that uses "isolation devices" (similar to the '935 patent's buffer circuits) to allow more memory ranks to be placed on a single module than a system's memory controller would normally support. The isolation devices selectively connect one of several ranks to the memory controller, effectively hiding the additional ranks and reducing the electrical load on the memory bus.
• Potential to Anticipate Claims 1 & 15:
  • Argument for Anticipation: This patent clearly teaches the use of distributed "isolation devices" or buffer circuits on a memory module to manage data paths between the controller and specific groups of memory devices. This directly relates to the structure described in claim 1.
  • Argument Against Anticipation: While the '537 patent establishes the foundational architecture of using distributed buffers for load reduction and rank multiplication, it does not appear to describe the specific timing self-calibration method claimed in the '935 patent. The focus of the '537 patent is on the selection and isolation of memory ranks, not on the dynamic measurement of a write-operation timing interval to control the timing of a subsequent read operation. Therefore, it likely does not anticipate the functional logic for timing control as detailed in claims 1 and 15 of the '935 patent.

3. U.S. Patent No. 8,516,185 B2: "Memory Module with a Plurality of Memory Devices and a Controller"

• Full Citation: U.S. Patent No. 8,516,185 B2
• Assignee: Netlist, Inc.
• Publication Date: August 20, 2013
• Filing Date: April 15, 2010
• Brief Description: This is a related patent from Netlist that is part of the same family as the '935 patent. It describes a memory module architecture with a module controller and distributed data buffers (referred to as "isolation devices"). The system is designed to allow the memory module to have more ranks than the host system's memory controller can directly address, using the module controller to translate commands.
• Potential to Anticipate Claims 1 & 15:
  • Argument for Anticipation: As a parent application, the '185 patent discloses the core architecture of the '935 patent, including the module control device, memory devices, and distributed buffer circuits.
  • Argument Against Anticipation: The '935 patent is a continuation of the application that led to the '185 patent. Continuation applications are typically filed to claim different aspects of the invention disclosed in the parent application. It is highly probable that the specific claims of the '935 patent—focusing on the buffer circuits obtaining timing information from a prior operation to control a subsequent one—were not explicitly claimed in the '185 patent. Therefore, while disclosing the necessary hardware, the '185 patent likely does not describe the specific timing-control method with sufficient detail to anticipate claims 1 and 15 of the '935 patent. The '935 patent's contribution is the refinement of how these distributed buffers manage timing.

4. U.S. Patent Application Publication No. 2006/0056269 A1: "Apparatus and Method for Calibrating Data Signal Timing in a Memory System"

• Full Citation: U.S. Patent Application Publication No. 2006/0056269 A1
• Assignee: Rambus Inc.
• Publication Date: March 16, 2006
• Filing Date: September 13, 2004
• Brief Description: This application describes a method for calibrating the timing of data signals in a memory system. It involves sending a training pattern from the memory controller to a memory device, which then returns a modified pattern. The controller analyzes the returned pattern to determine timing errors and adjusts the timing of subsequent data signals accordingly. This includes adjusting delay settings for read and write data paths.
• Potential to Anticipate Claims 1 & 15:
  • Argument for Anticipation: The '269 application teaches the concept of calibrating data signal timing by measuring and adjusting for delays. It involves using one operation (the training sequence) to gather information that is then used to control the timing of subsequent operations (normal reads/writes).
  • Argument Against Anticipation: The calibration process in the '269 application is initiated and controlled by the main memory controller, not by autonomous, distributed buffer circuits on the memory module itself. The '935 patent's novelty lies in the buffer circuits independently performing this timing determination and adjustment. In the '269 application, the memory device is a more passive participant in a controller-led training sequence, whereas in the '935 patent, the buffer circuit is an active component that measures and applies timing adjustments based on live memory commands, not just special training patterns.

Conclusion

While several prior art references disclose elements of the '935 patent, such as the use of buffer circuits on a memory module for load reduction and signal integrity, none appear to fully anticipate the independent claims. The key inventive concept of the '935 patent is the combination of a distributed buffer architecture with a specific self-calibration timing method. This method involves each buffer independently determining a timing interval from a first memory operation (e.g., write) and using that information to apply a calculated delay to a subsequent, different memory operation (e.g., read) to ensure proper data alignment with the system's memory controller. The cited prior art either describes a centralized architecture (Rambus '143), lacks the specific "learn and apply" timing method (Netlist '537), or describes a controller-driven calibration process rather than one performed autonomously by distributed buffers (Rambus '269).