Derivative works

Defensive Disclosure: US 9,824,035

Publication Date: May 13, 2026
Reference Patent: U.S. Patent No. 9,824,035 B2
Title: Memory module with timing-controlled data paths in distributed data buffers
Summary: This document discloses several derivative inventions and improvements upon the core concepts described in U.S. Patent No. 9,824,035. The purpose of this disclosure is to place these concepts into the public domain, thereby establishing them as prior art for any future patent applications. The core invention involves a memory module with distributed buffer circuits, where each buffer independently captures timing information from a write operation to calibrate the timing of a subsequent read operation.

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Derivative Embodiment Set 1: Based on Independent Claim 1 (Apparatus)

1.1. Material & Component Substitution

1.1.1. Cryogenic High-Frequency Substrate and Gallium Nitride (GaN) Buffer Circuits

• Enabling Description: This embodiment describes a memory module designed for operation in cryogenic environments (-180°C to -270°C), such as those used in quantum computing control planes or high-frequency trading servers. The module's printed circuit board (119) is constructed from a low-loss ceramic substrate, such as Alumina (Al₂O₃) or Aluminum Nitride (AlN), which exhibit superior dimensional stability and dielectric performance at low temperatures compared to standard FR-4. The buffer circuits (118) are fabricated using a Gallium Nitride (GaN) High-Electron-Mobility Transistor (HEMT) process instead of conventional CMOS. GaN's higher electron mobility and lower on-resistance result in significantly faster switching speeds and reduced propagation delays, enabling the timing control logic within the buffer to operate with picosecond-level precision. The delay control circuit (650) utilizes a GaN-based tapped delay line, where each tap provides a delay increment below 5ps, a resolution unachievable with standard CMOS at these temperatures. The memory devices (112) are specifically qualified low-temperature DRAMs. This configuration allows the on-the-fly timing calibration to compensate for thermal-gradient-induced signal skew across the module as it cools.

• Diagram:

  graph TD
      subgraph Memory Module (Cryogenic)
          A[Memory Controller Interface] --> B{Module Control Device};
          B --> C1[GaN Buffer 1];
          B --> C2[GaN Buffer 2];
          B --> C3[GaN Buffer N];
          C1 --> D1[Memory Devices - Group 1];
          C2 --> D2[Memory Devices - Group 2];
          C3 --> D3[Memory Devices - Group N];
      end
      subgraph Substrate
          S[Ceramic Substrate (AlN)]
      end
      subgraph Components
          GaN[GaN HEMT Buffer Circuit];
          DRAM[Low-Temperature DRAM];
      end
      style S fill:#dae8fc,stroke:#333,stroke-width:2px
      style GaN fill:#d5f5e3,stroke:#333,stroke-width:2px
  

1.1.2. Reconfigurable Timing Logic via Embedded FPGA Buffers

• Enabling Description: In this variant, the dedicated ASIC buffer circuits (118) are replaced with small, low-power Field-Programmable Gate Arrays (FPGAs). Each FPGA is co-packaged with a group of memory devices. The "logic" described in the patent is implemented as soft IP cores within the FPGA. This includes a Time-to-Digital Converter (TDC) core to measure the EWD (Enable-to-Write Data delay) and a digitally-controlled delay line (DCDL) core to apply the DS (Delay Signal) to the read path. This approach allows the timing calibration algorithm itself to be updated in the field via a firmware update delivered over the system's SMBus. For example, the algorithm could be switched from a simple last-write measurement to a moving-average or a Kalman filter-based estimation of the timing drift, adapting to different system workloads or aging effects without requiring a hardware revision.

• Diagram:

  sequenceDiagram
      participant MCH as Memory Controller
      participant MCD as Module Control Device
      participant FPGA_Buffer as FPGA Buffer
      participant DRAM as Memory Devices
  
      MCH->>MCD: Write Command
      MCD->>FPGA_Buffer: Module Control Signal (MCS)
      FPGA_Buffer->>FPGA_Buffer: Start TDC Counter
      MCH->>FPGA_Buffer: Write DQS
      FPGA_Buffer->>FPGA_Buffer: Stop TDC Counter; Calculate Delay
      FPGA_Buffer->>DRAM: Write Data
      Note over FPGA_Buffer: Stores calculated delay value
      MCH->>MCD: Read Command
      MCD->>FPGA_Buffer: Module Control Signal (MCS)
      DRAM-->>FPGA_Buffer: Read Data
      FPGA_Buffer->>FPGA_Buffer: Apply Stored Delay
      FPGA_Buffer-->>MCH: Delayed Read Data
  

1.2. Operational Parameter Expansion

1.2.1. High-Radiation Environment with Redundant Timing Logic

• Enabling Description: A memory module for aerospace or nuclear applications is constructed using radiation-hardened components. The buffer circuit (118) is designed with Triple Modular Redundancy (TMR) for its critical logic, including the counter circuit (1330) and the registers storing the final delay value DS. The device contains three identical logic paths for timing measurement. A voter circuit compares the outputs of the three paths. If a Single Event Upset (SEU) caused by a high-energy particle corrupts one of the counters, the voter circuit discards the erroneous value and uses the result from the other two, ensuring the applied read delay remains correct. The buffer circuit also monitors the system's EDAC (Error Detection and Correction) flags. A high rate of correctable memory errors can trigger an automatic recalibration cycle, assuming the errors may be timing-related due to radiation-induced drift.

• Diagram:

  graph TD
      subgraph Rad-Hard Buffer
          Input[MCS, DQS] --> Logic1(Timing Logic A);
          Input --> Logic2(Timing Logic B);
          Input --> Logic3(Timing Logic C);
          Logic1 --> Voter;
          Logic2 --> Voter;
          Logic3 --> Voter;
          Voter -- Majority Vote --> Register(Store Correct Delay 'DS');
          Register --> DelayLine(Apply Delay to Read Path);
          ReadPath_In[Read Data In] --> DelayLine;
          DelayLine --> ReadPath_Out[Read Data Out];
      end
  

1.3. Cross-Domain Application

1.3.1. Automotive LiDAR Sensor Synchronization

• Enabling Description: This concept is applied to an automotive LiDAR (Light Detection and Ranging) system. The "memory module" is a sensor array board, and the "memory devices" are individual laser/detector pairs. A central processing unit (the "memory controller") sends a global "fire laser" command (analogous to a write command) to all sensor modules via a module control device. Due to varying cable lengths and thermal conditions across the vehicle chassis, this command arrives at different times. Each sensor module contains a buffer circuit (118). This buffer measures the time delta between the arrival of the "fire laser" command and a synchronized master clock signal (analogous to DQS) distributed to all modules. It stores this delta as a timing offset. When a photon is detected by the sensor (analogous to a read operation), the buffer applies the stored offset to the timestamp of the detection event before forwarding it to the central processor. This calibration ensures that the time-of-flight calculations for all points in the LiDAR cloud share a common, highly accurate time reference, dramatically improving the accuracy of the 3D environmental map.

• Diagram:

  flowchart LR
      subgraph LiDAR System
          A[Central ECU] -- Fire Command --> B(Control Hub);
          A -- Master Clock --> B;
          B -- Fire Pulse 1 --> C1(Sensor Buffer 1);
          B -- Master Clock --> C1;
          B -- Fire Pulse 2 --> C2(Sensor Buffer 2);
          B -- Master Clock --> C2;
          C1 -- Calibrated Fire --> D1[Laser/Detector 1];
          C2 -- Calibrated Fire --> D2[Laser/Detector 2];
          D1 -- Photon Detect --> C1;
          D2 -- Photon Detect --> C2;
          C1 -- Time-Corrected Data --> A;
          C2 -- Time-Corrected Data --> A;
      end
      C1 -- Measures Δt1 --> C1;
      C2 -- Measures Δt2 --> C2;
  

1.4. Integration with Emerging Tech

1.4.1. AI-Based Predictive Thermal Drift Compensation

• Enabling Description: The buffer circuit (118) is enhanced with an integrated temperature sensor and a lightweight machine learning inference engine (e.g., a Bonsai-style decision tree or a quantized neural network). During system operation, the buffer continuously measures the EWD interval as described in the patent and correlates it with the on-chip temperature reading. This data builds a model of how timing skews as a function of temperature and workload intensity (inferred from the frequency of commands). The ML engine then proactively adjusts the read data path delay (DS) based on the predicted skew for the current temperature, rather than simply using the last measured skew. For example, if the temperature rapidly increases, the model predicts the impending timing drift and applies a counter-acting delay before any timing errors can occur, improving system reliability under dynamic thermal loads.

• Diagram:

  stateDiagram-v2
      state "Monitoring & Learning" as ML
      state "Predictive Adjustment" as PA
      [*] --> Idle
      Idle --> ML : Write Operation
      ML --> ML : Measure(EWD, Temp)
      ML --> ML : Update Model(EWD, Temp)
      ML --> Idle : Write Complete
      Idle --> PA : Read Operation
      PA --> PA : Read Current Temp
      PA --> PA : Predict Skew(Temp)
      PA --> PA : Calculate DS_predictive
      PA --> Idle : Apply DS_predictive & Send Data
  

1.5. The "Inverse" or Failure Mode

1.5.1. Failsafe Operation with Graceful Performance Degradation

• Enabling Description: The buffer circuit's delay control logic (650) is augmented with a "sanity checker" and a failsafe path. The sanity checker is a simple digital comparator that continuously monitors the calculated delay value DS. If DS falls outside a pre-determined valid window (e.g., +/- 1 clock cycle of a nominal value), which is programmed into an eFuse during manufacturing, it indicates a fault in the measurement logic. Upon detecting an invalid DS value, the checker triggers a multiplexer to switch the read data path away from the variable delay line (1660) and through a fixed, conservative delay path. Simultaneously, it asserts an alert signal on a sideband pin (e.g., connecting to the system's SMBus) to notify the host BIOS or OS of the fault condition. This prevents a timing miscalculation from causing a catastrophic system crash, allowing the system to continue operating in a "limp mode" with safe, albeit non-optimal, memory timing until the module can be serviced.

• Diagram:

  graph TD
      subgraph Failsafe Buffer
          A[Read Data In] --> MUX;
          subgraph Dynamic Path
              A1[Variable Delay Line] --> B1[Output];
          end
          subgraph Failsafe Path
              A2[Fixed Delay Line] --> B2[Output];
          end
          A1 -- "Controlled by DS" --> MUX;
          A2 --> MUX;
          
          C[Delay Control Logic] -- "Calculates DS" --> DS_Val(DS);
          DS_Val --> D{Sanity Check};
          D -- "DS is Valid" --> Ctrl(Control MUX to select Dynamic Path);
          D -- "DS is Invalid" --> Failsafe(Control MUX to select Failsafe Path);
          Failsafe --> Alert[Assert ALERT_N pin];
          
          MUX --> E[Read Data Out];
      end
  

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Derivative Embodiment Set 2: Based on Independent Claim 15 (Method)

2.1. Material & Component Substitution

2.1.1. Method using Analog Phase Interpolation for Delay Generation

• Enabling Description: This method refines step 1830 ("generating a delay signal DS"). Instead of a digital counter producing a discrete delay value, the buffer circuit employs an analog delay-locked loop (DLL) or phase interpolator. The time interval EWD between the module control signal and the write DQS is measured and converted to a control voltage via a time-to-voltage converter. This analog voltage is then used to control the phase interpolator in the read path. The interpolator mixes two quadrature-phase clock signals to produce an output clock (RDQS) with a continuously variable phase offset that precisely matches the required delay. This analog approach provides much finer delay resolution (sub-picosecond) than a digital tapped delay line, enabling more accurate timing alignment for extremely high data rates (e.g., >25 GT/s) where digital step sizes would be too coarse.

• Diagram:

  flowchart TD
      A[Receive Write MCS] --> T1(Start Time-to-Voltage Ramp);
      B[Receive Write DQS] --> T2(Stop Ramp & Hold Voltage);
      T2 -- Control Voltage V_ctrl --> C{Analog Phase Interpolator};
      D[Receive Read Data from DRAM] --> E[Latch with System Clock];
      E --> C;
      C -- Applies V_ctrl-based phase shift --> F[Output Read Data to Host];
  

2.2. Cross-Domain Application

2.2.1. Method for Distributed Ledger Timestamp Synchronization

• Enabling Description: This method applies the '035 patent's timing calibration to a distributed network of blockchain nodes. Each node acts as a "buffer circuit." A "write command" is a consensus-critical message (e.g., a block proposal) broadcast from a leader node (the "module control device"). Each receiving node executes the method. It receives the proposal (analogous to the module control signal) and also receives a periodic, high-precision timing beacon from a network time protocol (NTP) or GPS source (analogous to the DQS signal). The node measures the time interval between the receipt of the proposal and the next timing beacon. This interval represents the network latency for that specific message. When this node creates its own transactions for the next block (a "read operation"), it adjusts their timestamps by this measured latency value. This process ensures that timestamps across all nodes are corrected for network propagation delay, leading to a more fair and accurate transaction ordering within the distributed ledger.

• Diagram:

  sequenceDiagram
      participant Leader
      participant Node_A
      participant Node_B
      participant TimeSource as GPS/NTP
  
      loop Every Second
          TimeSource->>Node_A: Time Beacon
          TimeSource->>Node_B: Time Beacon
      end
  
      Leader->>Node_A: Block Proposal (t1)
      Note over Node_A: Measures Δt between Proposal and next Beacon
      Leader->>Node_B: Block Proposal (t2)
      Note over Node_B: Measures Δt between Proposal and next Beacon
  
      Node_A->>Node_A: Create Transaction
      Node_A->>Node_A: Adjust Timestamp using Δt
      Node_B->>Node_B: Create Transaction
      Node_B->>Node_B: Adjust Timestamp using Δt
  

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Combination Prior Art Scenarios

1. Integration with Compute Express Link (CXL) Protocol

• Description: The memory module apparatus of claim 1 is implemented as a CXL Type 3 memory device. The module control device (116) acts as a CXL endpoint, receiving and decoding CXL.mem protocol FLITs (Flow Control Units) from the host CPU. The "module control signals" sent to the buffer circuits (118) are derived from the commands within these FLITs (e.g., MemWr, MemRd). The "data strobe signal" is the CXL link's differential clock. The buffer circuits (118) perform the claimed method of measuring the time between the decoded CXL command arriving from the on-module CXL endpoint and the physical CXL clock edge. This locally-derived delay value (DS) is then used to fine-tune the timing of read data being returned to the CXL endpoint for packaging into CXL.mem Data FLITs. This method supplements the standard CXL PHY-level link training by providing continuous, per-buffer-chip timing calibration to compensate for on-module thermal and voltage variations not visible to the host controller.

2. Integration with RISC-V and the I²C Open Standard

• Description: The module control device (116) incorporates an open-source, 32-bit RISC-V microcontroller core (e.g., a VexRiscv core). The firmware running on this core is responsible for receiving commands from the host memory controller and generating the internal module control signals. Each buffer circuit (118) implements the timing measurement method of claim 15. The resulting delay value (DS) is stored in a register accessible via an I²C (Inter-Integrated Circuit) slave interface, an open standard. The RISC-V core on the module controller acts as the I²C master, polling each buffer circuit periodically to read its currently calibrated delay value. This allows the central on-module intelligence (the RISC-V core) to build a complete timing map of the module, log it, and potentially perform more advanced system-wide optimizations, such as throttling memory access to a specific group of DRAMs if its corresponding buffer reports a dangerously high timing drift.

3. Integration with the AMBA AXI4-Stream Open Standard

• Description: The on-module communication between the module control device (116) and the distributed buffer circuits (118) is implemented using the open AMBA AXI4-Stream protocol. The module control signals are encapsulated as packets and transmitted over a lightweight, point-to-multipoint AXI4-Stream bus (TVALID, TDATA, TLAST). Each buffer circuit (118) has an AXI4-Stream slave interface. When a buffer circuit performs the timing measurement of claim 15, it captures the arrival time of the TLAST signal for the write command packet. It then measures the interval until the arrival of the write DQS from the host. During a read operation, when the buffer sends read data back towards the module control device, it does so over another AXI4-Stream bus, using the TUSER sideband signal to embed the calculated delay value (DS) alongside the read data. This allows the module control device to be aware of the exact timing compensation being applied by each individual buffer.