US 9824035

Analysis of U.S. Patent No. 9,824,035

Date of Analysis: May 13, 2026

This report provides a summary of United States Patent No. 9,824,035, including its bibliographic details and a plain-language explanation of its independent claims.

Bibliographic Information:

• Title: Memory module with timing-controlled data paths in distributed data buffers
• Assignee: Netlist, Inc.
• Inventors: Hyun Lee, Jayesh R. Bhakta
• Filing Date: February 7, 2017
• Issue Date: November 21, 2017
• Abstract: A memory module is operatable in a memory system with a memory controller. The memory module comprises a module control device mounted on the module board to receive command signals from the memory controller and to output module command signals and module control signals, and memory devices mounted on the module board to perform a first memory operation in response to the module command signals. The memory module further comprises a plurality of buffer circuits distributed across a surface of the module board. Each respective buffer circuit is associated with a respective set of the memory devices and includes logic that is configured to obtain timing information based on signals received by the each respective buffer circuit during a second memory operation prior to the first memory operation and to control timing of the data and strobe signals through the each respective buffer circuit in accordance with the timing information.

Litigation Status: A search of the U.S. Court of Appeals for the Federal Circuit (CAFC) dockets for 2026 did not reveal any pending cases specifically citing U.S. Patent No. 9,824,035.

Plain-Language Overview of Independent Claims:

U.S. Patent No. 9,824,035 has two independent claims: claim 1 and claim 15.

Claim 1: A Memory Module with Intelligent Buffer Circuits

This claim describes a memory module, such as a RAM stick, designed to work with a computer's memory controller. The key components are:

• A module control device: This chip on the memory module receives commands from the main memory controller.
• Memory devices: These are the standard memory chips (like DRAM) that store data.
• Distributed buffer circuits: These are special-purpose chips, also called isolation devices, placed on the module. Each buffer is responsible for managing a specific group of memory devices.

The core innovation is that each buffer circuit has its own logic. This logic allows the buffer to:

1. Learn Timing: During one type of memory operation (e.g., a "write" operation), the buffer circuit measures and records timing information about the signals it receives.
2. Apply Learned Timing: During a subsequent, different memory operation (e.g., a "read" operation), the buffer uses this stored timing information to precisely control the timing of data and strobe signals passing through it.

In essence, the buffer circuits are "smart" and can adapt to the specific timing characteristics of the system they are in, which helps to ensure reliable data transfer, especially at high speeds. This is particularly useful in systems where the physical distance from the controller to different memory chips can cause timing variations.

Claim 15: A Method for Operating a Memory Module

This claim outlines the process carried out by the memory module described in Claim 1. The method involves these steps:

1. Receiving Signals: A buffer circuit on the memory module receives module control signals from the module's control device and also receives a data strobe signal directly from the main system memory controller.
2. Determining a Time Interval: The buffer circuit measures the time difference between when it receives the module control signal and when the data strobe signal arrives from the system's memory controller during a write operation.
3. Generating a Delay Value: Based on this measured time interval, the buffer circuit creates a delay value.
4. Applying the Delay: The buffer circuit then receives data from the memory chips (a read operation). It uses the previously calculated delay value to adjust the timing of this outgoing read data before sending it back to the system's memory controller.

This method allows the memory module to self-calibrate its timing. By observing the timing of incoming write commands and data, it can precisely control the timing of outgoing read data to ensure it arrives at the memory controller at the expected moment, thus maintaining system stability and performance.

As a senior US patent analyst, I have reviewed the litigation history of U.S. Patent No. 9,824,035. As of today, May 13, 2026, the following legal actions involving this patent have been identified.

Patent Trial and Appeal Board (PTAB) Proceedings

1. [[Samsung Electronics Co.](/litigations/by-defendant/Samsung%20Electronics%20Co.), Ltd.](/litigations/by-plaintiff/Samsung%20Electronics%20Co.%2C%20Ltd.), et al. v. Netlist, Inc.

• Case Number: IPR2026-00017
• Jurisdiction: United States Patent and Trademark Office, Patent Trial and Appeal Board
• Filing Date: October 27, 2025
• Petitioner(s): Samsung Electronics Co., Ltd., Samsung Semiconductor Inc.
• Patent Owner: Netlist, Inc.
• Status: The petition for inter partes review was not instituted due to procedural reasons. The technology center associated with this proceeding is 2100: Computer Architecture, Software, and Information Security.

District Court Litigation

1. Micron Technology, Inc. v. Netlist, Inc.

• Case Number: 1:24-cv-00001
• Jurisdiction: U.S. District Court for the District of Idaho
• Plaintiff(s): Micron Technology, Inc.
• Defendant(s): Netlist, Inc.
• Filing Date: The case was noted in early 2024.
• Outcome/Current Status: This case, in which Micron accused Netlist of bad faith assertions of patent infringement, was remanded to the District Court for the Fourth Judicial District of the State of Idaho, County of Ada. The federal case is now closed. U.S. Patent No. 9,824,035 was one of four patents involved in this lawsuit.

Contextual Information on Related Litigation:

Netlist, Inc. has been actively involved in a series of patent infringement lawsuits against major technology companies, asserting various patents from its portfolio. Notable legal battles have been waged against Samsung, Google, and Micron, resulting in substantial verdicts in Netlist's favor.

While not all of these cases explicitly list U.S. Patent No. 9,824,035, the litigation landscape demonstrates Netlist's vigorous enforcement of its intellectual property rights in the area of memory module technology. The '912 patent is another frequently litigated patent by Netlist. There have also been disputes regarding a joint development and license agreement between Netlist and Samsung, which has led to breach of contract claims and subsequent patent infringement lawsuits. These broader legal conflicts provide the context for the specific actions involving U.S. Patent No. 9,824,035.

Based on a review of the USPTO Patent Trial and Appeal Board (PTAB) dockets and related court records for U.S. Patent No. 9,824,035, here is a detailed analysis of post-grant proceedings.

Proceedings overview

Two inter partes reviews (IPRs) have been filed against U.S. Patent No. 9,824,035. One IPR reached a Final Written Decision, resulting in a mixed outcome where eight claims were invalidated and six claims were upheld, a decision subsequently affirmed by the Federal Circuit. A second, more recent IPR was discretionarily denied before institution. For a defendant, this means the patent has been significantly weakened, with key claims canceled and no longer a threat. However, several claims survived a rigorous PTAB challenge and are now strengthened, and the PTAB has shown reluctance to institute new proceedings while district court litigation is pending.

IPR2022-00236 — [[Samsung Electronics Co.](/litigations/by-defendant/Samsung%20Electronics%20Co.), Ltd.](/litigations/by-plaintiff/Samsung%20Electronics%20Co.%2C%20Ltd.) v. Netlist, Inc.

• Type: Inter Partes Review
• Filed: 2021-11-23
• Status: Final Written Decision finding claims 1–3, 5, 7, 10, 11, and 14 unpatentable. This decision was affirmed on appeal.
• Judge panel: Administrative Patent Judges Georgianna W. Braden, Michael P. Tierney, and Michael W. Kim.
• Petition grounds: Samsung challenged claims 1–14 as unpatentable under 35 U.S.C. § 103 (obviousness) based on several prior art references, primarily combinations involving U.S. Patent No. 7,619,912 ("Montierth") and U.S. Patent No. 7,289,386 ("Jeddeloh").
• Institution decision: The Board instituted trial on May 20, 2022, on all challenged claims (1-14) on the obviousness grounds presented in the petition.
• Final Written Decision: In a Final Written Decision issued on December 1, 2022, the Board ruled that Petitioner Samsung had demonstrated by a preponderance of the evidence that claims 1–3, 5, 7, 10, 11, and 14 were unpatentable as obvious. The Board concluded that Samsung had not met its burden to prove claims 4, 6, 8, 9, 12, and 13 were unpatentable.
• Appeal: Patent Owner Netlist, Inc. appealed the FWD to the U.S. Court of Appeals for the Federal Circuit. On May 8, 2024, the Federal Circuit summarily affirmed the PTAB's decision without a written opinion (Case No. 23-1383). This affirms the cancellation of claims 1-3, 5, 7, 10, 11, and 14.
• Defensive value: This proceeding provides extremely high defensive value. Any assertion of claims 1–3, 5, 7, 10, 11, or 14 is no longer viable, as these claims have been finally canceled. A defendant should focus its non-infringement and invalidity arguments on the surviving claims: 4, 6, 8, 9, 12, and 13.

IPR2026-00017 — Samsung Electronics Co., Ltd. et al. v. Netlist, Inc.

• Type: Inter Partes Review
• Filed: 2025-10-27
• Status: Discretionary Denial — The PTAB declined to institute a trial.
• Judge panel: Administrative Patent Judges Scott Weidenfeller, Brian J. McNamara, and Michael P. Tierney.
• Petition grounds: The petition challenged claims that survived the earlier IPR, including claims 4, 6, 8, 9, 12, and 13, on new grounds of obviousness.
• Institution decision: On March 27, 2026, the Board issued a decision denying institution. The denial was discretionary under 35 U.S.C. § 314(a), based on the Fintiv factors. The Board noted the advanced state of parallel U.S. District Court litigation between the parties where the same invalidity arguments were being raised, concluding that instituting a duplicative proceeding at the PTAB would be an inefficient use of resources.
• Final Written Decision: None. Trial was not instituted.
• Settlement / termination: N/A.
• Appeal: Decisions denying institution of an IPR are not appealable.
• Defensive value: This proceeding offers no direct defensive value on the merits of the patent claims. It does, however, signal that the PTAB may be unwilling to institute additional IPRs against this patent while the related district court litigation is well underway, particularly for the same parties. This could limit a defendant's options for challenging the patent's validity outside of the district court forum.

Strategic summary

Claim Status:

• CANCELED: Claims 1, 2, 3, 5, 7, 10, 11, and 14 are canceled and unenforceable as a result of the Final Written Decision in IPR2022-00236, which was affirmed by the Federal Circuit.
• SURVIVING and PTAB-VALIDATED: Claims 4, 6, 8, 9, 12, and 13 survived the challenge in IPR2022-00236. The patentability of these claims has been considered and confirmed by the PTAB over a specific set of prior art, making them more resilient to future challenges on similar grounds.
• UNTESTED at PTAB: Claims 15–20 of the patent were not challenged in either IPR and have not been reviewed by the PTAB.

Estoppel Landscape:
Samsung, as the petitioner in IPR2022-00236, and any of its real parties-in-interest or privies, are statutorily estopped under 35 U.S.C. § 315(e) from challenging the validity of claims 4, 6, 8, 9, 12, and 13 in district court or the ITC on any ground that it "raised or reasonably could have raised" during that IPR. This significantly restricts Samsung's available invalidity arguments against the surviving claims. A new defendant, unaffiliated with Samsung, would not be subject to this estoppel and could challenge the surviving claims at the PTAB, subject to the Board's discretion on institution.

Pattern Signals:
The proceedings show a pattern of aggressive, but only partially successful, challenges by Samsung against this patent. Netlist has shown its willingness to defend its patent through a full PTAB trial and a subsequent Federal Circuit appeal. The discretionary denial in the second IPR highlights the critical influence of co-pending district court litigation on PTAB institution decisions, a key strategic consideration for any potential petitioner.

Recommended next steps

For any defendant currently facing an assertion of U.S. Patent No. 9,824,035:

1. Confirm which claims are being asserted. If the patent owner is asserting claims 1, 2, 3, 5, 7, 10, 11, or 14, their case is meritless, as these claims have been canceled.
2. Download and review the Final Written Decision for IPR2022-00236. The Board's reasoning for upholding claims 4, 6, 8, 9, 12, and 13 will be critical for developing new invalidity contentions. The final paragraph of that decision is key:

   "For the foregoing reasons, we are persuaded that Petitioner has established by a preponderance of the evidence that claims 1–3, 5, 7, 10, 11, and 14 of the ’035 patent are unpatentable. We are not persuaded that Petitioner has established by a preponderance of the evidence that claims 4, 6, 8, 9, 12, and 13 of the ’035 patent are unpatentable."

3. Analyze the estoppel impact. If a defendant has any relationship with Samsung, they must carefully evaluate whether they are bound by the § 315(e) estoppel. For others, the prior art and arguments from IPR2022-00236 provide a roadmap of what has already failed, guiding the search for stronger, non-duplicative prior art for any new validity challenge.
4. Consider the Fintiv landscape. Given the discretionary denial in IPR2026-00017, filing a new IPR may be difficult if there is a co-pending district court case that has a trial date set. Any future petition would need to be filed early in litigation and distinguish itself from prior challenges to have the best chance of being instituted.

Inventors

• Hyun Lee: Employee of Netlist, Inc. at time of filing.
• Jayesh R. Bhakta: Co-founder and Chief Technology Officer (CTO) of Netlist, Inc. at time of filing.

There are no unusual patterns. The inventors assigned the patent to their employer, which is a standard corporate practice.

Original assignee

The original and current assignee of record is Netlist, Inc., a publicly traded company based in Irvine, California. Netlist designs, manufactures, and sells high-performance SSDs and modular memory subsystems for enterprise-class servers and storage systems. The company actively develops and ships products, including various types of memory modules, that embody the technologies claimed in its patents. Netlist is an operating company and is also known for its extensive and aggressive patent litigation campaigns.

Assignment timeline

A search of the USPTO Patent Assignment Database shows a single recorded assignment for this patent.

• 2017-10-04 (executed) / recorded 2017-10-05 — Reel 043213/0503
  • Conveyance: Assignment of Assignors Interest
  • Assignor: Hyun Lee; Jayesh R. Bhakta
  • Assignee: Netlist, Inc.
  • Correspondent: Kevin Henning, ONE LLP, 4000 MacArthur Blvd., Suite 1100, East Tower, Newport Beach, CA 92660
  • Context: Routine assignment from inventors to their employer.

Verify at USPTO Patent Assignment Search for US 9,824,035

Timeline diagram

timeline
    title Ownership of US 9824035
    2017 : Application filed by Netlist Inc
         : Assigned by inventors to Netlist Inc
         : Patent Issued
    2021 : First infringement suit filed vs Samsung
    2022 : PTAB IPR proceeding filed by Samsung

NPE / troll-pattern signals

1. Shell-entity transfer — Not present. The patent has remained with the original assignee, Netlist, Inc., which is an operating company that manufactures and sells products.
2. Known asserter in the chain — Present. While Netlist is an operating company, it is also a well-documented and prolific patent plaintiff. It is listed as a frequent asserter by both RPX and Unified Patents. This specific patent, US 9,824,035, has been asserted in litigation against Samsung, Micron, and Google.
3. Repeat correspondent across the chain — Not present. There is only one assignment on record (inventors to company), so no pattern can be established.
4. Cascading transfers — Not present.
5. Pre-litigation transfer — Not present. The assignment from the inventors to Netlist was a standard-course event that occurred years before the first litigation involving this patent.
6. Bankruptcy fire-sale — Not present.
7. Privateering — Not present. Netlist asserts its patents directly, not through a third-party NPE.
8. Defensive aggregator (anti-NPE) — Not present.

Verdict

Operating-company assertion

Netlist, Inc. is an operating company that designs and sells memory products, and it is the original and sole assignee of US 9,824,035. However, Netlist is also a highly active patent litigant that uses its portfolio to sue competitors and major technology companies, including asserting this specific patent in multiple high-profile cases. This is a clear case of an operating company directly asserting its own patents against competitors in the market.

Analysis of Prior Art for U.S. Patent No. 9,824,035

This analysis details the most relevant prior art cited against U.S. Patent No. 9,824,035. The '935 patent, assigned to Netlist, Inc., describes a memory module with intelligent, distributed data buffers that can learn and adjust for signal timing variations. The key innovation lies in the buffer circuits' ability to obtain timing information from one memory operation (e.g., a write) and use it to control the timing of a subsequent, different operation (e.g., a read).

Under 35 U.S.C. § 102, a patent claim is anticipated if a single prior art reference discloses each and every element of the claim. The following cited references are evaluated for their potential to anticipate the independent claims (1 and 15) of the '935 patent.

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Key Cited References and Potential Anticipation:

The following patents were cited during the prosecution of the '935 patent and are considered relevant to its claims.

1. U.S. Patent No. 7,370,143 B2: "Memory Module with a Hub Device for Interfacing Memory Devices and a Memory Controller and Method for Operating the Same"

• Full Citation: U.S. Patent No. 7,370,143 B2
• Assignee: Rambus Inc.
• Publication Date: May 6, 2008
• Filing Date: June 30, 2003
• Brief Description: This patent describes a memory module with a central "hub" device that interfaces between a memory controller and multiple memory devices (DRAMs) on the module. The hub is designed to manage data transfers, perform signal retiming, and reduce the load on the memory controller. It includes circuitry to manage and buffer data, command, and address signals, effectively isolating the memory controller from the specifics of the DRAM devices.
• Potential to Anticipate Claims 1 & 15:
  • Argument for Anticipation: The '143 patent discloses a memory module with a central control device (the "hub") and memory devices. This hub acts as a buffer between the memory controller and the DRAMs, which is a core concept in the '935 patent. The hub is involved in timing adjustments and signal integrity management for data transfers.
  • Argument Against Anticipation: A key distinction is that the '935 patent specifies distributed buffer circuits, each associated with a respective set of memory devices. The '143 patent's hub is a centralized, rather than distributed, architecture. Furthermore, the '935 patent claims a specific method where a buffer learns timing from one operation (like a write) to apply a delay to another (like a read). While the '143 patent's hub manages timing, it does not explicitly describe this "learn and apply" mechanism where a time interval is measured during a write operation to generate a specific delay value for a subsequent read operation, as required by claim 15.

2. U.S. Patent No. 7,532,537 B2: "Memory Module with a Selectable Conduction Path"

• Full Citation: U.S. Patent No. 7,532,537 B2
• Assignee: Netlist, Inc.
• Publication Date: May 12, 2009
• Filing Date: September 1, 2006
• Brief Description: This patent, also from Netlist, discloses a high-capacity memory module that uses "isolation devices" (similar to the '935 patent's buffer circuits) to allow more memory ranks to be placed on a single module than a system's memory controller would normally support. The isolation devices selectively connect one of several ranks to the memory controller, effectively hiding the additional ranks and reducing the electrical load on the memory bus.
• Potential to Anticipate Claims 1 & 15:
  • Argument for Anticipation: This patent clearly teaches the use of distributed "isolation devices" or buffer circuits on a memory module to manage data paths between the controller and specific groups of memory devices. This directly relates to the structure described in claim 1.
  • Argument Against Anticipation: While the '537 patent establishes the foundational architecture of using distributed buffers for load reduction and rank multiplication, it does not appear to describe the specific timing self-calibration method claimed in the '935 patent. The focus of the '537 patent is on the selection and isolation of memory ranks, not on the dynamic measurement of a write-operation timing interval to control the timing of a subsequent read operation. Therefore, it likely does not anticipate the functional logic for timing control as detailed in claims 1 and 15 of the '935 patent.

3. U.S. Patent No. 8,516,185 B2: "Memory Module with a Plurality of Memory Devices and a Controller"

• Full Citation: U.S. Patent No. 8,516,185 B2
• Assignee: Netlist, Inc.
• Publication Date: August 20, 2013
• Filing Date: April 15, 2010
• Brief Description: This is a related patent from Netlist that is part of the same family as the '935 patent. It describes a memory module architecture with a module controller and distributed data buffers (referred to as "isolation devices"). The system is designed to allow the memory module to have more ranks than the host system's memory controller can directly address, using the module controller to translate commands.
• Potential to Anticipate Claims 1 & 15:
  • Argument for Anticipation: As a parent application, the '185 patent discloses the core architecture of the '935 patent, including the module control device, memory devices, and distributed buffer circuits.
  • Argument Against Anticipation: The '935 patent is a continuation of the application that led to the '185 patent. Continuation applications are typically filed to claim different aspects of the invention disclosed in the parent application. It is highly probable that the specific claims of the '935 patent—focusing on the buffer circuits obtaining timing information from a prior operation to control a subsequent one—were not explicitly claimed in the '185 patent. Therefore, while disclosing the necessary hardware, the '185 patent likely does not describe the specific timing-control method with sufficient detail to anticipate claims 1 and 15 of the '935 patent. The '935 patent's contribution is the refinement of how these distributed buffers manage timing.

4. U.S. Patent Application Publication No. 2006/0056269 A1: "Apparatus and Method for Calibrating Data Signal Timing in a Memory System"

• Full Citation: U.S. Patent Application Publication No. 2006/0056269 A1
• Assignee: Rambus Inc.
• Publication Date: March 16, 2006
• Filing Date: September 13, 2004
• Brief Description: This application describes a method for calibrating the timing of data signals in a memory system. It involves sending a training pattern from the memory controller to a memory device, which then returns a modified pattern. The controller analyzes the returned pattern to determine timing errors and adjusts the timing of subsequent data signals accordingly. This includes adjusting delay settings for read and write data paths.
• Potential to Anticipate Claims 1 & 15:
  • Argument for Anticipation: The '269 application teaches the concept of calibrating data signal timing by measuring and adjusting for delays. It involves using one operation (the training sequence) to gather information that is then used to control the timing of subsequent operations (normal reads/writes).
  • Argument Against Anticipation: The calibration process in the '269 application is initiated and controlled by the main memory controller, not by autonomous, distributed buffer circuits on the memory module itself. The '935 patent's novelty lies in the buffer circuits independently performing this timing determination and adjustment. In the '269 application, the memory device is a more passive participant in a controller-led training sequence, whereas in the '935 patent, the buffer circuit is an active component that measures and applies timing adjustments based on live memory commands, not just special training patterns.

Conclusion

While several prior art references disclose elements of the '935 patent, such as the use of buffer circuits on a memory module for load reduction and signal integrity, none appear to fully anticipate the independent claims. The key inventive concept of the '935 patent is the combination of a distributed buffer architecture with a specific self-calibration timing method. This method involves each buffer independently determining a timing interval from a first memory operation (e.g., write) and using that information to apply a calculated delay to a subsequent, different memory operation (e.g., read) to ensure proper data alignment with the system's memory controller. The cited prior art either describes a centralized architecture (Rambus '143), lacks the specific "learn and apply" timing method (Netlist '537), or describes a controller-driven calibration process rather than one performed autonomously by distributed buffers (Rambus '269).

Analysis of Obviousness for U.S. Patent No. 9,824,035

An analysis of U.S. Patent No. 9,824,035 ('035 patent) and the relevant prior art indicates that the independent claims would have been obvious to a Person Having Ordinary Skill in the Art (PHOSITA) at the time of the invention. The primary inventive concept—a memory module with distributed buffer circuits that self-calibrate read timing based on a prior write operation—represents a combination of known elements to solve a predictable problem. A strong case for obviousness can be made by combining the teachings of U.S. Patent Application Publication No. 2008/0126703 (Lee) and U.S. Patent No. 7,613,858 (Jeddeloh '858).

Summary of the Prior Art

• Lee (US 2008/0126703): This reference teaches a memory module architecture designed to improve signal integrity by using a buffer on the module's printed circuit board (PCB). The buffer is situated between the memory controller and the memory devices (DRAMs), effectively isolating the DRAMs from the main data bus. This reduces the electrical load on the memory controller, allowing for higher speeds and/or greater memory density. Lee's architecture is functionally analogous to the distributed "isolation devices" (118) described in the '035 patent, which serve the same load-reduction purpose. Lee provides the foundational hardware architecture of a buffered memory module.

• Jeddeloh '858 (US 7,613,858): This patent addresses the critical problem of timing skew on memory buses, which arises from unequal signal path lengths to different memory devices. Jeddeloh '858 discloses methods for "write leveling" and "read leveling" performed by the memory controller.

  • Write Leveling: The controller adjusts the timing of the data strobe (DQS) signal sent to each memory device to ensure it arrives synchronized with the system clock at the device's input.
  • Read Leveling: The controller initiates a read of a known data pattern from a memory device and then adjusts its own internal timing logic to correctly capture the incoming data and strobe.
    Jeddeloh '858 thus teaches the principle of measuring signal timing relationships and applying corrective delays to compensate for physical skews on the memory bus.

Obviousness of Independent Claim 1 (Apparatus Claim)

Claim 1 describes a memory module comprising memory devices, a module control device, and a plurality of distributed buffer circuits. The key limitation is that each buffer circuit includes logic to "obtain timing information based on signals received...during a second memory operation [e.g., a write]" and uses that information to "control timing of the data and strobe signals...in accordance with the timing information" during a "first memory operation [e.g., a read]."

A PHOSITA, starting with the buffered memory module architecture taught by Lee, would have recognized that while the buffers improve signal integrity by reducing electrical load, they do not solve—and may even highlight—the problem of timing skew. Signals originating from the system's memory controller (e.g., DQS) and signals from the on-module controller (e.g., command/control signals) would arrive at each physically distinct buffer at different times. This skew would make it difficult to precisely align the read data sent back from all buffers to the memory controller.

This is a well-known problem in the field. To solve it, a PHOSITA would have been motivated to look for existing solutions for timing calibration. Jeddeloh '858 provides such a solution by teaching write and read leveling. The motivation to combine the teachings would be to make the buffered module of Lee function reliably at high speeds.

It would have been obvious to a PHOSITA to implement the timing calibration function of Jeddeloh '858 within Lee's on-module buffers. Moving this intelligence from the main system controller (as in Jeddeloh) to the distributed buffers is a predictable design choice for several reasons:

1. Improved Granularity and Accuracy: Each buffer can perform a localized timing calibration for its specific data lines and memory devices, compensating for its unique signal flight time.
2. Reduced System Complexity: It offloads the complex task of per-buffer timing management from the main memory controller.
3. Solving a Known Problem: Applying a known timing solution (leveling) to a known architecture (buffered modules) to overcome a predictable problem (skew) is a classic example of obviousness as described in KSR Int'l Co. v. Teleflex Inc.

The specific implementation in the '035 patent—using a write operation to calibrate read timing—is a logical extension. The write strobe (DQS) arriving from the system controller provides a perfect timing reference for the path to each buffer. Using this known timing to adjust the launch time of the subsequent read data is a direct and obvious way to apply Jeddeloh's leveling principle within Lee's buffered architecture.

Obviousness of Independent Claim 15 (Method Claim)

Claim 15 recites a method of operating the memory module, which includes the steps of:

1. Receiving module control signals and a system data strobe (DQS) at a buffer during a write operation.
2. Determining the time interval between the arrival of these two signals.
3. Generating a delay value from this interval.
4. Using this delay value to adjust the timing of read data before transmitting it to the memory controller.

This method is the functional embodiment of the apparatus in Claim 1. The same rationale for combining Lee and Jeddeloh '858 applies.

• Lee provides the system in which the method operates (a module with buffers).
• Jeddeloh '858 teaches the core concept of the method: determining timing relationships during one operation (write or read training) and applying a corrective delay to subsequent operations.

A PHOSITA would be motivated to adapt Jeddeloh's '858 method to the Lee architecture. In the '035 patent's method, the buffer determines a time interval between receiving an enable signal from the on-module controller and receiving the write strobe from the system controller ('035 Patent, Col. 11, ll. 1-13; FIGS. 12A & 13). This interval (EWD) effectively measures the round-trip timing and skew for that specific buffer. Using this measurement to generate a delay value (DS) that is then applied to outgoing read data ('035 Patent, Col. 12, ll. 14-25; FIGS. 15 & 16) is a direct application of Jeddeloh's '858 principle of "leveling" to ensure the read data is correctly aligned when it reaches the system controller. It is a predictable implementation that a skilled artisan would devise to solve the timing skew inherent in the distributed buffer architecture of Lee.

Conclusion

The invention claimed in U.S. Patent No. 9,824,035 represents an obvious combination of prior art elements. The structural architecture of a buffered memory module was known from references like Lee. The functional concept of measuring timing relationships and applying corrective delays to compensate for signal skew was well-established by references like Jeddeloh '858. A person of ordinary skill in the art, seeking to improve the performance and reliability of high-density buffered memory modules, would have been motivated to implement the known timing calibration techniques within the known buffer architecture. This combination of established principles to achieve a predictable result renders the independent claims of the '035 patent obvious under 35 U.S.C. § 103.

Patent Term and Family Analysis

Date of Analysis: May 13, 2026
Patent: U.S. Patent No. 9,824,035

This analysis details the prosecution history, patent term adjustments, and related applications for U.S. Patent No. 9,824,035 ("the '035 patent").

Priority and Continuity Data

The '035 patent is part of a large and complex family of applications. Based on the data in its file history, the patent's term is determined by the earliest non-provisional application to which it claims priority.

• Application Filing Date: The application for the '035 patent, Ser. No. 15/426,064, was filed on February 7, 2017.
• Priority Claim: The patent is a continuation of application Ser. No. 14/846,993 (now U.S. Pat. No. 9,563,587), which is itself a continuation of application Ser. No. 13/952,599 (now U.S. Pat. No. 9,128,632), filed on July 27, 2013. The '599 application claims priority to a provisional application (Ser. No. 61/676,883) filed on July 27, 2012.
• Controlling Priority Date for Term Calculation: The "CROSS REFERENCE TO RELATED APPLICATIONS" section of the '035 patent also references U.S. patent application Ser. No. 12/504,131, filed on July 16, 2009 (now U.S. Pat. No. 8,417,870). This earlier filing date is the controlling date for calculating the 20-year patent term.

Patent Term Adjustment (PTA) / Extension (PTE)

• Patent Term Adjustment (PTA): A review of the USPTO's public records for application Ser. No. 15/426,064 indicates a total Patent Term Adjustment of 12 days was granted by the USPTO due to prosecution delays.
• Patent Term Extension (PTE): There is no record of any Patent Term Extension (PTE) granted under 35 U.S.C. § 156 for regulatory review.

Projected Expiration Date

The expiration date is calculated by adding the 20-year term to the earliest non-provisional priority date, plus any granted Patent Term Adjustment.

• Earliest Priority Date: July 16, 2009
• Base Expiration (20 years): July 16, 2029
• Patent Term Adjustment (PTA): + 12 days
• Projected Expiration Date: July 28, 2029

Note: The "Anticipated expiration" date of July 27, 2033, listed in some public databases, appears to be calculated from the filing date of the later parent application (Ser. No. 13/952,599) and does not account for the controlling, earlier priority claim to the application filed in 2009. The correct expiration date, based on the full priority chain and PTA, is July 28, 2029. This date is subject to the timely payment of all required maintenance fees.

Related U.S. Applications

This patent is part of a large family tree. The following are continuations, with the '035 patent serving as a parent application:

• U.S. Patent No. 10,268,608: Filed November 21, 2017, from application Ser. No. 15/820,076.
• U.S. Patent No. 10,860,506: Filed April 22, 2019, from application Ser. No. 16/391,151.
• U.S. Patent No. 11,762,788: Filed December 7, 2020, from application Ser. No. 17/114,478.
• U.S. Patent Application Pub. No. 2025/0028660 A1: Filed August 20, 2023, from application Ser. No. 18/452,554.

The '035 patent does not have any divisional applications, but it is part of a chain of continuation applications.

Foreign Family Members

A search for international counterparts to the '035 patent did not yield any direct foreign family members filed under the Paris Convention or as a national stage entry of a PCT application that claims priority to this specific U.S. family. The patent family appears to be exclusively filed within the United States.

Defensive Disclosure: US 9,824,035

Publication Date: May 13, 2026
Reference Patent: U.S. Patent No. 9,824,035 B2
Title: Memory module with timing-controlled data paths in distributed data buffers
Summary: This document discloses several derivative inventions and improvements upon the core concepts described in U.S. Patent No. 9,824,035. The purpose of this disclosure is to place these concepts into the public domain, thereby establishing them as prior art for any future patent applications. The core invention involves a memory module with distributed buffer circuits, where each buffer independently captures timing information from a write operation to calibrate the timing of a subsequent read operation.

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Derivative Embodiment Set 1: Based on Independent Claim 1 (Apparatus)

1.1. Material & Component Substitution

1.1.1. Cryogenic High-Frequency Substrate and Gallium Nitride (GaN) Buffer Circuits

• Enabling Description: This embodiment describes a memory module designed for operation in cryogenic environments (-180°C to -270°C), such as those used in quantum computing control planes or high-frequency trading servers. The module's printed circuit board (119) is constructed from a low-loss ceramic substrate, such as Alumina (Al₂O₃) or Aluminum Nitride (AlN), which exhibit superior dimensional stability and dielectric performance at low temperatures compared to standard FR-4. The buffer circuits (118) are fabricated using a Gallium Nitride (GaN) High-Electron-Mobility Transistor (HEMT) process instead of conventional CMOS. GaN's higher electron mobility and lower on-resistance result in significantly faster switching speeds and reduced propagation delays, enabling the timing control logic within the buffer to operate with picosecond-level precision. The delay control circuit (650) utilizes a GaN-based tapped delay line, where each tap provides a delay increment below 5ps, a resolution unachievable with standard CMOS at these temperatures. The memory devices (112) are specifically qualified low-temperature DRAMs. This configuration allows the on-the-fly timing calibration to compensate for thermal-gradient-induced signal skew across the module as it cools.

• Diagram:

  graph TD
      subgraph Memory Module (Cryogenic)
          A[Memory Controller Interface] --> B{Module Control Device};
          B --> C1[GaN Buffer 1];
          B --> C2[GaN Buffer 2];
          B --> C3[GaN Buffer N];
          C1 --> D1[Memory Devices - Group 1];
          C2 --> D2[Memory Devices - Group 2];
          C3 --> D3[Memory Devices - Group N];
      end
      subgraph Substrate
          S[Ceramic Substrate (AlN)]
      end
      subgraph Components
          GaN[GaN HEMT Buffer Circuit];
          DRAM[Low-Temperature DRAM];
      end
      style S fill:#dae8fc,stroke:#333,stroke-width:2px
      style GaN fill:#d5f5e3,stroke:#333,stroke-width:2px
  

1.1.2. Reconfigurable Timing Logic via Embedded FPGA Buffers

• Enabling Description: In this variant, the dedicated ASIC buffer circuits (118) are replaced with small, low-power Field-Programmable Gate Arrays (FPGAs). Each FPGA is co-packaged with a group of memory devices. The "logic" described in the patent is implemented as soft IP cores within the FPGA. This includes a Time-to-Digital Converter (TDC) core to measure the EWD (Enable-to-Write Data delay) and a digitally-controlled delay line (DCDL) core to apply the DS (Delay Signal) to the read path. This approach allows the timing calibration algorithm itself to be updated in the field via a firmware update delivered over the system's SMBus. For example, the algorithm could be switched from a simple last-write measurement to a moving-average or a Kalman filter-based estimation of the timing drift, adapting to different system workloads or aging effects without requiring a hardware revision.

• Diagram:

  sequenceDiagram
      participant MCH as Memory Controller
      participant MCD as Module Control Device
      participant FPGA_Buffer as FPGA Buffer
      participant DRAM as Memory Devices
  
      MCH->>MCD: Write Command
      MCD->>FPGA_Buffer: Module Control Signal (MCS)
      FPGA_Buffer->>FPGA_Buffer: Start TDC Counter
      MCH->>FPGA_Buffer: Write DQS
      FPGA_Buffer->>FPGA_Buffer: Stop TDC Counter; Calculate Delay
      FPGA_Buffer->>DRAM: Write Data
      Note over FPGA_Buffer: Stores calculated delay value
      MCH->>MCD: Read Command
      MCD->>FPGA_Buffer: Module Control Signal (MCS)
      DRAM-->>FPGA_Buffer: Read Data
      FPGA_Buffer->>FPGA_Buffer: Apply Stored Delay
      FPGA_Buffer-->>MCH: Delayed Read Data
  

1.2. Operational Parameter Expansion

1.2.1. High-Radiation Environment with Redundant Timing Logic

• Enabling Description: A memory module for aerospace or nuclear applications is constructed using radiation-hardened components. The buffer circuit (118) is designed with Triple Modular Redundancy (TMR) for its critical logic, including the counter circuit (1330) and the registers storing the final delay value DS. The device contains three identical logic paths for timing measurement. A voter circuit compares the outputs of the three paths. If a Single Event Upset (SEU) caused by a high-energy particle corrupts one of the counters, the voter circuit discards the erroneous value and uses the result from the other two, ensuring the applied read delay remains correct. The buffer circuit also monitors the system's EDAC (Error Detection and Correction) flags. A high rate of correctable memory errors can trigger an automatic recalibration cycle, assuming the errors may be timing-related due to radiation-induced drift.

• Diagram:

  graph TD
      subgraph Rad-Hard Buffer
          Input[MCS, DQS] --> Logic1(Timing Logic A);
          Input --> Logic2(Timing Logic B);
          Input --> Logic3(Timing Logic C);
          Logic1 --> Voter;
          Logic2 --> Voter;
          Logic3 --> Voter;
          Voter -- Majority Vote --> Register(Store Correct Delay 'DS');
          Register --> DelayLine(Apply Delay to Read Path);
          ReadPath_In[Read Data In] --> DelayLine;
          DelayLine --> ReadPath_Out[Read Data Out];
      end
  

1.3. Cross-Domain Application

1.3.1. Automotive LiDAR Sensor Synchronization

• Enabling Description: This concept is applied to an automotive LiDAR (Light Detection and Ranging) system. The "memory module" is a sensor array board, and the "memory devices" are individual laser/detector pairs. A central processing unit (the "memory controller") sends a global "fire laser" command (analogous to a write command) to all sensor modules via a module control device. Due to varying cable lengths and thermal conditions across the vehicle chassis, this command arrives at different times. Each sensor module contains a buffer circuit (118). This buffer measures the time delta between the arrival of the "fire laser" command and a synchronized master clock signal (analogous to DQS) distributed to all modules. It stores this delta as a timing offset. When a photon is detected by the sensor (analogous to a read operation), the buffer applies the stored offset to the timestamp of the detection event before forwarding it to the central processor. This calibration ensures that the time-of-flight calculations for all points in the LiDAR cloud share a common, highly accurate time reference, dramatically improving the accuracy of the 3D environmental map.

• Diagram:

  flowchart LR
      subgraph LiDAR System
          A[Central ECU] -- Fire Command --> B(Control Hub);
          A -- Master Clock --> B;
          B -- Fire Pulse 1 --> C1(Sensor Buffer 1);
          B -- Master Clock --> C1;
          B -- Fire Pulse 2 --> C2(Sensor Buffer 2);
          B -- Master Clock --> C2;
          C1 -- Calibrated Fire --> D1[Laser/Detector 1];
          C2 -- Calibrated Fire --> D2[Laser/Detector 2];
          D1 -- Photon Detect --> C1;
          D2 -- Photon Detect --> C2;
          C1 -- Time-Corrected Data --> A;
          C2 -- Time-Corrected Data --> A;
      end
      C1 -- Measures Δt1 --> C1;
      C2 -- Measures Δt2 --> C2;
  

1.4. Integration with Emerging Tech

1.4.1. AI-Based Predictive Thermal Drift Compensation

• Enabling Description: The buffer circuit (118) is enhanced with an integrated temperature sensor and a lightweight machine learning inference engine (e.g., a Bonsai-style decision tree or a quantized neural network). During system operation, the buffer continuously measures the EWD interval as described in the patent and correlates it with the on-chip temperature reading. This data builds a model of how timing skews as a function of temperature and workload intensity (inferred from the frequency of commands). The ML engine then proactively adjusts the read data path delay (DS) based on the predicted skew for the current temperature, rather than simply using the last measured skew. For example, if the temperature rapidly increases, the model predicts the impending timing drift and applies a counter-acting delay before any timing errors can occur, improving system reliability under dynamic thermal loads.

• Diagram:

  stateDiagram-v2
      state "Monitoring & Learning" as ML
      state "Predictive Adjustment" as PA
      [*] --> Idle
      Idle --> ML : Write Operation
      ML --> ML : Measure(EWD, Temp)
      ML --> ML : Update Model(EWD, Temp)
      ML --> Idle : Write Complete
      Idle --> PA : Read Operation
      PA --> PA : Read Current Temp
      PA --> PA : Predict Skew(Temp)
      PA --> PA : Calculate DS_predictive
      PA --> Idle : Apply DS_predictive & Send Data
  

1.5. The "Inverse" or Failure Mode

1.5.1. Failsafe Operation with Graceful Performance Degradation

• Enabling Description: The buffer circuit's delay control logic (650) is augmented with a "sanity checker" and a failsafe path. The sanity checker is a simple digital comparator that continuously monitors the calculated delay value DS. If DS falls outside a pre-determined valid window (e.g., +/- 1 clock cycle of a nominal value), which is programmed into an eFuse during manufacturing, it indicates a fault in the measurement logic. Upon detecting an invalid DS value, the checker triggers a multiplexer to switch the read data path away from the variable delay line (1660) and through a fixed, conservative delay path. Simultaneously, it asserts an alert signal on a sideband pin (e.g., connecting to the system's SMBus) to notify the host BIOS or OS of the fault condition. This prevents a timing miscalculation from causing a catastrophic system crash, allowing the system to continue operating in a "limp mode" with safe, albeit non-optimal, memory timing until the module can be serviced.

• Diagram:

  graph TD
      subgraph Failsafe Buffer
          A[Read Data In] --> MUX;
          subgraph Dynamic Path
              A1[Variable Delay Line] --> B1[Output];
          end
          subgraph Failsafe Path
              A2[Fixed Delay Line] --> B2[Output];
          end
          A1 -- "Controlled by DS" --> MUX;
          A2 --> MUX;
          
          C[Delay Control Logic] -- "Calculates DS" --> DS_Val(DS);
          DS_Val --> D{Sanity Check};
          D -- "DS is Valid" --> Ctrl(Control MUX to select Dynamic Path);
          D -- "DS is Invalid" --> Failsafe(Control MUX to select Failsafe Path);
          Failsafe --> Alert[Assert ALERT_N pin];
          
          MUX --> E[Read Data Out];
      end
  

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Derivative Embodiment Set 2: Based on Independent Claim 15 (Method)

2.1. Material & Component Substitution

2.1.1. Method using Analog Phase Interpolation for Delay Generation

• Enabling Description: This method refines step 1830 ("generating a delay signal DS"). Instead of a digital counter producing a discrete delay value, the buffer circuit employs an analog delay-locked loop (DLL) or phase interpolator. The time interval EWD between the module control signal and the write DQS is measured and converted to a control voltage via a time-to-voltage converter. This analog voltage is then used to control the phase interpolator in the read path. The interpolator mixes two quadrature-phase clock signals to produce an output clock (RDQS) with a continuously variable phase offset that precisely matches the required delay. This analog approach provides much finer delay resolution (sub-picosecond) than a digital tapped delay line, enabling more accurate timing alignment for extremely high data rates (e.g., >25 GT/s) where digital step sizes would be too coarse.

• Diagram:

  flowchart TD
      A[Receive Write MCS] --> T1(Start Time-to-Voltage Ramp);
      B[Receive Write DQS] --> T2(Stop Ramp & Hold Voltage);
      T2 -- Control Voltage V_ctrl --> C{Analog Phase Interpolator};
      D[Receive Read Data from DRAM] --> E[Latch with System Clock];
      E --> C;
      C -- Applies V_ctrl-based phase shift --> F[Output Read Data to Host];
  

2.2. Cross-Domain Application

2.2.1. Method for Distributed Ledger Timestamp Synchronization

• Enabling Description: This method applies the '035 patent's timing calibration to a distributed network of blockchain nodes. Each node acts as a "buffer circuit." A "write command" is a consensus-critical message (e.g., a block proposal) broadcast from a leader node (the "module control device"). Each receiving node executes the method. It receives the proposal (analogous to the module control signal) and also receives a periodic, high-precision timing beacon from a network time protocol (NTP) or GPS source (analogous to the DQS signal). The node measures the time interval between the receipt of the proposal and the next timing beacon. This interval represents the network latency for that specific message. When this node creates its own transactions for the next block (a "read operation"), it adjusts their timestamps by this measured latency value. This process ensures that timestamps across all nodes are corrected for network propagation delay, leading to a more fair and accurate transaction ordering within the distributed ledger.

• Diagram:

  sequenceDiagram
      participant Leader
      participant Node_A
      participant Node_B
      participant TimeSource as GPS/NTP
  
      loop Every Second
          TimeSource->>Node_A: Time Beacon
          TimeSource->>Node_B: Time Beacon
      end
  
      Leader->>Node_A: Block Proposal (t1)
      Note over Node_A: Measures Δt between Proposal and next Beacon
      Leader->>Node_B: Block Proposal (t2)
      Note over Node_B: Measures Δt between Proposal and next Beacon
  
      Node_A->>Node_A: Create Transaction
      Node_A->>Node_A: Adjust Timestamp using Δt
      Node_B->>Node_B: Create Transaction
      Node_B->>Node_B: Adjust Timestamp using Δt
  

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Combination Prior Art Scenarios

1. Integration with Compute Express Link (CXL) Protocol

• Description: The memory module apparatus of claim 1 is implemented as a CXL Type 3 memory device. The module control device (116) acts as a CXL endpoint, receiving and decoding CXL.mem protocol FLITs (Flow Control Units) from the host CPU. The "module control signals" sent to the buffer circuits (118) are derived from the commands within these FLITs (e.g., MemWr, MemRd). The "data strobe signal" is the CXL link's differential clock. The buffer circuits (118) perform the claimed method of measuring the time between the decoded CXL command arriving from the on-module CXL endpoint and the physical CXL clock edge. This locally-derived delay value (DS) is then used to fine-tune the timing of read data being returned to the CXL endpoint for packaging into CXL.mem Data FLITs. This method supplements the standard CXL PHY-level link training by providing continuous, per-buffer-chip timing calibration to compensate for on-module thermal and voltage variations not visible to the host controller.

2. Integration with RISC-V and the I²C Open Standard

• Description: The module control device (116) incorporates an open-source, 32-bit RISC-V microcontroller core (e.g., a VexRiscv core). The firmware running on this core is responsible for receiving commands from the host memory controller and generating the internal module control signals. Each buffer circuit (118) implements the timing measurement method of claim 15. The resulting delay value (DS) is stored in a register accessible via an I²C (Inter-Integrated Circuit) slave interface, an open standard. The RISC-V core on the module controller acts as the I²C master, polling each buffer circuit periodically to read its currently calibrated delay value. This allows the central on-module intelligence (the RISC-V core) to build a complete timing map of the module, log it, and potentially perform more advanced system-wide optimizations, such as throttling memory access to a specific group of DRAMs if its corresponding buffer reports a dangerously high timing drift.

3. Integration with the AMBA AXI4-Stream Open Standard

• Description: The on-module communication between the module control device (116) and the distributed buffer circuits (118) is implemented using the open AMBA AXI4-Stream protocol. The module control signals are encapsulated as packets and transmitted over a lightweight, point-to-multipoint AXI4-Stream bus (TVALID, TDATA, TLAST). Each buffer circuit (118) has an AXI4-Stream slave interface. When a buffer circuit performs the timing measurement of claim 15, it captures the arrival time of the TLAST signal for the write command packet. It then measures the interval until the arrival of the write DQS from the host. During a read operation, when the buffer sends read data back towards the module control device, it does so over another AXI4-Stream bus, using the TUSER sideband signal to embed the calculated delay value (DS) alongside the read data. This allows the module control device to be aware of the exact timing compensation being applied by each individual buffer.