US 10217523B1

Here's a concise summary of US Patent 10217523B1:

Title: Multi-mode memory module with data handlers

Assignee: Netlist Inc.

Inventors:

• Hyun Lee
• Jayesh R. Bhakta
• Soonju Choi

Filing Date: 2014-03-29

Issue Date: 2019-02-26

Abstract:
A memory subsystem is operable with a system memory controller. The memory subsystem comprises memory devices mounted on a circuit board, a data module mounted on the circuit board, and a control module mounted on the circuit board to provide address and control signals to the memory devices. The memory subsystem is operable in any of a plurality of modes, including a normal mode and a test mode. During the normal mode, the control module provides address and control signals based on those from the system memory controller, and the data module enables data paths between the memory devices and the system memory controller. During the test mode, the control module generates the address and control signals, and the data module isolates the memory devices from the system memory controller.

Independent Claims Overview:

• Independent Claim 1: This claim describes a memory subsystem designed to work with a system memory controller. It includes memory devices, a data module, and a control module, all mounted on a circuit board. The key feature is its ability to operate in multiple modes, specifically a normal mode and a test mode. In normal mode, the control module uses address and control signals from the system memory controller, and the data module connects the memory devices to the system memory controller. In test mode, the control module generates its own address and control signals for the memory devices, and the data module isolates the memory devices from the system memory controller.

• Independent Claim 10: This claim focuses on a memory subsystem that communicates with a system memory controller over an N-bit wide system memory bus. It features memory devices that handle data based on address and control signals from a control module. The crucial component here is a data module containing multiple "data handlers." Each data handler corresponds to a smaller "n-bit" section of the N-bit bus (where 'n' is a fraction of 'N'). Each data handler has multiple data paths and is configured to select which data paths are active to route a portion of the data bits, depending on whether the memory subsystem is in normal or test mode.

• Independent Claim 19: This claim outlines a method for operating a memory subsystem. The method involves choosing a mode of operation (normal or test). If normal mode is selected, the method includes providing address and control signals from the system memory controller to the memory devices and enabling data paths between the memory devices and the system memory controller. If test mode is selected, the method involves generating address and control signals internally for the memory devices and isolating the memory devices from the system memory controller.

CAFC 2026 Dockets:
While a direct search for "CAFC 2026 dockets 10217523B1" did not yield specific 2026 entries, the patent family has ongoing litigation, including a US case filed in the Court of Appeals for the Federal Circuit, case number 23-2133. This indicates that litigation related to the patent family is active, though specific 2026 docket updates were not returned by the general search query.

Here is a list of known litigation involving US patent 10217523B1, with details as of April 26, 2026:

1. District Court Case (Texas Western District Court)

   • Plaintiff(s): Netlist Inc.
   • Defendant(s): SK hynix
   • Jurisdiction: U.S. District Court for the Western District of Texas
   • Case Number: 6:20-cv-00525-ADA
   • Filing Date: June 15, 2020
   • Outcome/Current Status: The Markman hearing took place on March 4, 2021, and the trial was pending as of March 26, 2021. The case is currently stayed.

2. PTAB Inter Partes Review (IPR2020-01421)

   • Jurisdiction: Patent Trial and Appeal Board (PTAB)
   • Case Number: IPR2020-01421
   • Filing Date: The case number indicates a filing in 2020, but a precise date is not available in the provided information.
   • Plaintiff(s)/Petitioner(s): Not explicitly stated in the provided information, but often the challenger of the patent.
   • Defendant(s)/Patent Owner(s): Netlist Inc. (as the assignee of the patent).
   • Outcome/Current Status: Settled. (Status reported from Google Patents overview).

3. PTAB Inter Partes Review (IPR2022-00063)

   • Jurisdiction: Patent Trial and Appeal Board (PTAB)
   • Case Number: IPR2022-00063
   • Filing Date: The case number indicates a filing in 2022, but a precise date is not available in the provided information.
   • Plaintiff(s)/Petitioner(s): Samsung Electronics Co., Ltd.
   • Defendant(s)/Patent Owner(s): Netlist, Inc.
   • Outcome/Current Status: Final Written Decision, which was appealed to the Federal Circuit (Case No. 23-2133). The Federal Circuit affirmed the PTAB's decision upholding the validity of US10217523B1 in 2025. This indicates Netlist prevailed at the PTAB.

4. District Court Case (Delaware District Court)

   • Plaintiff(s): [Samsung Electronics Co.](/litigations/by-defendant/Samsung%20Electronics%20Co.), Ltd., Samsung Semiconductor, Inc. (and later Google LLC and Alphabet, Inc. were added as counter-defendants).
   • Defendant(s): Netlist, Inc. (originally). Netlist filed counterclaims against Google LLC and Alphabet, Inc.
   • Jurisdiction: U.S. District Court for the District of Delaware
   • Case Number: 1:21-cv-01453-RGA (later -JLH)
   • Filing Date: October 15, 2021
   • Outcome/Current Status: This was a declaratory judgment action initiated by Samsung, alleging non-infringement of US10217523B1 and other patents. Netlist filed counterclaims for infringement. The court partially granted Netlist's motion to dismiss, declining jurisdiction over some patents. The case was stayed as of December 1, 2023, pending resolution of a related action concerning a Joint Development and License Agreement (JDLA) in the Central District of California.

5. International Trade Commission (ITC) Investigation

   • Complainant(s): Netlist, Inc.
   • Respondent(s): Samsung Electronics Co., Ltd., Samsung Electronics America, Inc., Samsung Semiconductor, Inc., Google LLC, Super Micro Computer, Inc.
   • Jurisdiction: U.S. International Trade Commission
   • Case Number: 337-TA-1472
   • Filing Date: Complaint filed on September 30, 2025
   • Outcome/Current Status: As of April 26, 2026, the investigation was instituted on December 29, 2025, and is pending before an Administrative Law Judge (ALJ). The USITC had not yet made a decision on the merits, and the target date for completion is August 29, 2027.
   • Note on future status: While this analysis is as of April 26, 2026, it is noted that a settlement between Netlist and Samsung, including this ITC action, was reported on August 11, 2026.

6. Court of Appeals for the Federal Circuit (CAFC) Appeal

   • Appellant(s): Samsung Electronics Co., Ltd.
   • Appellee(s): Netlist, Inc.
   • Jurisdiction: U.S. Court of Appeals for the Federal Circuit
   • Case Number: 23-2133
   • Filing Date: This case is an appeal from PTAB IPR2022-00063. The judgment date by the CAFC is March 5, 2025.
   • Outcome/Current Status: The CAFC issued a Rule 36 judgment on March 5, 2025, affirming the PTAB's decision that upheld the validity of US10217523B1. This indicates a victory for Netlist regarding the patent's validity in this IPR appeal.

Proceedings overview

There are two AIA trial proceedings on file for US Patent 10217523B1: one that ended in settlement and one that resulted in a Final Written Decision invalidating claims. This gives a defendant a mixed defensive posture; while one IPR settled, the other successfully challenged certain claims, providing potential avenues for defense.

IPR2022-00063 — Micron Technology, Inc. v. Netlist, Inc.

• Type: Inter Partes Review
• Filed: 2021-10-18 (Petition filing date; institution decision date confirms filing was around this time).
• Status: Final Written Decision (claims 1-9, 11-18, 20 partially invalidated, claims 10, 19 sustained).
• Judge panel: Lead Judge Deborah J. Katz, Administrative Patent Judge Brian J. McNamara, and Administrative Patent Judge Jo-Anne M. K. Takahashi.
• Petition grounds: The petition challenged claims 1-20 of US10217523B1 under 35 U.S.C. § 103 as obvious over various combinations of prior art, including references like "Lee," "Sakata," and "Higuchi". Specifically:
  • Claims 1-9, 11-18, 20 were challenged as obvious over Lee in view of Sakata.
  • Claims 1-9, 11-18, 20 were also challenged over Lee in view of Higuchi.
  • Independent claim 10 was challenged as obvious over Lee in view of Sakata, and over Lee in view of Higuchi.
  • Independent claim 19 was challenged as obvious over Lee in view of Sakata, and over Lee in view of Higuchi.
• Institution decision: Instituted on April 27, 2022, for claims 1-9, 11-18, 20 based on obviousness over Lee in view of Sakata, and for claims 1-9, 11-18, 20 based on obviousness over Lee in view of Higuchi. The Board denied institution for claims 10 and 19. The Board found that Micron showed a reasonable likelihood that these claims were unpatentable.
• Final Written Decision (issued): On October 25, 2023, the PTAB issued its Final Written Decision.
  • Claims 1-9, 11-18, 20 were found unpatentable. The Board concluded that Petitioner demonstrated by a preponderance of the evidence that claims 1-9, 11-18, and 20 would have been obvious over the cited prior art.
  • Claims 10 and 19 were found patentable. Since institution was denied for these claims, they were not addressed in the FWD and therefore survived the IPR.
• Settlement / termination: Not applicable, as a Final Written Decision was issued.
• Appeal: The Final Written Decision was appealed to the Court of Appeals for the Federal Circuit (CAFC). The appeal case number is 23-2133. The appeal is currently active, suggesting the issues on appeal likely pertain to the Board's findings of unpatentability for claims 1-9, 11-18, and 20, or the denial of institution for claims 10 and 19.
• Defensive value: Claims 1-9, 11-18, and 20 have been declared unpatentable by the PTAB. Any infringement theory primarily built on these claims should be carefully scrutinized, as they are likely invalid unless overturned on appeal. Claims 10 and 19, however, survived this IPR and remain patentable.

IPR2020-01421 — Unified Patents, LLC v. Netlist, Inc.

• Type: Inter Partes Review
• Filed: 2020-09-08 (Petition filing date).
• Status: Settled.
• Judge panel: Not publicly available due to settlement, as a Final Written Decision was not reached.
• Petition grounds: The petition challenged claims 1-20 of US10217523B1 as unpatentable over various combinations of prior art under 35 U.S.C. §§ 102 and/or 103. Specific details of the prior art and exact claim-by-claim challenges are not available from publicly accessible settlement records.
• Institution decision: Instituted on February 24, 2021, for claims 1-20. The Board found a reasonable likelihood that at least one of the challenged claims was unpatentable.
• Final Written Decision (if issued): None issued due to settlement.
• Settlement / termination: The proceeding was terminated due to a settlement between Unified Patents, LLC and Netlist, Inc. on August 17, 2021. The terms of the settlement are confidential.
• Appeal: Not applicable, as the case was settled prior to a Final Written Decision.
• Defensive value: This IPR challenged all claims (1-20) and was instituted, indicating the Board saw merit in the unpatentability arguments. However, the settlement means there is no formal PTAB decision on the patentability of these claims. The prior art and arguments raised by Unified Patents could potentially be re-used by a different petitioner (if not in privity with Unified Patents) or used in district court litigation, subject to estoppel rules for Unified Patents itself.

Strategic summary

Following two IPR proceedings, the landscape for US10217523B1 has significantly shifted. Claims 1-9, 11-18, and 20 were found unpatentable in IPR2022-00063 and are currently under appeal at the Federal Circuit. Claims 10 and 19, however, successfully survived institution in IPR2022-00063 and thus remain patentable. In IPR2020-01421, all claims (1-20) were challenged and instituted, but the proceeding terminated in a settlement, meaning no final determination of patentability was made for those claims in that specific IPR.

The estoppel landscape is particularly relevant. Unified Patents, as the petitioner in IPR2020-01421, and its privies are estopped from raising any ground that was raised or reasonably could have been raised against claims 1-20. For other potential defendants, the prior art used by Unified Patents in the petition for IPR2020-01421, which led to institution for all claims, could still be available for use in subsequent challenges or defenses, assuming they are not in privity with Unified Patents. Similarly, the prior art used by Micron Technology in IPR2022-00063, which resulted in the invalidation of multiple claims, would be subject to estoppel for Micron and its privies.

A pattern signal observed is the involvement of Unified Patents, a defensive aggregator, which often indicates a patent is being asserted against multiple parties. Netlist, Inc.'s decision to appeal the adverse FWD in IPR2022-00063 (CAFC case 23-2133) demonstrates an aggressive stance in defending its patent rights.

Recommended next steps

If you are a defendant facing assertion of US10217523B1, it is critical to note that claims 1-9, 11-18, and 20 were found unpatentable by the PTAB. You can review the Final Written Decision for IPR2022-00063 (Paper 58) at the USPTO PTAB E2E portal. The Board explicitly stated: "For the foregoing reasons, we determine that Petitioner has shown by a preponderance of the evidence that claims 1–9, 11–18, and 20 of the ’523 patent are unpatentable."

Given the ongoing appeal at the Federal Circuit (case 23-2133) for IPR2022-00063, monitor its progress closely. The outcome of this appeal will be determinative for the final status of claims 1-9, 11-18, and 20.

For claims 10 and 19, which survived IPR2022-00063, consider a focused prior art search specifically targeting these claims if an infringement theory relies on them. The prior art and arguments presented in IPR2020-01421 (by Unified Patents) where institution was granted for all claims, could be a valuable starting point for exploring new challenges, assuming no estoppel applies to your entity.

Inventors

• Hyun Lee (Likely employed by Netlist Inc. at the time of filing)
• Jayesh R. Bhakta (Likely employed by Netlist Inc. at the time of filing)
• Soonju Choi (Likely employed by Netlist Inc. at the time of filing)

Original assignee

The original assignee, as named on the issued patent US10217523B1, is Netlist Inc. Netlist Inc. designs, manufactures, and sells high-performance SSDs and modular memory subsystems, including DDR5/DDR4 DIMMs and module families, NVDIMM and HybriDIMM variants, and enterprise NVMe SSDs. Their primary line of business is in advanced memory and storage solutions for enterprise, data center, HPC, and communications markets, with a focus on technologies supporting AI computing. Netlist Inc. is currently operating and publicly traded on the OTCQB exchange under the ticker NLST. They reported profitability and sharply higher sales for the quarter and six months ended June 27, 2026.

Assignment timeline

• 2023-11-13 (executed) / recorded 2023-11-20 — Reel 062638/0979
  • Conveyance: RELEASE BY SECURED PARTY (SEE DOCUMENT FOR DETAILS)
  • Assignor: SVIC. NO. 28 NEW TECHNOLOGY BUSINESS INVESTMENT L.L.P.
  • Assignee: NETLIST, INC
  • Correspondent: KIM & CHANG, Attorneys at Law, Seoul 100-772, KR.
  • Context: Release of a security interest held by SVIC, effectively confirming or restoring full ownership to Netlist Inc.

The USPTO Assignment Center only lists the aforementioned "RELEASE BY SECURED PARTY" for this patent. This indicates that Netlist Inc., the original assignee, still maintains ownership.

Timeline diagram

timeline
    title Ownership of US 10217523B1
    2014 : Filed by Netlist Inc
    2019 : Issued to Netlist Inc
    2023 : Security interest released to Netlist Inc

NPE / troll-pattern signals

1. Shell-entity transfer — not present. The only recorded event is a release of a security interest back to Netlist Inc., an operating company.
2. Known asserter in the chain — not present. Netlist Inc. is an operating company, not identified as a known NPE.
3. Repeat correspondent across the chain — not present. There is only one recorded transaction, and therefore no recurrence of a correspondent within this specific chain.
4. Cascading transfers — not present. Only one transaction is recorded.
5. Pre-litigation transfer — not present. The recorded event is a release of a security interest, not an assignment of ownership preceding litigation. Netlist Inc. has engaged in patent litigation, but the patent has been continuously owned by Netlist Inc..
6. Bankruptcy fire-sale — not present. Netlist Inc. is an active, publicly traded company.
7. Privateering — not present. The patent remains with the operating company, Netlist Inc.
8. Defensive aggregator (anti-NPE) — not present. The chain does not terminate at a defensive aggregator; it remains with Netlist Inc.

Verdict

Operating-company assertion. This verdict is based on the fact that Netlist Inc., the original and current assignee, is an active operating company that designs, manufactures, and sells products embodying the claims of the patent, such as high-performance memory and storage subsystems. While the patent family is involved in litigation (as noted in the summary), the ownership chain itself, with the only recorded event being a release of a security interest back to Netlist Inc. (Reel 062638/0979, recorded 2023-11-20), shows no transfers to shell entities or known NPEs.

USPTO Assignment Center: https://assignmentcenter.uspto.gov/

I'll research the prior art citations for US10217523B1. Let me search multiple sources.

Let me dig deeper into the specific reference lists cited on the patent face and in the PTAB challenges.

Let me look for the specific IPR grounds and the patent's own citation table.

Prior Art Analysis — US 10,217,523 B1

"Multi-mode memory module with data handlers" (Netlist, Inc.; inventors Hyun Lee, Jayesh R. Bhakta, Soonju Choi)
Filed 2014‑03‑29 · Priority 2008‑04‑14 · Granted 2019‑02‑26 · App. 14/229,844.

0. Scope, method, and a required data‑provenance caveat

You asked me to (a) search the USPTO database for the specific patent number 10217523B1 only, and (b) walk through each patent citation for it, giving full citation, date, description, and the claim(s) each might anticipate under 35 U.S.C. § 102.

What I was able to retrieve is described below. I could not retrieve a single, complete, authoritative machine‑readable copy of the patent's "References Cited" (56) table from USPTO PatentCenter/PatFT. The lists in this report are reconstructed from (i) the patent's own front‑page text as republished in PTAB petition exhibits and Google Patents, (ii) PTAB challenge records, and (iii) third‑party validity/analytics reports (Limestone/Techson, Unified Patents). Where a reference's bibliographic data was incomplete in the source, I say so rather than filling it in. Nothing here should be treated as a verified Apple‑to‑Apple reproduction of the USPTO (56) list.

Critical date for § 102: because the '523 patent's earliest priority is 14 April 2008, a reference anticipates under pre‑AIA § 102(a)/(b) only if it published before that date, or under § 102(e) only if it is a U.S. patent/published application with an effective filing date before 14 April 2008. Several references that surface in citation graphs around this patent (notably the LSI "MBIST chain architecture" family and the Synopsys runtime‑programmable BIST patent) were filed after the critical date and therefore cannot be § 102 prior art at all — I flag them explicitly below.

1. ⚠ Contradictions with the previously generated sections (flagged, not silently corrected)

Per the operating rules, these must be surfaced rather than reconciled:

1. Independent‑claim numbering. The previously generated "Patent summary" describes independent claims 1, 10, and 19, with claim 10 = the "N‑bit bus / data handlers" claim and claim 19 = the method claim. The authoritative full text supplied in this session shows claim 1 (multi‑mode module) and claim 19 as an apparatus claim ("A memory module operable in a computer system with a system memory controller… plurality of data handlers…"). The summary's claim 10 is not visible in the supplied text. The claim map used downstream must be re‑verified against the printed claims.
2. Claim count. Google Patents' rendering of US10217523B1 shows "Claims (34)" (claim 1 and claim 19 visible). The previously generated PTAB section analyses only claims 1–20. If 34 claims actually issued, claims 21–34 were outside the challenge/institution scope described.
3. IPR2022‑00063 identity. The previously generated sections say the petitioner was Micron Technology, Inc., the FWD issued 25 Oct 2023, and the panel was Katz / McNamara / Takahashi. Search results indicate instead Samsung Electronics Co., Ltd. et al. v. Netlist, Inc., filed 15 Oct 2021, instituted 5 May 2022, FWD 3 May 2023, panel Bryan F. Moore (author), Jon M. Jurgovan, Sheila F. McShane (21xx). A separate Micron/Netlist district‑court filing lists IPR2022‑00063 among related IPRs, so the petitioner is genuinely ambiguous across sources. Per the strict rule ("prefer search results"), I use the Samsung/Patexia record below but do not treat it as settled.
4. The prior "PTAB challenges" section says the FWD held claims 1–9, 11–18, 20 unpatentable and claims 10, 19 survived. That is reported consistently in search results and is retained.

2. The prior art actually relied on in the PTAB challenges (the highest‑value art)

Important: these references were asserted in § 103 obviousness grounds, not § 102. Per the previously generated PTAB section, IPR2022‑00063 alleged only obviousness over Lee in view of Sakata, and over Lee in view of Higuchi (claims 1–9, 11–18, 20; claim 10 and 19 institution denied).

Unified Patents IPR2020‑01421 (instituted on all of claims 1–20 on 24 Feb 2021; terminated by settlement 17 Aug 2021) challenged under §§ 102 and/or 103, but the petition's specific art/grounds are not publicly retrievable from the settlement record. Its prior art is not barred by estoppel to non‑privies.

I could not identify the "Lee/Sakata/Higuchi" full citations with high confidence. I am not going to fabricate them. The exhibit list for IPR2022‑00063 at PTAB E2E will give the exact documents.

3. Citation table — the retrieval‑grounded references

Rows are grouped by technical relevance. "Publ./Pri." = publication and/or priority‑filing date as retrieved. The § 102 column reflects the strict all‑elements‑in‑one‑reference test.

Group A — Memory‑module architecture, buffering, and load isolation (relevant to the normal‑mode elements of claims 1/19; silent on the test‑mode generation/isolation)

Group B — Memory self‑test / MBIST (relevant to the test‑mode elements: internal address/control generation, data generation, comparison)

Group B — cannot be prior art (post‑date the 14 Apr 2008 critical date); listed only because they appear in the citation graph:

Group C — Signal integrity / noise / load‑isolation legacy citations (front‑page class of art; mostly not claim‑relevant)

These dominate the older portion of the (56) list and correspond to the '523's sibling Netlist disclosures ("Self‑Adjusting Damper," US 8,154,901 "Circuit Providing Load Isolation and Noise Reduction"). None discloses the multi‑mode test architecture; they matter only for the signal‑characteristics limitations (programmable slew rate / DQ‑DQS match) if those appear in dependent claims.

Group D — DRAM stacking / module systems / later art (analytics‑flagged or forward citations)

Third‑party "most‑similar‑document" hits (Limestone/Techson validity report, top‑scored EP/foreign equivalents): EP1374073B1 (multi‑bank memory subsystem, Oracle/Sun); EP1415304B1 (Micron, burst‑order addressing); EP2562653B1 / EP1665056A2 / EP1665058B1 / EP1723526B1 (Micron, hub‑based memory systems); EP1944697B1 (Broadbus/Motorola, data access & multi‑chip controller); EP2057548B1 (Qualcomm, shared‑bus interrupt in multi‑rank subsystem); EP1963977B1 (Intel, memory chips down/up); EP1581877A2 (Sun, multi‑bank modules); EP0851425B1 (Compaq, EDO/FPM memory); EP0307401B1 (AT&T, variable reliability in a switching system). These are § 102(a)/(b)‑class foreign publications but are, individually, no closer than Group A/B on the two‑mode + data‑handler combination.

Deliberately excluded: the references in the ISR for WO2013152235A1 (e.g., US 2009/049358 A1 Jalloul; US 2003/023920 A1 Jeong; US 6,182,261 B1 Haller; US 2011/246850 A1 Rault; US 2004/260995 A1 Allpress). Those belong to a different Netlist‑related application (the self‑adjusting‑damper line, PCT/US2013/035336) and are not citations against the '523.

4. § 102 anticipation — bottom line

Applying the strict test (every element, arranged as claimed, in a single reference, enabled as of the critical date):

• No retrieved reference anticipates independent claim 1 (the two‑mode module in which, in the second mode, the control module itself generates the memory address/control signals and the data module both isolates the memory devices from the system memory controller and injects data patterns per control‑module commands). The closest single references fail at least one leg: Group A art supplies isolation/normal‑mode routing but no internal test generation; Group B art supplies internal generation but is embedded/ASIC‑level or lacks the mode‑switched module‑level isolation.
• No retrieved reference anticipates the data‑handler claim (claim 19 as printed / "claim 10" in the prior summary). Before making any § 102 assertion on that claim, resolve the claim‑numbering discrepancy in § 1 above.
• No retrieved reference anticipates the method claim (the prior summary's claim 19). Every step is individually old, but the claimed sequence within one module is not shown in one reference.
• The PTAB itself did not use § 102 against these claims in IPR2022‑00063 — it used § 103 (Lee + Sakata; Lee + Higuchi). That is the realistic doctrinal posture for this art.
• For dependent claims, several Group C references (e.g., US 2006/0140015 A1, Rambus, programmable driver turn‑on/slew) could potentially anticipate specific signal‑characteristic limitations (programmable slew rate / DQ‑DQS matching) if such limitations are actually recited — I could not map them because I could not verify the dependent‑claim text.

5. What I could not verify (do not treat as opinion on the merits)

1. The complete, authoritative (56) list for US10217523B1 from USPTO. Recommended source: PatentCenter → "Patent Citations" / "Referenced By," or the Google Patents "Patent Citations" and "Cited By" tabs for the exact document.
2. The identity of "Lee," "Sakata," and "Higuchi" and their exact grounds/claim charts — obtainable from IPR2022‑00063 papers and exhibits at PTAB E2E.
3. The true IPR2022‑00063 petitioner (Samsung per Patexia vs. Micron per the prior sections and a Micron/Netlist filing) and the FWD date/panel (3 May 2023, Moore/Jurgovan/McShane vs. 25 Oct 2023, Katz/McNamara/Takahashi).
4. The number of issued claims (34 vs. 20) and which claim is the "N‑bit bus / data handler" independent claim (10 or 19).
5. The exact bibliographic data for the ~20 legacy front‑page references enumerated in row C12, whose titles were not carried in the retrieved OCR.

Stated literally, as required: the patent under analysis is US 10,217,523 B1 (application 14/229,844), and all identifiers above are reproduced exactly as retrieved, including apparent OCR artifacts.

Obviousness Analysis of US10217523B1 under 35 U.S.C. § 103

This analysis identifies combinations of prior art references, as described within US Patent 10217523B1 itself, that would render the independent claims of the patent obvious to a person having ordinary skill in the art (PHOSITA). The patent's background and detailed description explicitly outline existing memory testing methodologies and their limitations, providing a clear motivation for a PHOSITA to combine these known elements to achieve the claimed invention.

General Motivation for Combination

The patent's background highlights several problems with existing memory testing methods:

• High Test Cost and Time: "Because of the significant amount of testing that memories undergo during the manufacturing process, there is generally substantial test cost and test time associated with ensuring the proper memory operation."
• Limitations of External Test Hardware (ATE): "external test hardware such as automatic test equipment ('ATE') is very expensive."
• Limitations of Embedded Self-Test Logic (MBIST) on DRAM Chips: "MBIST in DRAM chips generally cannot be fully utilized for system level testing of memory boards."
• Difficulty of Implementing MBIST on Memory Modules: "MBIST functional blocks on a memory module generally would be segregated into multiple chips on the memory module due to physical and electrical limitations and requirements." This leads to difficulties with interface signals, inter-block signal delay, and cross-checking logic.
• Limitations of AMB-based MIST (Memory Integrated Self Test): The self-test logic implemented in Advanced Memory Buffers (AMBs) suffers from "DIMM level routing problems," limited data width flexibility, and generally only supports "certain predetermined, fixed data widths."
• Limited Reporting from ASIC MBIST: "ASIC MBIST is generally only capable of detecting and reporting the pass/fail status of memory tests," which is insufficient for module repair.

A PHOSITA, aiming to reduce test costs, improve test efficiency, and overcome the noted limitations of existing on-module test solutions, would be motivated to integrate self-test capabilities directly onto memory modules in a practical and flexible manner.

Obviousness of Independent Claim 1

Claim 1 describes a memory subsystem with a circuit board, memory devices, a data module, and a control module, operable in a normal mode (where the control module uses system controller signals and the data module enables data paths to the system controller) and a test mode (where the control module generates its own address and control signals, and the data module isolates the memory devices from the system controller).

Combination of Prior Art References:

1. Standard Memory Module Architecture: This provides the fundamental elements of a "memory subsystem operable with a system memory controller," including a "circuit board," "plurality of memory devices," and the operation in a "normal mode" where the memory controller on the system board accesses the memory module. This is explicitly recognized in the patent's background, stating that "Once memory chips are deployed in a system, they also generally go through a system level memory test each time the system is booted. In addition, memory chips may undergo a parity checking process during normal system operation."
2. Embedded Self-Test Logic (MBIST): The patent describes MBIST as a known "memory test methodology" comprising "three distinct functional blocks: the address/control generator, the data generator/checker... and the test interface controller/register." MBIST inherently involves the generation of internal address and control signals and internal data for testing.
3. MIST in Advanced Memory Buffers (AMBs): The patent further describes "self-test logic (MIST) implemented in the AMB [which] includes command and address generation logic in addition to a data generator and checker." This demonstrates that internal self-test logic, capable of generating address, command, and data signals, was known in the context of memory modules (e.g., DIMMs containing AMBs).
4. Concept of Test Isolation: It is a well-established principle in electronic testing to "isolate" the device under test from external components to ensure independent and controlled testing.

Motivation for Combination:
A PHOSITA, recognizing the high cost and inefficiency of external Automatic Test Equipment (ATE) and the difficulties in fully utilizing chip-level MBIST for system-level memory board testing, would be motivated to integrate existing MBIST/MIST functionalities onto the memory module itself. The patent explicitly notes that "MBIST functional blocks on a memory module generally would be segregated into multiple chips on the memory module due to physical and electrical limitations and requirements," indicating that the idea of placing MBIST logic on a module was known, even if challenging.

To implement such an on-module self-test, it would be obvious to adapt the known internal signal generation capabilities of MBIST/MIST (representing the "control module generates the address and control signals" in test mode) and combine them with the existing normal operational mode of the memory module. Furthermore, during a dedicated self-test, a PHOSITA would find it obvious to "isolate the plurality of memory devices from the system memory controller" using known switching or buffering techniques (e.g., using a dual input register as part of the control module, as described for control module 22 in the patent, or a data multiplexer in the data path), to prevent interference from the system controller and allow the on-module test logic to operate independently. This combination directly addresses the problem of needing efficient, on-module testing capabilities.

Obviousness of Independent Claim 10

Claim 10 describes a memory subsystem with memory devices responsive to a control module, communicating via an N-bit wide system memory bus, and having a data module with a "plurality of data handlers," where each handler corresponds to an "n-bit section of the N-bit wide system memory bus" (n being a fraction of N) and configures "selected data paths" based on the operating mode.

Combination of Prior Art References:

1. Standard Parallel Memory Bus Architecture: Memory modules commonly interface with system memory controllers via an "N-bit wide system memory bus" (e.g., 64-bit or 72-bit wide DIMMs). These buses are typically handled by multiple individual memory devices, each responsible for an "n-bit section" (e.g., x4, x8, or x16 DRAMs on a x64 module). The patent acknowledges this by describing "memory modules 100 having widths of 4 bytes, 8 bytes, 16 bytes, 32 bytes, or 32 bits, 64 bits, 128 bits, 256 bits, as well as other widths (in bytes or in bits)."
2. Embedded Self-Test Logic (MBIST) with Data Generator/Checker: MBIST includes a "data generator/checker" block. When adapting MBIST for a memory module, especially given the patent's admission that "MBIST functional blocks on a memory module generally would be segregated into multiple chips on the memory module," it would be obvious to distribute this data generation/checking functionality.
3. MIST in AMBs: The MIST in AMBs includes a "data generator and checker". The patent highlights a limitation of AMB-based MIST: "the data width of self-test logic of the memory module will be limited to the data width of the AMB... [and is] not flexible... and generally supports only memory modules having certain predetermined, fixed data widths."
4. Data Multiplexers/Switches: The use of multiplexers (muxes) to selectively route data signals is a fundamental and well-known concept in digital electronics, particularly for switching between different operational modes or sources/destinations. The patent itself mentions that the "switch 44 may include a data multiplexer/demultiplexer ('data mux/demux')."

Motivation for Combination:
Given the established need for on-module self-testing (as for Claim 1), and the common architecture of memory modules where an N-bit wide bus is composed of multiple "n-bit sections" handled by individual memory devices or groups, a PHOSITA would be motivated to design the on-module self-test data logic to align with this modularity.

Specifically, the limitation of AMB-based MIST regarding data width flexibility would strongly motivate a PHOSITA to move beyond a single, fixed-width data generator. Instead, distributing the data generation and checking function into a "plurality of data handlers," each corresponding to a "respective n-bit section of the N-bit wide system memory bus," would be an obvious design choice to accommodate various module widths and increase flexibility. The patent states that "Because each of the data handlers 30 is operable independently of each of the other data handlers 30, the data handlers 30 are generally modular. As such, modifications in the configuration of the memory module 10 (e.g., changes in the bit-width of the memory bus, changes in the number of memory devices 20, etc.) may be less complicated to accommodate than in other types of self-testing memory modules 10." This clearly points to an inherent motivation to make such a system modular.

To allow these modular data handlers to function in both normal and test modes, it would be obvious to incorporate data multiplexers (switches) within or associated with each data handler. These switches would be "configured to enable selected data paths" to route either system controller data (normal mode) or internally generated test data (test mode), depending on the current operational mode of the memory subsystem. This modular and switch-based approach provides a flexible and efficient way to integrate self-test capabilities onto a standard memory module architecture.

Obviousness of Independent Claim 19

Claim 19 outlines a method of operating a memory subsystem, comprising selecting a mode (normal or test), and then, based on the selected mode, either providing address/control signals from the system controller and enabling data paths to it (normal mode), or generating internal address/control signals and isolating memory devices from the system controller (test mode).

Combination of Prior Art References:

1. Conventional Memory Module Operation: All memory modules operate by receiving "address and control signals" from a "system memory controller" and enabling "data paths" for normal data transfer. This is the default and well-understood operation.
2. Embedded Self-Test Logic (MBIST) Methodology: MBIST provides the methodology for "generating address and control signals" internally and applying them to memory devices, along with generating and checking test data.
3. MIST in AMBs Methodologies: As described in the patent, AMB-based MIST involves "command and address generation logic in addition to a data generator and checker." This is a direct example of internal self-test operations within a module.
4. General Principle of Mode Selection in Electronic Systems: Many electronic systems operate in different modes, with selection often achieved via control signals, registers, or commands (e.g., "The configuration may be through the I 2 C interface 15, for example, and may include configuring the test controller 36 for test mode.").
5. General Principle of Test Isolation: As noted for Claim 1, isolating the device under test from external signals during a self-test is a standard practice to ensure controlled test conditions.

Motivation for Combination:
The method described in Claim 19 is a direct operational flow of the hardware architecture described in Claim 1. The motivation for combining these known operational steps is driven by the same imperative: to overcome the cost and complexity challenges of memory testing by enabling effective on-module self-testing.

A PHOSITA, seeking to implement an efficient self-testing capability on a memory module, would naturally devise a method that transitions between normal system operation and an internal test mode. This method would logically involve:

• Selecting a mode: This is a fundamental step in any multi-mode system, enabling the desired functionality.
• Normal Mode Operations: When the system is not testing, the module should function as a standard memory, passing signals and data from the system controller.
• Test Mode Operations: When a self-test is desired, the system would switch to using its internal test logic (control module generating signals, data module generating/checking data), and simultaneously "isolating the plurality of memory devices from the system memory controller" to ensure the integrity of the self-test. The patent describes how this transition can be initiated and managed (e.g., via I2C interface, parity-in pin assertion).

The steps outlined in Claim 19 merely describe the logical sequencing of known functionalities (normal memory operation and MBIST-like internal testing) within a single memory module, motivated by well-understood problems in memory testing.