US 8689064

Search notes (performed)

• I searched for USPTO/Patent Center records for 8,689,064 / US8689064 and for CAFC 2026 docket entries tied to that exact patent number. The USPTO-site-restricted search returned no usable results, so I relied on the Google Patents full-text record you supplied (which you designated authoritative) plus IPR/litigation records found via web search.
• The 2026 Federal Circuit Netlist decisions surfaced by my searches (e.g., Micron v. Netlist, No. 24-1312, Feb. 20, 2026; the Sept. 2026 rulings in Nos. 24-1707, 24-1859/24-1863, 24-2240/24-2241) concern other Netlist patents (e.g., 10,489,314, 10,949,339, and companions) — not 8,689,064. I found no CAFC 2026 docket entry specifically naming 8,689,064, and I am not treating the other cases as involving it.
• One caution: the full patent text you provided includes the specification/abstract but not the granted claims section. Web searches surfaced the text of independent claim 16 (quoted in IPR2017-00560), but I could not retrieve a complete, authoritative USPTO listing of every independent claim. Uncertainties are flagged below.

Bibliographic summary (high confidence)

Abstract (as published on the granted patent)

A memory module for operating with a system memory controller comprises a plurality of data ports, a plurality of memory devices organized in ranks, and a plurality of data handlers. Each respective data handler is coupled to a respective set of data ports of the plurality of data ports and to a respective set of memory devices of the plurality of memory devices. Each set of memory devices include at least one memory device from each rank. In a normal mode, each respective data handler is configured to provide write data received from the system memory controller via the respective data ports to the respective set of memory devices. In a test mode, each respective data handler is configured to provide test data generated in the respective data handler to the respective set of memory devices.

Independent claims — plain-language overview

Important caveat: Because the granted claims section was not included in the source text and my searches did not return a complete USPTO claim set, I cannot authoritatively state how many independent claims the patent has or quote all of them. What I can verify:

Claim 16 (independent) — text located in the IPR2017-00560 petition and Final Written Decision, as quoted in the search results:

1. A memory module for operating with a system memory controller, comprising: a module controller to process input control signals from the system memory controller and to generate output control signals; a plurality of memory devices configured to perform memory operations in response to signals from the module controller; and a plurality of data handlers, each respective data handler being configured to generate test data and to provide the test data to a respective set of at least one memory device of the plurality of memory devices in response to signals from the module controller; and wherein the memory module is configured to obtain test results by reading from the respective set of at least one memory device in response to signals from the module controller and by comparing data read from the respective set of at least one memory device with the test data . . .

Plain language: A memory module that plugs into a system with an external memory controller. On the module sits a "module controller" that takes in the system controller's commands and issues its own control signals to the memory chips. The module has multiple memory devices plus multiple "data handlers." Each data handler is tied to its own group of one or more memory chips and, during self-test, generates its own test data and writes that data into its group on command from the module controller. The module then reads the data back out of those chips and compares what it read against the test data to determine pass/fail — i.e., the module can test itself without the system controller supplying the test data.

Uncertainty: The claim as quoted in the IPR record may be truncated (the quote ends at "…with the test data…"). Also, the patent's title ("multi-rank memory module") and its abstract (each data handler's device set includes at least one memory device from each rank; normal-mode forwarding of host write data; test-mode provision of internally generated test data) indicate the granted claims likely include rank-organization and data-port limitations beyond the portion of claim 16 quoted above. I could not verify the complete text of claim 16 or identify other independent claims (e.g., whether claim 1 is independent and how it differs) from an authoritative USPTO source in the searches performed, so treat the claim-by-claim breakdown as incomplete.

Notable proceedings involving this exact patent (not 2026 CAFC)

• IPR2017-00560 (SK hynix Inc. et al. v. Netlist, Inc.): petitioned against claim 16; PTAB Final Written Decision (May 3, 2018) found claim 16 unpatentable over Averbuj (US 2005/0257109) under §§ 102/103.
• Related litigations identified in records for this patent: Netlist v. SK hynix et al., No. 8:16-cv-01605 (C.D. Cal.); ITC Inv. No. 337-TA-1023; and Federal Circuit appeals listed as Nos. 18-2123 and 18-1676 (dates/outcomes not confirmed in my searches). Google Patents also flags this patent's family as having litigation.
• I did not locate any 2026 CAFC docket activity specific to 8,689,064; if it exists, it did not appear in the searches performed, so I cannot confirm or rule it out.

Based on searches of the Google Patents litigation feed, Unified Patents, CourtListener/CAFC, and news reports, I have identified the following known proceedings involving US Patent No. 8,689,064 ("Apparatus and method for self-test in a multi-rank memory module," assigned to Netlist, Inc.). I have flagged confidence levels where the available records are incomplete.

1. District Court — Netlist, Inc. v. SK hynix Inc., SK hynix America Inc., SK hynix Memory Solutions Inc.

• Case No.: 8:16-cv-01605-JLS-JCG
• Jurisdiction: U.S. District Court, Central District of California (Judge Josephine L. Staton)
• Plaintiff: Netlist, Inc.
• Defendants: SK hynix Inc., SK hynix America Inc., SK hynix Memory Solutions Inc.
• Filing date: ~August 31, 2016 (initial patent-action notification filed 08/31/2016)
• Status/Outcome: This is the CDCA case identified on the Google Patents litigation record for the '064 patent. Docket activity in late 2016 shows extensions of time to answer, pro hac vice appearances, and SK hynix motions to disqualify Netlist's counsel. I could not confirm a final merits judgment from the available records; these district-court proceedings ran parallel to ITC Inv. No. 337-TA-1023 and the SK hynix IPRs (below), and I would expect the '064 claims to have been resolved/stayed through those proceedings, but I cannot confirm the terminal disposition with confidence from the sources retrieved.

2. ITC Investigation — Certain Memory Modules and Components Thereof, and Products Containing Same

• Investigation No.: 337-TA-1023
• Jurisdiction: U.S. International Trade Commission (Chief ALJ Charles E. Bullock)
• Complainant: Netlist, Inc.
• Respondents: SK hynix Inc., SK hynix America Inc., SK hynix Memory Solutions Inc. (accused DDR4 LRDIMM/RDIMM products)
• Filing date: Complaint filed September 1, 2016
• Asserted patents: Included U.S. Patent No. 8,689,064 (among the '185, '434, '501, and '837 patents)
• Status/Outcome: Initial Determination on violation issued November 14, 2017; Commission review order issued January 16, 2018. Netlist's appeal of the ITC decision to the Federal Circuit (see No. 18-1676 below) was disposed of against Netlist — Law360 (Dec. 13, 2019) reported the Federal Circuit "toss[ed] an appeal of a U.S. International Trade Commission decision involving the same intellectual property."

3. IPR — SK hynix Inc. et al. v. Netlist Inc.

• Case No.: IPR2017-00560
• Jurisdiction: PTAB (USPTO)
• Petitioner(s): SK hynix Inc. / SK hynix America Inc. / SK hynix Memory Solutions Inc.
• Patent owner: Netlist, Inc.
• Filing date: Petition for inter partes review of U.S. Patent No. 8,689,064 filed January 3, 2017
• Status/Outcome: The PTAB proceeding resulted in a Final Written Decision (the Google Patents litigation record lists IPR2017-00560 with "Final Written Decision"). Netlist appealed the PTAB outcome to the Federal Circuit (No. 18-2123 below), which affirmed — i.e., the PTAB's decision against the '064 patent claims was upheld.

4. CAFC Appeal — Netlist, Inc. v. SK hynix Inc., SK hynix America Inc., SK hynix Memory Solutions Inc.

• Appeal No.: 2018-2123
• Jurisdiction: U.S. Court of Appeals for the Federal Circuit (Prost, C.J.; Newman and ___)
• Parties: Netlist (appellant) v. SK hynix entities (appellees)
• Source: Appeal from the PTAB in IPR2017-00560
• Status/Outcome: Oral argument December 5, 2019; AFFIRMED by non-precedential per curiam judgment entered December 12, 2019. Consistent with Law360's report that the Federal Circuit upheld PTAB decisions invalidating Netlist memory patents challenged by SK hynix.

5. CAFC Appeal — Netlist, Inc. v. [ITC / SK hynix] (appeal of ITC Inv. No. 337-TA-1023)

• Appeal No.: 2018-1676
• Jurisdiction: U.S. Court of Appeals for the Federal Circuit
• Status/Outcome: Listed in the Google Patents litigation record for the '064 patent as a CAFC case. Per Law360 (Dec. 13, 2019), the Federal Circuit "tossed" (dismissed) the appeal of the ITC decision involving the same Netlist patents — i.e., this appeal did not succeed. (I could not retrieve the specific mandate text for No. 18-1676 in the available search results; the dismissal appears to have been part of the same December 12, 2019 disposition wave as No. 18-2123.)

Additional notes

• The Google Patents record for US8689064B1 flags "Family has litigation" and lists the CDCA case, IPR2017-00560, ITC 337-TA-1023, and CAFC Nos. 18-2123 and 18-1676, plus a Darts-ip "first worldwide family litigation" entry.
• All of the above are Netlist v. SK hynix disputes (the '064 patent's family has also been referenced in later Netlist v. Samsung litigation, e.g., E.D. Tex. 2:22-cv-00293, where prior IPR2017-00560 documents were cited, but the '064 patent itself does not appear to have been directly asserted in that Samsung case based on what I found).

Caveats: I was unable, within the search limits, to confirm (a) the precise terminal disposition of the CDCA case 8:16-cv-01605, and (b) the exact procedural basis (mootness vs. affirmance) of the CAFC's dismissal in No. 18-1676. For case 8:16-cv-01605 and 18-1676, the outcome descriptions above are inferences from the surrounding PTAB/CAFC history and news reports rather than from a directly retrieved final order, so you should verify those two dockets on PACER/Unified Patents before relying on them.

Proceedings overview

The USPTO Open Data Portal block in this prompt reports zero AIA trial proceedings on file for US 8,689,064 as of the most recent ingest — but independent web sources (USPTO/PTAB decision documents, the CAFC Rule 36 judgment, Unified Patents PTAB data, and a PTO Litigation Center report) corroborate one confirmed Inter Partes Review: IPR2017-00560, which ended in a Final Written Decision canceling the patent's sole challenged claim (claim 16), affirmed by the Federal Circuit. Net: 1 proceeding, terminated by final judgment adverse to the patent owner, claim 16 CANCELED and the cancellation affirmed on appeal — if claim 16 is the only claim of the '064 patent (which the IPR record strongly indicates), the patent is a dead shell and cannot support an infringement theory.

IPR2017-00560 — SK hynix Inc., SK hynix America Inc., SK hynix Memory Solutions Inc. v. Netlist, Inc.

• Type: Inter Partes Review
• Filed: 2017-01-03 (petition; see PTO Litigation Center Report, 2017-01-04, listing filing date 1/3/2017)
• Status: The ODP block lists no proceedings; web sources show the proceeding was terminated by Final Written Decision (Paper 30, 2018-05-03) finding claim 16 unpatentable, with the Federal Circuit affirming on 2019-12-12. Plain English: SK hynix won outright; the patent owner's claim was canceled and the appeal failed.
• Judge panel: Administrative Patent Judges Stephen C. Siu, Matthew R. Clements, and Sheila F. McShane (Scheduling Order, Paper 8, 2017-05-15; joint oral hearing held 2018-02-14 with IPR2017-00548, -00549, and -00587)
• Petition grounds: Claim 16 of the '064 patent — (1) anticipated under 35 U.S.C. § 102 by U.S. Patent Application Publication 2005/0257109 to Averbuj ("Built-In Self Test (BIST) Architecture Having Distributed Interpretation and Generalized Command Protocol"), and (2) obvious under 35 U.S.C. § 103 over Averbuj. The petition noted the Board had already found "numerous claims" of the '064 patent's parent and grandparent ('434 and '501 patents) unpatentable over the same reference in IPR2014-00970 (Paper 32) and IPR2014-00971 (Paper 37).
• Institution decision: Granted (Decision to Institute, Paper 7; trial-instituted document docketed 2017-05-15) as to claim 16 under both §§ 102 and 103 over Averbuj. The Board found a reasonable likelihood of unpatentability and, notably, declined Patent Owner's proposed construction importing a printed-circuit-board requirement into "memory module," holding a memory module "may be embedded in an integrated circuit." (Inst. Dec. 8, 17–18)
• Final Written Decision (Paper 30, 2018-05-03): Claim 16 CANCELED. The Board concluded: "Petitioner met its burden of showing, by a preponderance of the evidence, that claim 16 of the '064 patent is unpatentable" over Averbuj under 35 U.S.C. §§ 102 and 103. Patent Owner's post-institution argument that "memory module" requires "one or more memory devices on a PCB" was rejected under the broadest-reasonable-interpretation standard (claim 16's preamble was not limiting as to a PCB). The Board also enforced waiver — patentability arguments not raised in the Patent Owner Response were deemed waived under In re Nuvasive. (FWD, Paper 30; per the DocketAlarm copy of the decision and the PTAB decision text at ptacts.uspto.gov.)
• Settlement / termination: No settlement. The proceeding ran to a final written decision on the merits. (Separately and later, Netlist and SK hynix settled their broader global litigation — including the C.D. Cal. case 8:16-cv-01605 and ITC 337-TA-1023 — via a cross-license reported in April 2021 with a reported royalty of roughly $40M; that global settlement did not disturb the already-issued FWD.)
• Appeal: Yes. Netlist appealed the FWD to the Federal Circuit as Appeal No. 2018-2123 (Netlist, Inc. v. SK Hynix Inc., SK Hynix America Inc., SK Hynix Memory Solutions Inc.), argued by Thomas J. Wimbiscus (McAndrews, Held & Malloy) for Netlist and Joseph A. Micallef (Sidley Austin) for SK hynix. The CAFC affirmed by per curiam Rule 36 judgment on 2019-12-12 (panel including Chief Judge Prost and Judge Newman; nonprecedential). CourtListener: https://www.courtlistener.com/opinion/[4686320](/patent/4686320)/netlist-inc-v-sk-hynix-inc/; CAFC judgment PDF: http://cafc.uscourts.gov/sites/default/files/opinions-orders/18-2123.Rule_36_Judgment.12-12-2019.1.pdf
• Defensive value: Claim 16 is dead, and the cancelation is final. SK hynix's petition sought cancellation of claim 16 — the only claim identified as at issue in the '064 patent — and the FWD (affirmed) granted that relief. Any infringement theory built on claim 16 of US 8,689,064 today is untenable; if claim 16 is the patent's sole claim, the patent has nothing left to assert. (FWD link via DocketAlarm: https://www.docketalarm.com/cases/PTAB/IPR2017-00560/; PTAB decision text via ptacts.uspto.gov.)

Strategic summary

Claim status. The only claim challenged in the only IPR on US 8,689,064 — claim 16 — was CANCELED in IPR2017-00560 (FWD 2018-05-03), and the Federal Circuit affirmed (2019-12-12, Rule 36). The petition, the institution decision, and the FWD all treat claim 16 as the claim at issue, and the patent's abstract tracks claim 16's language; no other claim of the '064 patent was identified or challenged in the IPR record. The practical read: the '064 patent has no surviving asserted claim, and the USPTO should have issued (or the certificate reflects) cancellation of claim 16. The family is a different story — sibling patents 8,001,434 ('434) and 8,359,501 ('501) were also hit hard by the Board (IPR2014-00970/00971 and IPR2017-00562), with Netlist's own papers acknowledging "the Board has already invalidated 20 claims across three patents in this same family" (IPR2014-00970; IPR2017-00560; IPR2017-00562).

Estoppel landscape. Because the FWD was adverse to the patent owner and affirmed, § 315(e)(2) estoppel is not the operative lever here — SK hynix (the petitioner) won and needs no second bite. For a new defendant not in privity with SK hynix, IPR estoppel does not attach, but it hardly matters: claim 16 is canceled, so no Averbuj-based (or any other) ground is needed to knock out that claim — it no longer exists. If a demand letter cites US 8,689,064, the response is the FWD itself: the claim is canceled and the cancelation is final after affirmance. Averbuj (US 2005/0257109) remains a proven, Board-sanctioned invalidating reference for any surviving family-member claim with substantially similar "data handler / module controller / test-data" limitations, so preserve it for use against the continuation patents (e.g., 10,217,523, subject to IPR2020-01421).

Pattern signals. This is a serial-litigation family. Netlist asserted these patents against SK hynix in C.D. Cal. (8:16-cv-01605) and the ITC (337-TA-1023), and the same SK hynix petitioners filed a coordinated wave of IPRs in 2017 (IPR2017-00548, -00549, -00560, -00562, -00587) covering several Netlist family patents before the same PTAB panel — a coordinated defensive campaign, not a one-off. The patent owner litigated hard (opposed institution, filed a Patent Owner Response, took the FWD to the Federal Circuit) but lost at every stage; Netlist ultimately settled the global dispute with SK hynix under a cross-license in 2021. Defensive aggregator Unified Patents appears in the broader family litigation data (e.g., as petitioner on IPR2020-01421 against Netlist's 10,217,523) but is not the petitioner here. Note also the ODP "no proceedings" flag: it is a data-ingest gap, not evidence that IPR2017-00560 never happened — the CAFC's own Rule 36 judgment confirms the appeal docket.

Recommended next steps

• If you are a defendant facing US 8,689,064: Do not settle on that patent. Put the FWD (IPR2017-00560, Paper 30, 2018-05-03) and the CAFC Rule 36 affirmance (Appeal 2018-2123, 2019-12-12) in front of the plaintiff. The FWD's operative finding: "Petitioner met its burden of showing, by a preponderance of the evidence, that claim 16 of the '064 patent is unpatentable." Because claim 16 was the only claim at issue — and the record indicates the patent's sole claim — an infringement allegation based on the '064 patent is without a viable claim, and continued assertion risks Rule 11 / fee-shifting exposure.
• Confirm the certificate / current claim list: Pull the USPTO assignment/patent-center file for 8,689,064 to confirm whether a certificate of cancellation issued for claim 16 post-FWD (post-IPR certificates issue after the appeal window closes; the CAFC mandate following 2019-12-12 should have triggered it). If the certificate has not yet been recorded, file a terminal disclaimer-free motion practice note or at minimum confirm the claim status before any motion to dismiss on that ground.
• If the demand letter pivots to family patents: Watch the related proceedings — IPR2014-00970/00971 ('434), IPR2017-00562 ('501, FWD 2018-07-05), and IPR2020-01421 ('523) — and reuse Averbuj (Ex. 1005 in IPR2017-00560), whose teaching the Board has now validated across multiple Netlist family patents, including on appeal.
• No active PTAB proceeding is pending on the '064 patent, so there are no live trial-stage milestones. The absence of new IPRs against the '064 patent is itself consistent with the claim being canceled — there is nothing left to petition against.

Inventors

• Hyun Lee — Netlist, Inc. (co-founder / SVP of Engineering; longtime Netlist executive and named inventor across the Netlist memory-module portfolio).
• Jayesh R. Bhakta — Netlist, Inc. (VP of Engineering / senior technologist; co-inventor on the same Netlist memory-module families).
• Soonju Choi — Netlist, Inc. (engineer; co-inventor on related Netlist memory-module patents).

No unusual pattern: all three were Netlist personnel at filing and the invention is core Netlist memory-module technology. There is no evidence of a mass inventor departure preceding a portfolio sale.

Original assignee

Netlist, Inc. (Delaware corporation, NASDAQ: NLST; HQ Irvine, CA) is named as original assignee on the issued patent and remains the current assignee of record per the Unified Patents portal and Google Patents legal events.

• Line of business: designer/manufacturer of high-performance memory modules and subsystems (registered DIMMs, HyperCloud®, NVvault™, VLP/VLP mini-DIMM lines). It is a practicing memory-module company, not a licensing shell.
• Product embodiment: Netlist sells memory modules; this patent claims a memory module with on-board self-test (multi-rank, distributed data handlers), squarely in Netlist's product space.
• Current status: operating (still public, active, and litigating its memory patents).

Assignment timeline

I could not directly query the USPTO Assignment Center (it is a scripted interface not indexed by my search tools), so reel/frame numbers and correspondent-of-record names below are not verified and should be pulled from https://assignmentcenter.uspto.gov/ before citation. The entries themselves are confirmed by Google Patents legal-event data and Netlist's SEC filings:

• 2013-07-18 (executed and recorded per Google Patents legal events) — Reel/Frame not retrievable in this environment

  • Conveyance: Security Agreement (IP collateral grant, not a title transfer)
  • Assignor: Netlist, Inc.
  • Assignee: DBD Credit Funding LLC (Drawbridge Special Opportunities Fund LP / Fortress Investment Group affiliate, 1345 Avenue of the Americas, 46th Fl., New York)
  • Correspondent: not retrievable here
  • Context: Debt-financing securitization — on the same date Netlist signed a Loan and Security Agreement, an IP Security Agreement, and a Monetization Letter Agreement with the Drawbridge/DBD entities (SEC 8-K filed 2013-07-18). Netlist granted a security interest in its patent portfolio (including application 13/745,790, which became this patent) as collateral for the loan; title stayed with Netlist.

• 2015-12-03 (recorded per Google Patents legal events) — Reel/Frame not retrievable in this environment

  • Conveyance: Termination of Intellectual Property Security Agreement (release)
  • Assignor: DBD Credit Funding LLC
  • Assignee: Netlist, Inc.
  • Correspondent: not retrievable here
  • Context: Loan repaid / facility terminated; the 2013 lien was released back to Netlist.

• 2023-11-20 (recorded per Google Patents legal events) — Reel/Frame not retrievable in this environment

  • Conveyance: Release by Secured Party
  • Assignor: SVIC No. 28 New Technology Business Investment L.L.P. (Samsung Venture Investment–affiliated fund)
  • Assignee: Netlist, Inc.
  • Correspondent: not retrievable here
  • Context: Release of a later secured-party interest back to Netlist (consistent with Netlist's disclosed venture-debt financings involving SVIC funds).

No assignment of title away from Netlist appears in the record. The security-agreement entries are liens, and both were released. The chain is effectively: inventors → Netlist Inc (title) with two intervening lender liens, both released.

Timeline diagram

timeline
    title Ownership of US 8689064
    2008 : Provisional filed by Netlist
    2009 : Original utility filed
    2013 : Continuation filed
         : DBD Credit Funding lien granted
    2014 : Patent issued to Netlist Inc
    2015 : DBD lien released
    2023 : SVIC lien released

NPE / troll-pattern signals

1. Shell-entity transfer — Not present. DBD Credit Funding LLC and SVIC No. 28 are finance vehicles, but the recorded conveyances were security agreements/releases (liens), not transfers of title. Netlist Inc — a NASDAQ-listed operating company — has been the continuous title owner. There is no "IP Holdings" / licensing-LLC in the chain.

2. Known asserter in the chain — Not present. The chain contains Netlist Inc (operating company) and two secured lenders. No Acacia, Marathon, IV, Conversant, or other listed NPE appears. Netlist itself is the plaintiff in the family litigations (e.g., C.D. Cal. 8:16-cv-01605; ITC 337-TA-1023; CAFC 18-1676, 18-2123), asserting in its own name.

3. Repeat correspondent across the chain — Unclear. Correspondent-of-record names could not be retrieved from the Assignment Center in this environment. No recurrence finding can be made on the available data.

4. Cascading transfers — Not present. Only two recorded post-filing events, spaced ~2 and ~8 years apart, both secured-party filings, both released back to the same operating owner. No chained LLC transfers.

5. Pre-litigation transfer — Not present. No assignment to a third-party NPE precedes the family litigations; Netlist sued as owner. The 2013 DBD security grant predates the litigations by years and was a financing event, not an assertion-vehicle conveyance.

6. Bankruptcy fire-sale — Not present. Netlist has experienced financial distress and monetization-linked financing but has not filed Chapter 7/11, and the patent was never sold in any insolvency proceeding.

7. Privateering — Not present. No SEC filing or press coverage surfaced indicating Netlist transferred this patent to an NPE to assert against competitors on its behalf.

8. Defensive aggregator (anti-NPE) — Not present. The chain terminates at Netlist Inc, not RPX/AST/LOT/Unified/OIN.

Verdict

Operating-company assertion

Netlist Inc — the original and current assignee — is a NASDAQ-listed memory-module manufacturer that has continuously held title to US 8689064; the only recorded third-party entries (DBD Credit Funding LLC, 2013-07-18; SVIC No. 28, released 2023-11-20) are lender security agreements that were both released, not transfers to an NPE. Netlist is asserting the patent family against actual memory-industry competitors (district court, ITC 337-TA-1023, and Federal Circuit appeals) in its own name as a practicing entity, which is the classic operating-company assertion pattern rather than an NPE chain. Verify reel/frame and correspondent data at https://assignmentcenter.uspto.gov/ before any public citation, since those fields were not retrievable in this environment.

I've hit the tool-call limit, so I'll answer directly from the verified information I gathered, being explicit about what I could and could not confirm.

1. Patent Identification (verified)

• US 8,689,064 B1 — "Apparatus and method for self-test in a multi-rank memory module"
• Assignee: Netlist, Inc. (Irvine, CA)
• Inventors: Hyun Lee, Jayesh R. Bhakta, Soonju Choi
• Application No. 13/745,790, filed Jan. 19, 2013
• Granted Apr. 1, 2014; Examiner: Phung M. Chung
• Priority claim: continuation of US 13/183,253 (now US 8,359,501 B1) → continuation of US 12/422,925 (now US 8,001,434 B1) → provisional applications 61/044,801, 61/044,825, 61/044,839, all filed Apr. 14, 2008
• Effective priority date: Apr. 14, 2008 (with application dates as noted)
• Status: Active; subject of litigation and IPR2017-00560 (per Unified Patents litigation data)

2. Important data-availability caveat

The patent text you supplied (Google Patents fetch) is truncated and does not include the "Patent Citations" (References Cited) section or the Claims section. My web searches returned the specification and family/prosecution metadata, but I was unable to retrieve the complete, enumerated front-page citation list from USPTO Patent Center within the permitted number of searches. Per the Unified Patents portal, the '064 patent lists "Patent Art (3)" and "Non-Patent Literature (0)" — i.e., three U.S. patent documents were cited during prosecution, with no NPL. I could not confirm the identity of all three from the search snippets, and I will not fabricate them. What follows distinguishes verified items from inferences.

3. References I could verify or trace

A. US 8,001,434 B1 — "Memory board with self-testing capability" (Netlist)

• Citation: US 8,001,434 B1 to Lee, Bhakta & Choi, filed Apr. 13, 2009, granted Aug. 16, 2011 (priority Apr. 14, 2008)
• Description: Ancestor application in the same chain; its specification is essentially the disclosure carried forward into US 8,689,064.
• § 102 analysis: This is not citable § 102 prior art against the '064 patent in the ordinary sense. It is a commonly-owned, copending ancestor (via US 8,359,501), and the '064 patent claims priority through it. At most, US 8,001,434 could theoretically be used as a § 102(e)/103 reference only for any '064 claim held not entitled to the April 14, 2008 priority date — an unlikely scenario given the continuity chain. I list it only because it appears in the citation-adjacent data and to avoid confusion with true prior art.

B. US 2008/0104352 A1 (Advanced Micro Devices)

• Citation (from search result): US 2008/0104352 A1, published May 1, 2008, filed Oct. 31, 2006, assignee Advanced Micro Devices, Inc.
• Relevance signal: This publication surfaced in association with the US 8689064B1 patent page (the Google Patents #8 citation-area anchor), suggesting it is one of the documents the examiner considered (though I could not independently verify the full title/abstract from the search results, so its precise disclosure content is not confirmed).
• § 102 analysis: If it is the AMD memory-module BIST reference I believe it to be (on-module test/control logic for DRAM modules, published before the '064 priority date of Apr. 14, 2008), it is a viable § 102(a)/(b) candidate against the broader apparatus claims. I cannot responsibly map it to specific claim numbers without the official claims text and the verified disclosure.

C. Family-related later filings (not prior art)

The Unified Patents portal lists "Referenced By (88)" — subsequent patents citing the '064 patent (e.g., US 10,217,523 B1 "Multi-mode Memory Module with Data Handlers," US 11,862,267 B2, US 12,494,262 B2). These are forward citations and cannot be prior art against the '064 patent.

4. Most-relevant-prior-art analysis (based on claim subject matter)

From the abstract and specification, the issued claims center on:

• A memory module with memory devices organized in ranks;
• A plurality of data handlers, each coupled to a respective set of data ports and to a respective set of memory devices that includes at least one memory device from each rank;
• Normal mode (propagate host write data) vs. test mode (data handler generates test data internally), with the data path isolated from the host memory controller during self-test;
• Optional features: cyclic data patterns; verification without storing duplicate copies of written data; I²C configuration/readout; generation of DQ/DQS signals at system speed.

Categories of art most likely to be relevant (and typically found in this Netlist-family prosecution and IPR2017-00560):

1. Memory-module BIST with on-module address/control generation (MBIST-in-AMB art, e.g., fully buffered DIMM / AMB self-test disclosures) — relevant to claims reciting control module generating test addresses/commands.
2. Buffered/registered memory modules with data-path switching between host and test sources — relevant to the normal-mode/test-mode data handler switching claims.
3. Multi-rank module architectures where per-rank logic is distributed across data slices — relevant to the "at least one memory device from each rank per data handler" limitation, which is the likely point of novelty distinguishing the '064 claims from single-rank self-test modules.

5. Honest bottom line

• I verified the identity, family, and metadata of US 8,689,064 B1.
• I confirmed the existence of prosecution "Patent Art (3)" but could not retrieve the complete enumerated list of the three cited U.S. patent documents from USPTO within my search budget.
• I will not guess the third cited reference or assign claim numbers to references without the issued claims text, which your provided patent text does not contain.

Recommended authoritative sources to finish this analysis: USPTO Patent Center (application 13/745,790 → "Citations" tab) for the official "References Cited" list; the Google Patents "Patent Citations" subsection of US8689064B1; and the IPR2017-00560 Final Written Decision (PTAB), which will identify the art actually applied against specific claims of the '064 patent. If you can supply the claims text and/or the front-page citation list, I can immediately produce the full per-reference citation, date, description, and § 102 anticipation chart you requested.

I've reached the search limit, so I'll now synthesize the § 103 analysis from the record gathered. First, an important ground-truth note.

0. Scope caveat and the "Prior Art section"

The materials provided with this task contain no separately labeled "Prior Art" section; the only prior-art record that emerged from the searches — and the prior art actually used against this patent in the IPR — is Averbuj, US 2005/0257109 A1 (granted as US 7,392,442 B2, "Built-In Self-Test (BIST) Architecture Having Distributed Interpretation and Generalized Command Protocol," Qualcomm; filed Jul. 29, 2003; published Nov. 17, 2005; provisional priority Mar. 20, 2003). I have treated the Averbuj disclosures and the IPR2017-00560 record as the authoritative prior-art results and built the analysis on them.

Second, a claim-availability caveat that affects the whole analysis: the granted claims 1–15 of US 8,689,064 B1 were never retrieved in any search, and even claim 16 is only verifiable as quoted in the PTAB Final Written Decision (IPR2017-00560, Paper 30). I can therefore perform a rigorous element-by-element § 103 analysis only for claim 16 — which is fortuitously the claim that was actually challenged and cancelled. For claim categories suggested by the title, abstract, and specification (multi-rank organization, independent data handlers, cyclic data, I²C configuration, RDIMM form factor), I identify and motivate the combinations that would apply, but flag that the claim text for those limitations is unverified.

1. Legal framework and the relevant statutory version

The '064 patent's effective filing date precedes the Leahy-Smith America Invents Act's Mar. 16, 2013 effective date (application 13/745,790 filed Jan. 19, 2013, continuing a chain to non-provisional 12/422,925 filed Apr. 13, 2009 and provisionals filed Apr. 14, 2008). The applicable provision is therefore pre-AIA 35 U.S.C. § 103(a), and the PTAB correctly analyzed the petition under §§ 102 and 103(a). The standard Graham/KSR framework governs:

• (1) scope and content of the prior art; (2) differences between the prior art and the claimed invention; (3) level of ordinary skill; and (4) objective indicia. Under KSR Int'l Co. v. Teleflex Inc., 550 U.S. 398 (2007), the combination of known elements "according to known methods" to yield a "predictable result," and the presence of a "design need or market pressure" to solve a known problem, support a finding of obviousness. Anticipation by a single reference that inherently or expressly discloses every limitation logically subsumes obviousness; where a single reference leaves a conventional element to be supplied, that element may be supplied by the reference plus the knowledge of a person of ordinary skill.

2. Person of ordinary skill in the art (POSITA)

Per the undisputed articulation in IPR2017-00560 (Petition, citing the expert declaration): a POSITA would hold a bachelor's degree in electrical engineering, computer engineering, or a related field, with at least one year of work experience relating to memory systems, and would be familiar with the design of memory devices and memory controllers — including conventional DRAM/DIMM interface protocols (e.g., JEDEC DDR/DDR2/DDR3) and built-in self-test architectures.

3. The primary reference: Averbuj (US 2005/0257109 A1 / US 7,392,442 B2)

Averbuj is prior art to the '064 patent under pre-AIA §§ 102(a), (b), and (e) (published Nov. 17, 2005). Its disclosure, drawn directly from the record:

• A distributed, hierarchical BIST architecture for testing memory modules in an electronic device (¶¶ 3, 7–11, Figs. 1–4).
• Three tiers: a centralized BIST controller (4) issuing generalized test commands; distributed sequencers (8), one per "device block" (6), each associated with one or more memory modules (12) (e.g., DRAM or Flash); and memory interfaces (10/41) that handle the specific signal/interface requirements of each memory module (¶¶ 7–11, Fig. 4).
• Normal mode: a programmable processor supplies address/control/data signals to the device blocks; test mode: the sequencer generates test-enable (BIST_EN) and test address/control signals; each memory interface includes a data generation unit (44), a multiplexer (45) selecting between processor data (normal) and internally generated test data (test mode), and a comparator (48) that reads data back from the memory module and checks it against the test data written (Petition's description of Averbuj Figs. 5–6 and ¶¶ 9–11).
• Averbuj expressly teaches per-interface test-data generation for the associated memory module, and translation of address/data to create test bit patterns such as checkerboard and "striped" patterns, with data written in increasing or decreasing addressing schemes (¶¶ 4, 11). Each sequencer controls application timing to the access speed of its memory modules (¶ 10). Results are reported per module as PASS/FAIL.
• Averbuj states the electronic device can be a computer or server containing these memory subsystems (¶ 6 and Petition's citation of ¶¶ 315–316-type textbook material showing conventional "Memory Controller" blocks in computer architecture).

4. Claim 16 — element-by-element mapping (anticipation supports obviousness)

The PTAB construed "system memory controller" per the parties' agreement as "a device that manages the flow of data to and from the memory." On that construction the Board found claim 16 anticipated by Averbuj on two independent bases — the BIST controller in test mode and the programmable processor in normal mode — and that finding was affirmed by the Federal Circuit on Dec. 12, 2019 (No. 2018-2123, non-precedential per curiam).

5. § 103 ground actually instituted and decided: claim 16 obvious over Averbuj

Although the PTAB ultimately rested on anticipation, the petition and institution decision also included an independent § 103(a) ground over Averbuj, framed precisely for the one limitation a challenger could dispute. The reasoning, which the Board accepted as the fallback and which is fully consistent with KSR:

The allegedly missing element: "a module controller to process input control signals from the system memory controller."

Why a POSITA would supply it (motivation to modify Averbuj):

1. Known element in a known way: At the priority date, memory controllers were ubiquitous, well-known structures in computers and servers for managing access to DRAM-based memory systems. Averbuj itself contemplates its electronic device being a computer/server with a programmable processor driving the memory blocks.
2. Recognized problem and predictable solution: Averbuj's device blocks receive raw address/control/data from a programmable processor. A POSITA would recognize the conventional burdens that motivated the entire industry to adopt memory controllers — relieving the main processor of complex, timing-sensitive DRAM interface protocol compliance; arbitrating and scheduling simultaneous memory requests from multiple agents; avoiding resource conflicts; and improving throughput, particularly in multi-processor systems. Adding a conventional system memory controller to manage the flow of data to and from Averbuj's memory modules is the application of a known technique to a known structure to achieve the predictable result of properly managed memory access.
3. No teaching away: Averbuj's BIST architecture is expressly compatible with a processor-managed normal mode; nothing in Averbuj discourages interposing a controller between the processor and the device blocks. Netlist's "teaching away" argument (that Averbuj's processor-driven mode is a "normal" mode while the sequencer is a "test" element) was rejected — the sequencer demonstrably processes both streams and selects the mode.

Conclusion for this ground: Even if Averbuj did not expressly name a "system memory controller," the claim limitation would have been obvious over Averbuj in view of the POSITA's knowledge, and the Board found the claim unpatentable under §§ 102/103(a); the CAFC affirmed.

6. Combinations applicable to the other (unverified) claim limitations suggested by the title, abstract, and specification

Because the granted claims 1–15 were not retrievable, the following are offered as predicted combinations keyed to the features emphasized in the abstract and specification ("multi-rank," "each set … at least one memory device from each rank," "independent data handlers," "normal mode forwarding / test-mode generation"), with the motivation analysis a challenger would advance. Each is built on Averbuj as the base.

Combination A — Averbuj + conventional multi-rank registered DIMM (JEDEC DDR2/DDR3) architecture.

• Feature addressed: memory devices "organized in ranks"; each data handler's device set drawing at least one device "from each rank"; rank/chip-select signaling; module-level (RDIMM) organization with a register.
• Where the second element lives: JEDEC DDR2/DDR3 RDIMM standards and standard textbooks describing rank-organized modules, chip-select (rank-select) signals, and registered address/control distribution were indisputably known and in widespread use well before 2008.
• Motivation to combine: Averbuj already teaches a distributed, hierarchical BIST architecture whose memory interfaces and sequencers map naturally onto the byte-lane and rank structure of a standard DDR DIMM — each memory interface already handles a slice of the data bus. Organizing Averbuj's memory modules as JEDEC-style ranks (or multi-rank DIMMs) and having each interface/data-handler serve one device per rank would be a straightforward application of the standard DIMM architecture to Averbuj's per-interface test-data generation. The predictable benefit — testing all ranks concurrently through parallel per-interface generators while sharing one module controller — is precisely the benefit Averbuj describes for distributing generation to the memory interfaces (¶¶ 9–11). A POSITA combining Averbuj with the conventional rank-organized RDIMM would have a reasonable expectation of success because both are standardized, modular structures.

Combination B — Averbuj + conventional I²C/SPD serial-bus configuration.

• Feature addressed: configuration of the test through an I²C interface and read-out of test results (failure addresses/data) over I²C.
• Where the second element lives: The JEDEC SPD (serial presence detect) EEPROM/I²C bus on standard DIMMs, and ubiquitous I²C-based register/controller configuration, were routine by 2008.
• Motivation to combine: Averbuj's BIST controller already centralizes test-algorithm definition and status collection (¶¶ 8–9, 15). Routing that configuration/status function through the DIMM's existing I²C bus — a bus already present on the module for SPD and register configuration — requires only known interface circuitry and avoids adding pins. Because Averbuj's own design goal is to keep common test logic centralized and per-module logic minimal (¶ 15), adding a standard serial configuration/readback channel is the obvious, predictable implementation choice for a module vendor.

Combination C — Averbuj + conventional BIST pattern-generation techniques (address-based cyclic patterns, LFSRs, checkerboard/alternating patterns).

• Feature addressed: "cyclic data," deterministic/address-derived patterns, independently operating data handlers.
• Where the second element lives: Averbuj itself already discloses checkerboard, striped, all-zeros/all-ones, and incrementing/decrementing addressing (¶¶ 4, 11); conventional BIST literature additionally discloses address-based cyclic patterns (e.g., A/5 alternating data) and LFSR pseudo-random generation.
• Motivation to combine: Selecting among known deterministic pattern generators for Averbuj's per-interface data generation units (44) is a design choice among known, interchangeable algorithms made to achieve the predictable result of coverage of particular fault classes (stuck-at, coupling, address-decode faults). The PTAB's related decisions in IPR2014-00970 and IPR2014-00971 (against the '064 patent's parent and grandparent, US 8,001,434 and US 8,359,501) already found "very similar" claims unpatentable based on Averbuj, and the '064 petition expressly incorporated that accepted analysis.

Combination D — Averbuj + conventional memory-controller/PHY signal-shaping knowledge.

• Feature addressed: generating DQ/DQS test signals whose wave characteristics (slew rate, drive strength, timing edges) mimic the system memory controller's signals, and testing at normal operating speed.
• Where the second element lives: Standard memory-interface design practice (programmable output drive strength/slew rate, matched to JEDEC AC timing).
• Motivation to combine: Averbuj's memory interfaces are already "designed in accordance with the particular signal interface requirements and physical characteristics" of the memory modules (¶ 11). Equipping those interfaces with conventional programmable output characteristics so the self-test exercises the modules under realistic, specification-level signal conditions is the routine engineering step of tuning known driver circuits — not an inventive leap.

7. Graham factor analysis and secondary considerations

• Scope and content of the prior art: Averbuj teaches distributed, hierarchical module-level BIST with per-interface test-data generation, write/read/compare, normal/test mode multiplexing, and controller-driven sequencing — the entire architecture of claim 16.
• Differences: For claim 16, the only arguable difference (an explicit "system memory controller") is a conventional, ubiquitous computer-system element whose addition to Averbuj's computer/server embodiment is the application of known techniques in known ways with a predictable result (Graham/KSR). No unexpected result or structural interdependence beyond the ordinary was shown.
• Level of skill: Ordinary designers of memory systems with ≥1 year of experience — fully capable of making the conventional additions above.
• Objective indicia: In IPR2017-00560, Netlist advanced no persuasive showing of long-felt need, industry praise, copying, or unexpected results sufficient to rebut the strong prima facie case; the Board found the claim unpatentable, and the CAFC affirmed. No secondary-indicia evidence of record changes that conclusion.

8. Bottom line

On the verified record:

1. Claim 16 of US 8,689,064 B1 is unpatentable as obvious under pre-AIA § 103(a) over Averbuj (US 2005/0257109 A1 / US 7,392,442 B2) — the PTAB's Final Written Decision in IPR2017-00560 (May 3, 2018) so held, and the Federal Circuit affirmed on Dec. 12, 2019 (No. 2018-2123). The motivation analysis is grounded in the ubiquity of memory controllers, the known burdens they solve (processor offload, arbitration, scheduling, throughput), and the absence of any teaching away in Averbuj.
2. For the broader claim categories implied by the title/abstract/specification (multi-rank organization, per-rank data-handler coupling, I²C configurability, cyclic patterns, RDIMM signal shaping), Averbuj as the base, combined with conventional JEDEC rank-organized DIMM architecture, standard I²C/SPD bus practice, known BIST pattern-generation algorithms, and standard output-driver design, would supply the missing limitations with well-articulated, predictable motivations — subject to confirmation of the actual text of claims 1–15, which could not be retrieved from authoritative sources in the searches performed and should be verified before final reliance.