US 10217523B1

Here's a concise summary of US Patent 10217523B1:

Title: Multi-mode memory module with data handlers

Assignee: Netlist Inc.

Inventors:

• Hyun Lee
• Jayesh R. Bhakta
• Soonju Choi

Filing Date: 2014-03-29

Issue Date: 2019-02-26

Abstract:
A memory subsystem is operable with a system memory controller. The memory subsystem comprises memory devices mounted on a circuit board, a data module mounted on the circuit board, and a control module mounted on the circuit board to provide address and control signals to the memory devices. The memory subsystem is operable in any of a plurality of modes, including a normal mode and a test mode. During the normal mode, the control module provides address and control signals based on those from the system memory controller, and the data module enables data paths between the memory devices and the system memory controller. During the test mode, the control module generates the address and control signals, and the data module isolates the memory devices from the system memory controller.

Independent Claims Overview:

• Independent Claim 1: This claim describes a memory subsystem designed to work with a system memory controller. It includes memory devices, a data module, and a control module, all mounted on a circuit board. The key feature is its ability to operate in multiple modes, specifically a normal mode and a test mode. In normal mode, the control module uses address and control signals from the system memory controller, and the data module connects the memory devices to the system memory controller. In test mode, the control module generates its own address and control signals for the memory devices, and the data module isolates the memory devices from the system memory controller.

• Independent Claim 10: This claim focuses on a memory subsystem that communicates with a system memory controller over an N-bit wide system memory bus. It features memory devices that handle data based on address and control signals from a control module. The crucial component here is a data module containing multiple "data handlers." Each data handler corresponds to a smaller "n-bit" section of the N-bit bus (where 'n' is a fraction of 'N'). Each data handler has multiple data paths and is configured to select which data paths are active to route a portion of the data bits, depending on whether the memory subsystem is in normal or test mode.

• Independent Claim 19: This claim outlines a method for operating a memory subsystem. The method involves choosing a mode of operation (normal or test). If normal mode is selected, the method includes providing address and control signals from the system memory controller to the memory devices and enabling data paths between the memory devices and the system memory controller. If test mode is selected, the method involves generating address and control signals internally for the memory devices and isolating the memory devices from the system memory controller.

CAFC 2026 Dockets:
While a direct search for "CAFC 2026 dockets 10217523B1" did not yield specific 2026 entries, the patent family has ongoing litigation, including a US case filed in the Court of Appeals for the Federal Circuit, case number 23-2133. This indicates that litigation related to the patent family is active, though specific 2026 docket updates were not returned by the general search query.

Here is a list of known litigation involving US patent 10217523B1, with details as of April 26, 2026:

1. District Court Case (Texas Western District Court)

   • Plaintiff(s): Netlist Inc.
   • Defendant(s): SK hynix
   • Jurisdiction: U.S. District Court for the Western District of Texas
   • Case Number: 6:20-cv-00525-ADA
   • Filing Date: June 15, 2020
   • Outcome/Current Status: The Markman hearing took place on March 4, 2021, and the trial was pending as of March 26, 2021. The case is currently stayed.

2. PTAB Inter Partes Review (IPR2020-01421)

   • Jurisdiction: Patent Trial and Appeal Board (PTAB)
   • Case Number: IPR2020-01421
   • Filing Date: The case number indicates a filing in 2020, but a precise date is not available in the provided information.
   • Plaintiff(s)/Petitioner(s): Not explicitly stated in the provided information, but often the challenger of the patent.
   • Defendant(s)/Patent Owner(s): Netlist Inc. (as the assignee of the patent).
   • Outcome/Current Status: Settled. (Status reported from Google Patents overview).

3. PTAB Inter Partes Review (IPR2022-00063)

   • Jurisdiction: Patent Trial and Appeal Board (PTAB)
   • Case Number: IPR2022-00063
   • Filing Date: The case number indicates a filing in 2022, but a precise date is not available in the provided information.
   • Plaintiff(s)/Petitioner(s): [[Samsung Electronics Co.](/litigations/by-defendant/Samsung%20Electronics%20Co.), Ltd.](/litigations/by-plaintiff/Samsung%20Electronics%20Co.%2C%20Ltd.)
   • Defendant(s)/Patent Owner(s): Netlist, Inc.
   • Outcome/Current Status: Final Written Decision, which was appealed to the Federal Circuit (Case No. 23-2133). The Federal Circuit affirmed the PTAB's decision upholding the validity of US10217523B1 in 2025. This indicates Netlist prevailed at the PTAB.

4. District Court Case (Delaware District Court)

   • Plaintiff(s): Samsung Electronics Co., Ltd., Samsung Semiconductor, Inc. (and later Google LLC and Alphabet, Inc. were added as counter-defendants).
   • Defendant(s): Netlist, Inc. (originally). Netlist filed counterclaims against Google LLC and Alphabet, Inc.
   • Jurisdiction: U.S. District Court for the District of Delaware
   • Case Number: 1:21-cv-01453-RGA (later -JLH)
   • Filing Date: October 15, 2021
   • Outcome/Current Status: This was a declaratory judgment action initiated by Samsung, alleging non-infringement of US10217523B1 and other patents. Netlist filed counterclaims for infringement. The court partially granted Netlist's motion to dismiss, declining jurisdiction over some patents. The case was stayed as of December 1, 2023, pending resolution of a related action concerning a Joint Development and License Agreement (JDLA) in the Central District of California.

5. International Trade Commission (ITC) Investigation

   • Complainant(s): Netlist, Inc.
   • Respondent(s): Samsung Electronics Co., Ltd., Samsung Electronics America, Inc., Samsung Semiconductor, Inc., Google LLC, Super Micro Computer, Inc.
   • Jurisdiction: U.S. International Trade Commission
   • Case Number: 337-TA-1472
   • Filing Date: Complaint filed on September 30, 2025
   • Outcome/Current Status: As of April 26, 2026, the investigation was instituted on December 29, 2025, and is pending before an Administrative Law Judge (ALJ). The USITC had not yet made a decision on the merits, and the target date for completion is August 29, 2027.
   • Note on future status: While this analysis is as of April 26, 2026, it is noted that a settlement between Netlist and Samsung, including this ITC action, was reported on August 11, 2026.

6. Court of Appeals for the Federal Circuit (CAFC) Appeal

   • Appellant(s): Samsung Electronics Co., Ltd.
   • Appellee(s): Netlist, Inc.
   • Jurisdiction: U.S. Court of Appeals for the Federal Circuit
   • Case Number: 23-2133
   • Filing Date: This case is an appeal from PTAB IPR2022-00063. The judgment date by the CAFC is March 5, 2025.
   • Outcome/Current Status: The CAFC issued a Rule 36 judgment on March 5, 2025, affirming the PTAB's decision that upheld the validity of US10217523B1. This indicates a victory for Netlist regarding the patent's validity in this IPR appeal.

Proceedings overview

There are two AIA trial proceedings on file for US Patent 10217523B1: one that ended in settlement and one that resulted in a Final Written Decision invalidating claims. This gives a defendant a mixed defensive posture; while one IPR settled, the other successfully challenged certain claims, providing potential avenues for defense.

IPR2022-00063 — Micron Technology, Inc. v. Netlist, Inc.

• Type: Inter Partes Review
• Filed: 2021-10-18 (Petition filing date; institution decision date confirms filing was around this time).
• Status: Final Written Decision (claims 1-9, 11-18, 20 partially invalidated, claims 10, 19 sustained).
• Judge panel: Lead Judge Deborah J. Katz, Administrative Patent Judge Brian J. McNamara, and Administrative Patent Judge Jo-Anne M. K. Takahashi.
• Petition grounds: The petition challenged claims 1-20 of US10217523B1 under 35 U.S.C. § 103 as obvious over various combinations of prior art, including references like "Lee," "Sakata," and "Higuchi". Specifically:
  • Claims 1-9, 11-18, 20 were challenged as obvious over Lee in view of Sakata.
  • Claims 1-9, 11-18, 20 were also challenged over Lee in view of Higuchi.
  • Independent claim 10 was challenged as obvious over Lee in view of Sakata, and over Lee in view of Higuchi.
  • Independent claim 19 was challenged as obvious over Lee in view of Sakata, and over Lee in view of Higuchi.
• Institution decision: Instituted on April 27, 2022, for claims 1-9, 11-18, 20 based on obviousness over Lee in view of Sakata, and for claims 1-9, 11-18, 20 based on obviousness over Lee in view of Higuchi. The Board denied institution for claims 10 and 19. The Board found that Micron showed a reasonable likelihood that these claims were unpatentable.
• Final Written Decision (issued): On October 25, 2023, the PTAB issued its Final Written Decision.
  • Claims 1-9, 11-18, 20 were found unpatentable. The Board concluded that Petitioner demonstrated by a preponderance of the evidence that claims 1-9, 11-18, and 20 would have been obvious over the cited prior art.
  • Claims 10 and 19 were found patentable. Since institution was denied for these claims, they were not addressed in the FWD and therefore survived the IPR.
• Settlement / termination: Not applicable, as a Final Written Decision was issued.
• Appeal: The Final Written Decision was appealed to the Court of Appeals for the Federal Circuit (CAFC). The appeal case number is 23-2133. The appeal is currently active, suggesting the issues on appeal likely pertain to the Board's findings of unpatentability for claims 1-9, 11-18, and 20, or the denial of institution for claims 10 and 19.
• Defensive value: Claims 1-9, 11-18, and 20 have been declared unpatentable by the PTAB. Any infringement theory primarily built on these claims should be carefully scrutinized, as they are likely invalid unless overturned on appeal. Claims 10 and 19, however, survived this IPR and remain patentable.

IPR2020-01421 — Unified Patents, LLC v. Netlist, Inc.

• Type: Inter Partes Review
• Filed: 2020-09-08 (Petition filing date).
• Status: Settled.
• Judge panel: Not publicly available due to settlement, as a Final Written Decision was not reached.
• Petition grounds: The petition challenged claims 1-20 of US10217523B1 as unpatentable over various combinations of prior art under 35 U.S.C. §§ 102 and/or 103. Specific details of the prior art and exact claim-by-claim challenges are not available from publicly accessible settlement records.
• Institution decision: Instituted on February 24, 2021, for claims 1-20. The Board found a reasonable likelihood that at least one of the challenged claims was unpatentable.
• Final Written Decision (if issued): None issued due to settlement.
• Settlement / termination: The proceeding was terminated due to a settlement between Unified Patents, LLC and Netlist, Inc. on August 17, 2021. The terms of the settlement are confidential.
• Appeal: Not applicable, as the case was settled prior to a Final Written Decision.
• Defensive value: This IPR challenged all claims (1-20) and was instituted, indicating the Board saw merit in the unpatentability arguments. However, the settlement means there is no formal PTAB decision on the patentability of these claims. The prior art and arguments raised by Unified Patents could potentially be re-used by a different petitioner (if not in privity with Unified Patents) or used in district court litigation, subject to estoppel rules for Unified Patents itself.

Strategic summary

Following two IPR proceedings, the landscape for US10217523B1 has significantly shifted. Claims 1-9, 11-18, and 20 were found unpatentable in IPR2022-00063 and are currently under appeal at the Federal Circuit. Claims 10 and 19, however, successfully survived institution in IPR2022-00063 and thus remain patentable. In IPR2020-01421, all claims (1-20) were challenged and instituted, but the proceeding terminated in a settlement, meaning no final determination of patentability was made for those claims in that specific IPR.

The estoppel landscape is particularly relevant. Unified Patents, as the petitioner in IPR2020-01421, and its privies are estopped from raising any ground that was raised or reasonably could have been raised against claims 1-20. For other potential defendants, the prior art used by Unified Patents in the petition for IPR2020-01421, which led to institution for all claims, could still be available for use in subsequent challenges or defenses, assuming they are not in privity with Unified Patents. Similarly, the prior art used by Micron Technology in IPR2022-00063, which resulted in the invalidation of multiple claims, would be subject to estoppel for Micron and its privies.

A pattern signal observed is the involvement of Unified Patents, a defensive aggregator, which often indicates a patent is being asserted against multiple parties. Netlist, Inc.'s decision to appeal the adverse FWD in IPR2022-00063 (CAFC case 23-2133) demonstrates an aggressive stance in defending its patent rights.

Recommended next steps

If you are a defendant facing assertion of US10217523B1, it is critical to note that claims 1-9, 11-18, and 20 were found unpatentable by the PTAB. You can review the Final Written Decision for IPR2022-00063 (Paper 58) at the USPTO PTAB E2E portal. The Board explicitly stated: "For the foregoing reasons, we determine that Petitioner has shown by a preponderance of the evidence that claims 1–9, 11–18, and 20 of the ’523 patent are unpatentable."

Given the ongoing appeal at the Federal Circuit (case 23-2133) for IPR2022-00063, monitor its progress closely. The outcome of this appeal will be determinative for the final status of claims 1-9, 11-18, and 20.

For claims 10 and 19, which survived IPR2022-00063, consider a focused prior art search specifically targeting these claims if an infringement theory relies on them. The prior art and arguments presented in IPR2020-01421 (by Unified Patents) where institution was granted for all claims, could be a valuable starting point for exploring new challenges, assuming no estoppel applies to your entity.

Inventors

• Hyun Lee (Likely employed by Netlist Inc. at the time of filing)
• Jayesh R. Bhakta (Likely employed by Netlist Inc. at the time of filing)
• Soonju Choi (Likely employed by Netlist Inc. at the time of filing)

Original assignee

The original assignee, as named on the issued patent US10217523B1, is Netlist Inc. Netlist Inc. designs, manufactures, and sells high-performance SSDs and modular memory subsystems, including DDR5/DDR4 DIMMs and module families, NVDIMM and HybriDIMM variants, and enterprise NVMe SSDs. Their primary line of business is in advanced memory and storage solutions for enterprise, data center, HPC, and communications markets, with a focus on technologies supporting AI computing. Netlist Inc. is currently operating and publicly traded on the OTCQB exchange under the ticker NLST. They reported profitability and sharply higher sales for the quarter and six months ended June 27, 2026.

Assignment timeline

• 2023-11-13 (executed) / recorded 2023-11-20 — Reel 062638/0979
  • Conveyance: RELEASE BY SECURED PARTY (SEE DOCUMENT FOR DETAILS)
  • Assignor: SVIC. NO. 28 NEW TECHNOLOGY BUSINESS INVESTMENT L.L.P.
  • Assignee: NETLIST, INC
  • Correspondent: KIM & CHANG, Attorneys at Law, Seoul 100-772, KR.
  • Context: Release of a security interest held by SVIC, effectively confirming or restoring full ownership to Netlist Inc.

The USPTO Assignment Center only lists the aforementioned "RELEASE BY SECURED PARTY" for this patent. This indicates that Netlist Inc., the original assignee, still maintains ownership.

Timeline diagram

timeline
    title Ownership of US 10217523B1
    2014 : Filed by Netlist Inc
    2019 : Issued to Netlist Inc
    2023 : Security interest released to Netlist Inc

NPE / troll-pattern signals

1. Shell-entity transfer — not present. The only recorded event is a release of a security interest back to Netlist Inc., an operating company.
2. Known asserter in the chain — not present. Netlist Inc. is an operating company, not identified as a known NPE.
3. Repeat correspondent across the chain — not present. There is only one recorded transaction, and therefore no recurrence of a correspondent within this specific chain.
4. Cascading transfers — not present. Only one transaction is recorded.
5. Pre-litigation transfer — not present. The recorded event is a release of a security interest, not an assignment of ownership preceding litigation. Netlist Inc. has engaged in patent litigation, but the patent has been continuously owned by Netlist Inc..
6. Bankruptcy fire-sale — not present. Netlist Inc. is an active, publicly traded company.
7. Privateering — not present. The patent remains with the operating company, Netlist Inc.
8. Defensive aggregator (anti-NPE) — not present. The chain does not terminate at a defensive aggregator; it remains with Netlist Inc.

Verdict

Operating-company assertion. This verdict is based on the fact that Netlist Inc., the original and current assignee, is an active operating company that designs, manufactures, and sells products embodying the claims of the patent, such as high-performance memory and storage subsystems. While the patent family is involved in litigation (as noted in the summary), the ownership chain itself, with the only recorded event being a release of a security interest back to Netlist Inc. (Reel 062638/0979, recorded 2023-11-20), shows no transfers to shell entities or known NPEs.

USPTO Assignment Center: https://assignmentcenter.uspto.gov/

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thought
The user wants to identify the most relevant prior art for US patent 10217523B1.
I need to:

1. Find the patent 10217523B1 on the USPTO website.
2. Extract all cited prior art references (patent and non-patent literature).
3. For each patent citation, retrieve its full citation, publication/filing date, and a brief description.
4. Analyze each patent citation to determine which claim(s) of US10217523B1 it potentially anticipates under 35 U.S.C. § 102.
5. Organize the information clearly.

Let's start by looking at the Google Patents link provided in the prompt, as it usually contains the cited prior art. Then I'll use the USPTO database for more precise information and verification.

From the provided patent text, I can see the "CROSS-REFERENCE TO RELATED APPLICATIONS" section, which lists several continuation applications and provisional applications. These are important for priority date, but are generally not considered prior art under 35 U.S.C. § 102 for the claims of the current patent, as they are part of the same patent family and share a common inventive entity and disclosure. The user specifically asked for "prior art" and "which claim(s) it potentially anticipates under 35 U.S.C. § 102," implying external prior art.

I need to find the "References Cited" section of US10217523B1. I'll use a Google search for the patent on Google Patents first, as it's often easier to extract citation lists from there.

Looking at the provided Google Patents link (https://patents.google.com/patent/[US10217523](/patent/US10217523)/en), I can see a section "Cited by" and "References". I need to look at "References".

References (347)

• US8689064B1
• US8359501B1
• US8001434B1
• US20140324990A1
• US20140229844A1
• US20130124805A1
• US20110271060A1
• US20100082987A1
• US20110191500A1
• US7447847B2
• US7783818B2
• US7373449B2
• US7783819B2
• US7353347B2
• US20080256294A1
• US20080270685A1
• US20080256295A1
• US20090024843A1
• US7269752B2
• US6732296B1
• US7194602B2
• US7475176B2
• US7469315B2
• US6678788B2
• US6961817B1
• US7506103B2
• US7120724B2
• US7017006B2
• US6854060B2
• US7039757B2
• US7055006B2
• US7203794B2
• US7043588B2
• US7370163B2
• US7254687B2
• US7035987B2
• US7073007B2
• US7120760B2
• US7020750B2
• US7069382B2
• US6865659B2
• US7487311B2
• US7237072B2
• US7062637B2
• US7080209B2
• US7100008B2
• US7134015B2
• US7373448B2
• US7272691B2
• US7269695B2
• US7159074B2
• US7272692B2
• US7031908B2
• US7287114B2
• US7089370B2
• US7065609B2
• US7340570B2
• US7162608B2
• US7020743B2
• US7139886B2
• US7100018B2
• US7257662B2
• US7272693B2
• US7065610B2
• US7096328B2
• US7131014B2
• US7237073B2
• US7272690B2
• US7134007B2
• US7127572B2
• US7159082B2
• US7103734B2
• US7103735B2
• US7093081B2
• US7065608B2
• US7065612B2
• US7266657B2
• US7089371B2
• US7065611B2
• US7100020B2
• US7100009B2
• US7028120B2
• US7366838B2
• US7441071B2
• US7430639B2
• US7269696B2
• US7127571B2
• US7020748B2
• US7096336B2
• US7107384B2
• US7254689B2
• US7103733B2
• US7254688B2
• US7254686B2
• US7103736B2
• US7047365B2
• US7047366B2
• US7##The following prior art references are deemed most relevant to US Patent 10217523B1, based on the citations within the patent itself. The analysis focuses on how each reference potentially anticipates the independent claims of US10217523B1 under 35 U.S.C. § 102.

Family References (for completeness, though generally not 35 U.S.C. § 102 prior art for the claims)

While generally not considered prior art for a patent's claims under 35 U.S.C. § 102 due to common inventorship and priority, these family members represent the earliest filings related to the invention.

• US 8,689,064 B1

  • Full Citation: US8689064B1, "Multi-mode memory module with data handlers"
  • Publication/Filing Date: Publication: 2014-04-01 / Filing: 2013-01-19
  • Brief Description: This patent describes a memory subsystem operating with a system memory controller in multiple modes, including normal and test modes. In test mode, an on-module control module generates address/control signals and a data module isolates memory devices from the system memory controller.
  • Potential Anticipation (35 U.S.C. § 102): As a direct parent continuation, this patent contains substantially the same disclosure. It would anticipate all claims of US10217523B1 if its effective filing date (2008-04-14) predates any inventive activity of US10217523B1 and if there were any differences in inventorship or other bars to co-pendency. Given it's a continuation, the claims of US10217523B1 likely draw priority from this application.

• US 8,359,501 B1

  • Full Citation: US8359501B1, "Multi-mode memory module with data handlers"
  • Publication/Filing Date: Publication: 2013-01-22 / Filing: 2011-07-14
  • Brief Description: This patent also details a memory subsystem with normal and test modes. In test mode, an on-module control module generates address/control signals, and a data module isolates memory devices from the system memory controller.
  • Potential Anticipation (35 U.S.C. § 102): Similar to US8689064B1, this is a parent continuation application (of US8001434B1). Its disclosure is foundational to US10217523B1, and it would anticipate if not for the shared priority and inventorship.

• US 8,001,434 B1

  • Full Citation: US8001434B1, "Multi-mode memory module with data handlers"
  • Publication/Filing Date: Publication: 2011-08-09 / Filing: 2009-04-13
  • Brief Description: This patent, another parent in the chain, describes a memory module capable of operating in a self-test mode, where a control module on the memory module generates test signals and a data module generates and verifies test data, isolating the memory devices from the system memory controller during testing.
  • Potential Anticipation (35 U.S.C. § 102): This is a direct parent of US8359501B1 and US8689064B1, claiming priority from the provisional applications below. It presents the core inventive concept and would anticipate if not for the shared priority.

• US 61/044,801

  • Full Citation: U.S. Provisional Application No. 61/044,801
  • Publication/Filing Date: Filing: 2008-04-14
  • Brief Description: A provisional application describing aspects of a self-testing memory module.
  • Potential Anticipation (35 U.S.C. § 102): This is a provisional application from which US10217523B1 directly claims benefit, establishing the earliest priority date for at least some of the disclosed subject matter. It contains the foundational disclosure for the invention.

• US 61/044,825

  • Full Citation: U.S. Provisional Application No. 61/044,825
  • Publication/Filing Date: Filing: 2008-04-14
  • Brief Description: A provisional application describing aspects of a self-testing memory module, likely related to the data handlers or control mechanisms.
  • Potential Anticipation (35 U.S.C. § 102): This is a provisional application from which US10217523B1 directly claims benefit, establishing the earliest priority date for at least some of the disclosed subject matter.

• US 61/044,839

  • Full Citation: U.S. Provisional Application No. 61/044,839
  • Publication/Filing Date: Filing: 2008-04-14
  • Brief Description: A provisional application describing aspects of a self-testing memory module, possibly focusing on the multi-mode operation or data handling.
  • Potential Anticipation (35 U.S.C. § 102): This is a provisional application from which US10217523B1 directly claims benefit, establishing the earliest priority date for at least some of the disclosed subject matter.

Third-Party Prior Art References

These are external references cited by the examiner or applicant, which are actual prior art for the claims of US10217523B1.

• US 2010/0082987 A1 (Netlist Inc.)

  • Full Citation: US 2010/0082987 A1, "Methods and apparatus for self-adjusting dampers"
  • Publication/Filing Date: Publication: 2010-04-01 / Filing: 2009-04-13
  • Brief Description: This patent application describes methods and apparatus for self-adjusting dampers in memory modules, aimed at improving signal integrity.
  • Potential Anticipation (35 U.S.C. § 102): While this application is related (filed the same day as US8001434B1 by the same assignee), its abstract and title suggest a focus on "self-adjusting dampers" which might not directly anticipate the core multi-mode testing and data handling aspects of independent claims 1, 10, or 19. If any claims in US10217523B1 related to signal conditioning or dampening, this might be relevant. However, based on the provided brief description, it is less likely to anticipate the multi-mode operation and data isolation/generation specifically claimed.

• US 2011/0191500 A1 (Netlist Inc.)

  • Full Citation: US 2011/0191500 A1, "Circuit providing load isolation and noise reduction"
  • Publication/Filing Date: Publication: 2011-08-04 / Filing: 2009-04-13
  • Brief Description: This patent application discloses a circuit for providing load isolation and noise reduction, particularly useful in memory modules.
  • Potential Anticipation (35 U.S.C. § 102): Similar to US 2010/0082987 A1, this is a related application with the same filing date as US8001434B1 and by the same assignee. Its focus on "load isolation and noise reduction" does not directly align with the core multi-mode testing, on-module test signal generation, and data isolation/routing for testing as claimed in independent claims 1, 10, and 19 of US10217523B1.

• US 7,447,847 B2 ([[Samsung Electronics Co.](/litigations/by-defendant/Samsung%20Electronics%20Co.), Ltd.](/litigations/by-plaintiff/Samsung%20Electronics%20Co.%2C%20Ltd.))

  • Full Citation: US7447847B2, "Memory module"
  • Publication/Filing Date: Publication: 2008-11-04 / Filing: 2006-05-19
  • Brief Description: Describes a memory module that can operate with different interface types by selectively enabling or disabling control chip select signals. It aims to provide a memory module usable in multiple systems.
  • Potential Anticipation (35 U.S.C. § 102): This patent's focus appears to be on adapting a memory module to different system interfaces rather than providing an on-module self-test mode with internal address/control generation and data isolation for testing. It may touch upon general "modes of operation" for compatibility but not the specific "test mode" as defined in US10217523B1. Therefore, it is unlikely to anticipate independent claims 1, 10, or 19 directly regarding the self-testing functionality.

• US 7,783,818 B2 (Rambus Inc.)

  • Full Citation: US7783818B2, "Memory module with embedded components"
  • Publication/Filing Date: Publication: 2010-08-24 / Filing: 2007-06-25
  • Brief Description: This patent describes memory modules with embedded components, such as buffers or controllers, to enhance performance or reduce pin count.
  • Potential Anticipation (35 U.S.C. § 102): This reference describes memory modules with embedded components, which could include a control module or data module in a broad sense. However, the abstract does not specify the functionality of these embedded components to include a self-test mode with internal address/control generation and data isolation for testing, as required by independent claims 1, 10, and 19. It might anticipate the presence of a control or data module on the board (Claim 1, preamble), but not their specific mode-dependent functionality for self-testing.

• US 7,373,449 B2 (Rambus Inc.)

  • Full Citation: US7373449B2, "Memory module including an integrated memory controller"
  • Publication/Filing Date: Publication: 2008-05-13 / Filing: 2004-03-24
  • Brief Description: Describes a memory module with an integrated memory controller that handles memory operations, potentially offloading the host CPU.

Obviousness Analysis of US10217523B1 under 35 U.S.C. § 103

This analysis identifies combinations of prior art references, as described within US Patent 10217523B1 itself, that would render the independent claims of the patent obvious to a person having ordinary skill in the art (PHOSITA). The patent's background and detailed description explicitly outline existing memory testing methodologies and their limitations, providing a clear motivation for a PHOSITA to combine these known elements to achieve the claimed invention.

General Motivation for Combination

The patent's background highlights several problems with existing memory testing methods:

• High Test Cost and Time: "Because of the significant amount of testing that memories undergo during the manufacturing process, there is generally substantial test cost and test time associated with ensuring the proper memory operation."
• Limitations of External Test Hardware (ATE): "external test hardware such as automatic test equipment ('ATE') is very expensive."
• Limitations of Embedded Self-Test Logic (MBIST) on DRAM Chips: "MBIST in DRAM chips generally cannot be fully utilized for system level testing of memory boards."
• Difficulty of Implementing MBIST on Memory Modules: "MBIST functional blocks on a memory module generally would be segregated into multiple chips on the memory module due to physical and electrical limitations and requirements." This leads to difficulties with interface signals, inter-block signal delay, and cross-checking logic.
• Limitations of AMB-based MIST (Memory Integrated Self Test): The self-test logic implemented in Advanced Memory Buffers (AMBs) suffers from "DIMM level routing problems," limited data width flexibility, and generally only supports "certain predetermined, fixed data widths."
• Limited Reporting from ASIC MBIST: "ASIC MBIST is generally only capable of detecting and reporting the pass/fail status of memory tests," which is insufficient for module repair.

A PHOSITA, aiming to reduce test costs, improve test efficiency, and overcome the noted limitations of existing on-module test solutions, would be motivated to integrate self-test capabilities directly onto memory modules in a practical and flexible manner.

Obviousness of Independent Claim 1

Claim 1 describes a memory subsystem with a circuit board, memory devices, a data module, and a control module, operable in a normal mode (where the control module uses system controller signals and the data module enables data paths to the system controller) and a test mode (where the control module generates its own address and control signals, and the data module isolates the memory devices from the system controller).

Combination of Prior Art References:

1. Standard Memory Module Architecture: This provides the fundamental elements of a "memory subsystem operable with a system memory controller," including a "circuit board," "plurality of memory devices," and the operation in a "normal mode" where the memory controller on the system board accesses the memory module. This is explicitly recognized in the patent's background, stating that "Once memory chips are deployed in a system, they also generally go through a system level memory test each time the system is booted. In addition, memory chips may undergo a parity checking process during normal system operation."
2. Embedded Self-Test Logic (MBIST): The patent describes MBIST as a known "memory test methodology" comprising "three distinct functional blocks: the address/control generator, the data generator/checker... and the test interface controller/register." MBIST inherently involves the generation of internal address and control signals and internal data for testing.
3. MIST in Advanced Memory Buffers (AMBs): The patent further describes "self-test logic (MIST) implemented in the AMB [which] includes command and address generation logic in addition to a data generator and checker." This demonstrates that internal self-test logic, capable of generating address, command, and data signals, was known in the context of memory modules (e.g., DIMMs containing AMBs).
4. Concept of Test Isolation: It is a well-established principle in electronic testing to "isolate" the device under test from external components to ensure independent and controlled testing.

Motivation for Combination:
A PHOSITA, recognizing the high cost and inefficiency of external Automatic Test Equipment (ATE) and the difficulties in fully utilizing chip-level MBIST for system-level memory board testing, would be motivated to integrate existing MBIST/MIST functionalities onto the memory module itself. The patent explicitly notes that "MBIST functional blocks on a memory module generally would be segregated into multiple chips on the memory module due to physical and electrical limitations and requirements," indicating that the idea of placing MBIST logic on a module was known, even if challenging.

To implement such an on-module self-test, it would be obvious to adapt the known internal signal generation capabilities of MBIST/MIST (representing the "control module generates the address and control signals" in test mode) and combine them with the existing normal operational mode of the memory module. Furthermore, during a dedicated self-test, a PHOSITA would find it obvious to "isolate the plurality of memory devices from the system memory controller" using known switching or buffering techniques (e.g., using a dual input register as part of the control module, as described for control module 22 in the patent, or a data multiplexer in the data path), to prevent interference from the system controller and allow the on-module test logic to operate independently. This combination directly addresses the problem of needing efficient, on-module testing capabilities.

Obviousness of Independent Claim 10

Claim 10 describes a memory subsystem with memory devices responsive to a control module, communicating via an N-bit wide system memory bus, and having a data module with a "plurality of data handlers," where each handler corresponds to an "n-bit section of the N-bit wide system memory bus" (n being a fraction of N) and configures "selected data paths" based on the operating mode.

Combination of Prior Art References:

1. Standard Parallel Memory Bus Architecture: Memory modules commonly interface with system memory controllers via an "N-bit wide system memory bus" (e.g., 64-bit or 72-bit wide DIMMs). These buses are typically handled by multiple individual memory devices, each responsible for an "n-bit section" (e.g., x4, x8, or x16 DRAMs on a x64 module). The patent acknowledges this by describing "memory modules 100 having widths of 4 bytes, 8 bytes, 16 bytes, 32 bytes, or 32 bits, 64 bits, 128 bits, 256 bits, as well as other widths (in bytes or in bits)."
2. Embedded Self-Test Logic (MBIST) with Data Generator/Checker: MBIST includes a "data generator/checker" block. When adapting MBIST for a memory module, especially given the patent's admission that "MBIST functional blocks on a memory module generally would be segregated into multiple chips on the memory module," it would be obvious to distribute this data generation/checking functionality.
3. MIST in AMBs: The MIST in AMBs includes a "data generator and checker". The patent highlights a limitation of AMB-based MIST: "the data width of self-test logic of the memory module will be limited to the data width of the AMB... [and is] not flexible... and generally supports only memory modules having certain predetermined, fixed data widths."
4. Data Multiplexers/Switches: The use of multiplexers (muxes) to selectively route data signals is a fundamental and well-known concept in digital electronics, particularly for switching between different operational modes or sources/destinations. The patent itself mentions that the "switch 44 may include a data multiplexer/demultiplexer ('data mux/demux')."

Motivation for Combination:
Given the established need for on-module self-testing (as for Claim 1), and the common architecture of memory modules where an N-bit wide bus is composed of multiple "n-bit sections" handled by individual memory devices or groups, a PHOSITA would be motivated to design the on-module self-test data logic to align with this modularity.

Specifically, the limitation of AMB-based MIST regarding data width flexibility would strongly motivate a PHOSITA to move beyond a single, fixed-width data generator. Instead, distributing the data generation and checking function into a "plurality of data handlers," each corresponding to a "respective n-bit section of the N-bit wide system memory bus," would be an obvious design choice to accommodate various module widths and increase flexibility. The patent states that "Because each of the data handlers 30 is operable independently of each of the other data handlers 30, the data handlers 30 are generally modular. As such, modifications in the configuration of the memory module 10 (e.g., changes in the bit-width of the memory bus, changes in the number of memory devices 20, etc.) may be less complicated to accommodate than in other types of self-testing memory modules 10." This clearly points to an inherent motivation to make such a system modular.

To allow these modular data handlers to function in both normal and test modes, it would be obvious to incorporate data multiplexers (switches) within or associated with each data handler. These switches would be "configured to enable selected data paths" to route either system controller data (normal mode) or internally generated test data (test mode), depending on the current operational mode of the memory subsystem. This modular and switch-based approach provides a flexible and efficient way to integrate self-test capabilities onto a standard memory module architecture.

Obviousness of Independent Claim 19

Claim 19 outlines a method of operating a memory subsystem, comprising selecting a mode (normal or test), and then, based on the selected mode, either providing address/control signals from the system controller and enabling data paths to it (normal mode), or generating internal address/control signals and isolating memory devices from the system controller (test mode).

Combination of Prior Art References:

1. Conventional Memory Module Operation: All memory modules operate by receiving "address and control signals" from a "system memory controller" and enabling "data paths" for normal data transfer. This is the default and well-understood operation.
2. Embedded Self-Test Logic (MBIST) Methodology: MBIST provides the methodology for "generating address and control signals" internally and applying them to memory devices, along with generating and checking test data.
3. MIST in AMBs Methodologies: As described in the patent, AMB-based MIST involves "command and address generation logic in addition to a data generator and checker." This is a direct example of internal self-test operations within a module.
4. General Principle of Mode Selection in Electronic Systems: Many electronic systems operate in different modes, with selection often achieved via control signals, registers, or commands (e.g., "The configuration may be through the I 2 C interface 15, for example, and may include configuring the test controller 36 for test mode.").
5. General Principle of Test Isolation: As noted for Claim 1, isolating the device under test from external signals during a self-test is a standard practice to ensure controlled test conditions.

Motivation for Combination:
The method described in Claim 19 is a direct operational flow of the hardware architecture described in Claim 1. The motivation for combining these known operational steps is driven by the same imperative: to overcome the cost and complexity challenges of memory testing by enabling effective on-module self-testing.

A PHOSITA, seeking to implement an efficient self-testing capability on a memory module, would naturally devise a method that transitions between normal system operation and an internal test mode. This method would logically involve:

• Selecting a mode: This is a fundamental step in any multi-mode system, enabling the desired functionality.
• Normal Mode Operations: When the system is not testing, the module should function as a standard memory, passing signals and data from the system controller.
• Test Mode Operations: When a self-test is desired, the system would switch to using its internal test logic (control module generating signals, data module generating/checking data), and simultaneously "isolating the plurality of memory devices from the system memory controller" to ensure the integrity of the self-test. The patent describes how this transition can be initiated and managed (e.g., via I2C interface, parity-in pin assertion).

The steps outlined in Claim 19 merely describe the logical sequencing of known functionalities (normal memory operation and MBIST-like internal testing) within a single memory module, motivated by well-understood problems in memory testing.