Invalidity dossier
US 5033048
Memory selftest method and apparatus same
Current assignee: Hewlett Packard Development Co LP
Added 9/21/2026, 4:03:47 AM
Active provider: DeepSeek · deepseek-flash
Patent summary
Title, assignee, inventors, filing/issue dates, abstract, and a plain-language overview of the claims.
Patent Overview — US 5,033,048 A
Title: Memory selftest method and apparatus same
Source: https://patents.google.com/patent/US5033048/en
Bibliographic data (as supplied): Application US07/525,203; filed 1990-04-19; granted and published 1991-07-16; prior art date (priority) 1988-04-01; legal status "Expired – Lifetime"; anticipated expiration 2008-07-16. Inventors: Donald C. Pierce, Edward H. Utzig, Robert N. Crouse, Noreen Hession, Donald W. Smelser, Hansel A. Collins. Original assignee: Digital Equipment Corp. The listing also shows later reassignments (2002, 2004) and a current assignee of Hewlett Packard Development Co LP; per the operating rules, ownership transfers are not analyzed here, and the listing is described only as it appears in the source.
Purpose and plain-language scope (per the supplied text): The invention relates to an apparatus and method for testing the memory locations of a memory device. The method includes generating each memory address in a predetermined order, generating a predetermined series of data words, storing one data word at each location, reading each data word back, regenerating the series, comparing read-back words with regenerated words, and indicating an error when they differ. In further aspects described, the memory is written with a second series in which each data word is the inverse of the corresponding word in the first series; addresses are generated in pseudo-random order and the data-word series is pseudo-random. A novel linear feedback shift register generates the pseudo-random addresses and is able to generate address zero. An accumulating register stores approximate locations of bad memory sections to aid diagnostic service.
Related application noted: U.S. Pat. No. 4,782,487, issued Nov. 1, 1988, "Memory Test Method and Apparatus," same assignee.
What the excerpt does not establish: It contains only the abstract/definitions, classification entries, figures list, and partial description text—claims are not included in the supplied material. Therefore no claim scope, claim count, or claim language can be verified from this excerpt; specific elements of the described embodiments appear only in the partial description. No independent verification of dates, assignments, or legal status was performed.
Generated 10/1/2026, 10:02:34 PM
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Litigation summary
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Proceedings on file (0)
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PTAB challenges
AIA trial proceedings at the USPTO Patent Trial and Appeal Board — IPR, PGR, and CBM. Petitioners, judge panels, claim-level invalidation outcomes from Final Written Decisions, and Federal Circuit appeals. The single most important defensive datapoint after litigation history.
Assignment history
Inventors, original assignee, and the chain of ownership recorded with the USPTO — including the correspondent attorney who recorded each assignment, since shell-LLC chains often share one repeat-player attorney even when the entity names look unrelated. Surfaces NPE / patent-troll patterns: shell-entity transfers, known asserters in the chain, repeat correspondent fingerprints, pre-litigation assignments, and bankruptcy fire-sales.
Prior art
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Obviousness
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Extensions
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Derivative works
Defensive disclosure: derivative variations of each claim designed to render future incremental improvements obvious or non-novel.