US 5173906

Patent Overview: US5173906A — "Built-in Self Test for Integrated Circuits"

Bibliographic data (as supplied): US Patent 5,173,906 A; application US07/576,646; filed 1990-08-31; priority date 1990-08-31; granted/publication date 1992-12-22; inventor(s) Jeffrey H. Dreibelbis, Erik L. Hedberg, and John G. Petrovick, Jr.; assigned to International Business Machines Corporation (IBM), a corp. of NY. Related priorities listed: EP0472818B1 and JP3190809A/JPH06342040A (both 1991-05-07 foreign filings). Status listed as "Expired – Lifetime" (anticipated expiration 2010-08-31). Classifications include G11C29/12 (BIST arrangements) and G06F11/27 (built-in tests).

Purpose and subject matter: The invention concerns built-in self test (BIST) arrangements fabricated on the integrated circuit chip itself, particularly for testing embedded memory circuits such as SRAMs and DRAMs that are not directly accessible from primary input/output pins. The excerpt states that prior BIST circuits for embedded memories "have heretofore been limited to the provision of deterministic patterns by way of memory arrays that take large amounts of chip area, which is undesirable." The disclosed approach provides an on-chip self-test arrangement including a data pattern generator on the same chip as the VLSI circuit for generating predetermined deterministic test data applied to the circuit's data inputs, a control signal generator for control signals enabling operation on that test data, and a generator for producing expected data, with expected data compared against actual data to produce a pass/fail signal.

Additional stated scope: A further aspect stores the location within the VLSI circuit where a failure occurred, for later use in failure analysis or activation of duplicative logic or memory circuitry. The excerpt also notes test circuitry manufactured directly on chip permitting external testers to invoke a variety of array tests without chip redesign.

What the excerpt does not establish: The excerpt is expressly partial ("Excerpt only"), so claim text is unavailable. It does not reproduce the claims, specification, figures, or references, and does not establish the actual inventive scope, claim limitations, prosecution history, validity, or any post-grant proceedings.

Source: https://patents.google.com/patent/[US5173906](/patent/US5173906)/en