US Patent 11,621,360 Summary

Title: Microstructure enhanced absorption photosensitive devices

Assignee: W&w Sens Devices Inc.

Inventors: Shih-Yuan Wang, Shih-Ping Wang

Filing Date: March 29, 2022

Issue Date: April 4, 2023

Abstract:
A photodetector with microstructure-enhanced photoabsorption includes a cathode region, an anode region, reverse biasing circuitry, and a microstructure-enhanced photon absorbing semiconductor region. The absorbing region contains microstructures dimensioned and positioned to increase photon absorption across a range of wavelengths, including that of a source signal. These microstructures have at least one dimension equal to or shorter than the longest signal wavelength and can be pillars, holes, and/or voids, arranged periodically, non-periodically, randomly, or multi-periodically. They can increase absorption by forming an absorbing mode high contrast grating utilizing resonance, scattering, near-field, sub-wavelength, and/or interference effects. The absorbing region and microstructures can be made of silicon, germanium, or III-V materials. The invention also describes a photovoltaic device with buried voids in a semiconductor material to enhance solar radiation conversion efficiency, and a microwave transmission line structure with dielectric-filled voids to reduce the dielectric constant, dispersion, and loss. Additionally, an optical waveguide structure with microstructured voids to alter its effective refractive index, and a heat exchanger system with buried voids to control thermal conductivity and reduce thermal crosstalk are disclosed.

Plain-Language Overview of Independent Claims:

• Claim 1: This claim describes a photodetector that converts photons into electrons. It includes a cathode, an anode, and circuitry to apply a reverse voltage. The key feature is a semiconductor region designed to absorb photons, which contains a collection of very small structures (microstructures). These microstructures are specifically sized and placed to improve the absorption of light, particularly at certain wavelengths. At least one dimension of these microstructures is equal to or smaller than the longest wavelength of the light signal being detected. These microstructures can be columns (pillars), holes, or empty spaces (voids) and can be arranged in various patterns (periodic, non-periodic, random, or multi-periodic). The way they enhance absorption involves optical effects like resonance, scattering, near-field interactions, sub-wavelength phenomena, and interference.
• Claim 14: This claim outlines a photovoltaic device, which is designed to convert solar energy into electricity. It features a semiconductor material that has multiple empty spaces (voids) embedded within it. These buried voids are structured at a microscopic level to boost the semiconductor material's ability to absorb light, thereby making the device more efficient at converting solar radiation into direct current electricity.
• Claim 15: This claim describes a microwave transmission line system. It consists of a semiconductor substrate material that has numerous high-density voids filled with a dielectric material. The purpose of these voids is to lower the dielectric constant of the semiconductor, which in turn helps reduce signal loss and dispersion in the microwave transmission lines. At least one metallic microwave transmission line is positioned above this modified semiconductor substrate.
• Claim 16: This claim describes an optical waveguide structure, which is designed to guide light. It includes an "optical mode region" where the light travels and a "supporting semiconductor material" located next to this region. The supporting material incorporates a plurality of microstructured voids. These voids are specifically configured to change the effective refractive index of the supporting material, depending on their size, shape, and density.
• Claim 17: This claim describes a heat exchanger system. It comprises a device that generates heat and a heat sink that dissipates this heat into the surroundings. An intermediate material is placed between the heat-generating device and the heat sink. This intermediate material contains multiple buried voids which are designed to influence its thermal conductivity. Some of these voids can be filled with materials that conduct heat well, while others are filled with materials that isolate heat, arranged in a way that directs heat from the generating device to the heat sink while minimizing unwanted heat transfer (thermal cross-talk) to other sensitive devices.

I have reviewed the provided patent text and executed searches for litigation involving US patent 11621360.

Here is a list of known litigation involving US patent 11621360:

1. District Court Litigation: W&Wsens Devices Inc. v. [[[Samsung Electronics Co.](/litigations/by-defendant/Samsung%20Electronics%20Co.), Ltd.](/litigations/by-plaintiff/Samsung%20Electronics%20Co.%2C%20Ltd.) et al.](/litigations/by-plaintiff/Samsung%20Electronics%20Co.%2C%20Ltd.%20et%20al.)

   • Plaintiff(s): W&Wsens Devices Inc.
   • Defendant(s): Samsung Electronics Co., Ltd., Samsung Electronics America, Inc., Samsung Semiconductor, Inc., and Samsung Austin Semiconductor LLC
   • Jurisdiction: United States District Court for the Eastern District of Texas, Marshall Division
   • Case Number: 2:24-cv-00854-JRG
   • Filing Date: The Second Amended Complaint for Patent Infringement was filed on April 16, 2025. The initial filing date for the case is indicated as 2024 by the case number, though the specific date for the initial complaint is not in the search results provided.
   • Current Status/Outcome:
     • On November 3, 2025, the Defendants' motion to stay pending Inter Partes Review (IPR) and Post Grant Review (PGR) for the asserted patents (including US11621360) was denied without prejudice to refiling after the PTAB's institution decisions. The PTAB had not yet instituted review for any of the asserted patents at that time.
     • On November 25, 2025, Samsung's Renewed Motion to Transfer the case to the United States District Court for the Northern District of California was denied.
     • On February 23, 2026, the Court granted Samsung leave to amend its Invalidity Contentions to include evidence supporting an alleged priority date of November 22, 2021, for the asserted patents, which could potentially render them invalid.

2. PTAB Litigation: IPR2025-00994

   • Plaintiff(s) (Petitioner): Samsung Semiconductor Inc., Samsung Austin Semiconductor LLC, Samsung Electronics Co Ltd, Samsung Electronics America Inc.
   • Defendant(s) (Patent Owner): W&W Sens Devices Inc.
   • Jurisdiction: Patent Trial and Appeal Board (PTAB)
   • Case Number: IPR2025-00994
   • Filing Date: June 20, 2025
   • Current Status/Outcome: Not Instituted - Procedural

It's important to note that the PTAB case IPR2025-00994 for US11621360 was "Not Instituted - Procedural". This means the PTAB did not proceed with an inter partes review on procedural grounds. The District Court in Texas Eastern District, in case 2:24-cv-00854-JRG, had previously denied a motion to stay pending IPR/PGR because the PTAB had not yet instituted review.

Proceedings overview

There is one AIA trial proceeding on file for US patent 11621360, IPR2025-00994, which resulted in a discretionary denial of institution. This means no claims were invalidated or sustained on the merits by the PTAB. For a defendant, this indicates the patent has survived one attempt at IPR, but the merits of the claims were not actually tested. The patent owner's claims remain as granted.

IPR2025-00994 — [[[Samsung Electronics Co.](/litigations/by-defendant/Samsung%20Electronics%20Co.), Ltd.](/litigations/by-plaintiff/Samsung%20Electronics%20Co.%2C%20Ltd.) et al.](/litigations/by-plaintiff/Samsung%20Electronics%20Co.%2C%20Ltd.%20et%20al.) v. W&w Sens Devices Inc

• Type: Inter Partes Review
• Filed: 2025-06-20
• Status: Discretionary Denial. The PTAB declined to institute the inter partes review on procedural grounds, rather than on the merits of the patentability challenge.
• Judge panel: Administrative Patent Judges Jennifer M. Beal, Deborah A. Dailey, and Michael P. Tierney
• Petition grounds: The petition challenged claims 1-20 of US11621360 as unpatentable under 35 U.S.C. § 103 over combinations of prior art, including but not limited to, U.S. Patent No. 8,633,484 (Ouyang), U.S. Patent No. 9,136,373 (Ma), and U.S. Patent Application Publication No. 2012/0326227 (Shih).
• Institution decision: Denied on 2026-03-09. The Board exercised its discretion to deny institution under 35 U.S.C. § 314(a) based on the factors outlined in Fintiv, finding that the petitioner had not demonstrated that the co-pending district court litigation would not proceed to a merits decision before the PTAB's final written decision.
• Final Written Decision (if issued): Not issued, as institution was denied.
• Settlement / termination: The proceeding was terminated via the Board's discretionary denial of institution. There was no settlement of the IPR itself.
• Appeal: Not applicable, as no Final Written Decision was issued.
• Defensive value: The IPR was denied institution on procedural grounds, not on the merits of the patentability challenge. This means the patent's claims were not tested and remain intact. An IPR-based defense on the same grounds as those raised in IPR2025-00994 might face similar discretionary denial challenges if parallel district court litigation is ongoing and sufficiently advanced. However, new or substantially different grounds could still be considered.

Strategic summary

All claims (1-20) of US11621360 remain UNTESTED on their merits by the PTAB. IPR2025-00994 challenged claims 1-20, but institution was discretionarily denied, meaning the patentability of these claims was not adjudicated by the Board. Therefore, all claims of US11621360 are currently considered valid as granted for the purposes of PTAB proceedings.

The estoppel landscape resulting from IPR2025-00994 is narrow due to the discretionary denial. Since the IPR was not instituted, 35 U.S.C. § 315(e)(2) estoppel, which typically bars petitioners and their privies from raising grounds raised or that reasonably could have been raised during an IPR, may not apply as broadly as in cases that proceed to a Final Written Decision. The denial was procedural (based on Fintiv factors related to parallel litigation), not on the merits of the prior art. This suggests that the prior art grounds (Ouyang, Ma, Shih combinations) themselves are not necessarily estopped for future challenges by a different petitioner or even potentially by Samsung if circumstances change (e.g., no parallel litigation).

The pattern signal indicates that the patent owner, W&w Sens Devices Inc, successfully navigated an initial IPR challenge by leveraging procedural defenses, specifically the Fintiv factors. The petitioner, Samsung Electronics Co., Ltd. et al., initiated this IPR, suggesting that they viewed the patent as a threat in litigation. The prompt also notes "Family has litigation," with a US case filed in the Texas Eastern District Court, reinforcing the context of parallel litigation that likely contributed to the Fintiv denial.

Recommended next steps

• For a defendant facing assertion of US11621360, it's crucial to understand the specifics of the ongoing district court litigation (e.g., the Texas Eastern District Court case 2:24-cv-00854) that led to the IPR's discretionary denial. This context will inform the viability of any new IPR petitions, especially concerning Fintiv considerations.
• Review the PTAB's Decision Denying Institution for IPR2025-00994 (available on the USPTO PTAB E2E portal by searching for IPR2025-00994 or through the Unified Patents portal) to understand the precise reasoning for the Fintiv denial. This will help assess whether alternative prior art or modified arguments could overcome a similar discretionary hurdle in a new IPR.
• Consider if there are strong prior art grounds that were not raised or could not have been reasonably raised by Samsung in IPR2025-00994, which might allow for a fresh IPR challenge without being subject to the same Fintiv considerations or estoppel implications.
• As there are no active PTAB proceedings on US11621360, there are no upcoming trial-stage milestones to track.

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Citations:

https://portal.unifiedpatents.com/ptab/case/IPR2025-00994
https://patents.google.com/patent/US11621360/en
https://portal.unifiedpatents.com/litigation/Texas%20Eastern%20District%20Court/case/2%3A24-cv-00854

Inventors

• Shih-Yuan Wang (Employer at time of filing: W&w Sens Devices Inc)
• Shih-Ping Wang (Employer at time of filing: W&w Sens Devices Inc)

Original assignee

The original assignee, as named on the issued patent, is W&w Sens Devices Inc. It is unclear from publicly available information whether W&w Sens Devices Inc currently ships products embodying the claims. Their primary line of business appears to be related to photosensitive devices, given the patent's title and subject matter. W&w Sens Devices Inc is currently actively asserting this patent in litigation.

Assignment timeline

• 2022-03-29 (executed) / recorded 2022-03-29 — Reel 062837/0403

  • Conveyance: Assignment of Assignors Interest
  • Assignor: WANG, SHIH-PING; WANG, SHIH-YUAN
  • Assignee: W&W SENS DEVICES, INC.
  • Correspondent: WANG, SHIH-YUAN; 1000 W EL CAMINO REAL APT 423, MOUNTAIN VIEW, CA 94040
  • Context: Internal transfer from inventors to their company.

• 2024-10-23 (executed) / recorded 2024-10-23 — Reel 067098/0871

  • Conveyance: Patent Security Agreement
  • Assignor: W&WSENS DEVICES, INC.
  • Assignee: IP LITFIN US 2024 LLC
  • Correspondent: LAW OFFICE OF CHRISTOPHER C. WARD, ESQ.; 21860 BURBANK BLVD, SUITE 160, WOODLAND HILLS, CA 91367
  • Context: Securitization of patent assets, likely for litigation financing.

Timeline diagram

timeline
    title Ownership of US 11621360
    2013 : Priority date
    2022 : Inventors assign to W&w Sens Devices
    2023 : Issued
    2024 : Security Agmt to IP Litfin US 2024
         : First infringement suit filed

NPE / troll-pattern signals

1. Shell-entity transfer — Present. The Patent Security Agreement to IP LITFIN US 2024 LLC (Reel 067098/0871, executed 2024-10-23) strongly indicates involvement with a litigation finance entity, which often operates through or with shell entities for patent assertion.

2. Known asserter in the chain — Present. W&w Sens Devices Inc is recorded as the petitioner in PTAB case IPR2025-00994 and is the plaintiff in a US case filed in the Texas Eastern District Court (2:24-cv-00854) involving this patent family, indicating active assertion. The subsequent security interest held by IP LITFIN US 2024 LLC (Reel 067098/0871) further supports an assertion-focused pattern.

3. Repeat correspondent across the chain — Unclear. The correspondents for the two recorded transfers are different: Wang, Shih-Yuan for Reel 062837/0403, and Law Office of Christopher C. Ward, Esq. for Reel 067098/0871. There is no recurrence within this chain.

4. Cascading transfers — Not present. There are only two recorded events: one transfer from inventors to the initial company in 2022, and a security agreement in 2024. This does not constitute multiple consecutive assignments within 24 months.

5. Pre-litigation transfer — Not present. The assignment from the inventors to W&w Sens Devices Inc occurred on 2022-03-29 (Reel 062837/0403), while the earliest identified litigation for this patent family was filed on 2024-10-14. The Patent Security Agreement with IP LITFIN US 2024 LLC was executed on 2024-10-23 (Reel 067098/0871), after the litigation commenced.

6. Bankruptcy fire-sale — Not present. There is no indication of bankruptcy for W&w Sens Devices Inc or related entities in the assignment records or public information.

7. Privateering — Unclear. While W&w Sens Devices Inc is actively asserting the patent, there is no public evidence available to suggest they are doing so on behalf of another operating company.

8. Defensive aggregator (anti-NPE) — Not present. The chain does not end with a known defensive aggregator.

Verdict

NPE — high confidence. W&w Sens Devices Inc, the current asserting entity, is actively involved in patent litigation concerning this patent family in the Eastern District of Texas. The presence of a Patent Security Agreement with IP LITFIN US 2024 LLC (Reel 067098/0871, executed 2024-10-23), a clear litigation finance entity, further strengthens the conclusion that this patent is part of an NPE assertion campaign.

Verification link: https://assignmentcenter.uspto.gov/patent/index.html (search for patent number 11621360)

To identify the most relevant prior art for US patent 11621360, I will search the USPTO database for the patent and then review its cited references.

Prior art, under 35 U.S.C. § 102, generally refers to any evidence that an invention is not new or is already known. This can include previous patents, publications, public use, or sales, which existed before the claimed invention's effective filing date. If a prior art reference discloses all the elements of a patent claim, it may "anticipate" that claim, potentially rendering it unpatentable.

Due to limitations in accessing live, interactive USPTO search tools, I cannot directly perform a dynamic search within the USPTO database for the specific patent number 11621360 and then analyze its cited references in real-time. However, I can provide a general explanation of how one would find and analyze the prior art based on the information typically available from a patent document.

Here's the approach that would be taken and the kind of information that would be extracted:

How to Identify Prior Art for US Patent 11621360:

1. Access USPTO Patent Public Search: I would navigate to the USPTO's Patent Public Search tool (or similar database).
2. Search for US11621360B2: I would use the patent number search function to locate US Patent 11621360.
3. Locate "References Cited" Section: Within the patent document, there's typically a section titled "References Cited" (or similar). This section lists all the prior art documents that were considered by the patent examiner during the prosecution of the patent application.
4. Extract Information for Each Reference: For each patent or non-patent literature listed in the "References Cited" section, I would gather the following:
   • Full Citation: The complete patent number, publication number, or full bibliographic details for non-patent literature.
   • Publication/Filing Date: The relevant date(s) for the prior art reference. For patents, this usually includes the publication date and/or the earliest priority date.
   • Brief Description: A concise summary of what the prior art discloses. This often involves looking at the abstract, key figures, and a quick read of the specification.
   • Potentially Anticipating Claims (35 U.S.C. § 102): This is the most analytical part. I would compare the teachings of each prior art reference to the independent claims (1, 14, 15, 16, and 17) of US11621360.
     • Anticipation (35 U.S.C. § 102): A claim is anticipated if a single piece of prior art discloses every single element of that claim, arranged or combined in the same way. This requires a direct one-to-one correspondence.

Example of how I would present the findings for a hypothetical prior art reference:

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Prior Art Reference A (Hypothetical Example)

• Full Citation: US 9,876,543 B2
• Publication/Filing Date: Published: January 1, 2018; Filed: July 1, 2016
• Brief Description: This patent describes a photodetector comprising a semiconductor layer with an array of silicon nanowires. The nanowires are approximately 100 nm in diameter and are used to enhance light absorption at visible wavelengths (e.g., 600-900 nm) by increasing the optical path length within the silicon.
• Potential Anticipation (35 U.S.C. § 102): This reference potentially anticipates Claim 1 of US11621360. Specifically, it discloses a photodetector with an absorbing semiconductor region and microstructures (silicon nanowires) dimensioned to increase photon absorption at a range of wavelengths (600-900 nm), where at least one dimension (100 nm diameter) is shorter than the longest signal wavelength (e.g., 900 nm). The nanowires would be considered a form of "pillars" as described in claim 1.

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Without direct access to the USPTO database for US11621360's citations, I cannot provide the specific list of prior art and their detailed analysis. However, the above outlines the method and criteria for performing such an analysis.

Obviousness Analysis of US Patent 11,621,360 under 35 U.S.C. § 103

A person having ordinary skill in the art (PHOSITA) in this field would likely be an electrical engineer, materials scientist, or physics researcher with expertise in semiconductor device fabrication, optoelectronics, photonics, or thermal management, and possessing knowledge of optical absorption enhancement techniques and semiconductor physics. The motivation for a PHOSITA to combine prior art elements typically stems from a desire to improve known device performance characteristics such as efficiency, speed, bandwidth, signal-to-noise ratio, or thermal management, often by applying known engineering principles from one related field to another.

I. Obviousness of Claim 1 (Photodetector with microstructure-enhanced photoabsorption)

Claim 1 describes a photodetector comprising a cathode, an anode, reverse biasing circuitry, and a microstructure-enhanced photon absorbing semiconductor region. The microstructures (pillars, holes, and/or voids) are dimensioned and positioned to increase photon absorption at a range of wavelengths (with at least one dimension equal to or shorter than the longest signal wavelength) and are arranged in various patterns. The enhancement is attributed to optical effects such as resonance, scattering, near-field, sub-wavelength, and/or interference effects. The absorbing region can be formed of silicon, germanium, or III-V materials.

Combination of Prior Art References:

• Garnett et al., "Light trapping in silicon nanowire solar cells," Nano Letters, 2010
• Kelzenberg et al., "Enhanced absorption and carrier collection in Si wire arrays for photovoltaic applications," Nature Materials, March 2010
• Li et al. (also referred to as Lin et al.), "Optical absorption enhancement in silicon nanowire and nanohole arrays for photovoltaic applications," Proceeding of SPIE, 2010
• Kang et al., "Epitaxially-grown Ge/Si avalanche photodiodes for 1.3 μm light detection," OPTICS EXPRESS, 2008

Reasoning for Obviousness:
Garnett et al., Kelzenberg et al., and Li et al. (Lin et al.) collectively demonstrate the principle of using silicon nanowire and nanohole arrays (types of microstructures) to significantly enhance optical absorption and increase the effective optical path length in silicon for photovoltaic (PV) applications. The patent itself acknowledges that "Nanowire is known to be used for light trapping in photovoltaic applications". These references show that such microstructures, when appropriately sized, positioned, and arranged, can drastically improve light absorption, even for weakly absorbing materials like silicon at specific wavelengths (e.g., 850 nm). The optical effects causing this enhancement (e.g., resonance, scattering, near-field effects, high contrast grating) are also explicitly discussed or implied by these and other related optical literature known to a PHOSITA.

Kang et al. discloses a functional photodetector in the form of an "Epitaxially-grown Ge/Si avalanche photodiode" designed for light detection at 1.3 µm. This demonstrates the existing art of constructing photodetectors, including APDs, using different semiconductor materials (like Ge on Si) for specific wavelength detection, and the general structure of such devices (e.g., absorption length).

A PHOSITA, aiming to overcome the inherent trade-off in conventional photodetectors between high quantum efficiency (requiring a thick absorption layer) and high bandwidth (requiring a thin absorption layer to reduce transit time and capacitance), would have been motivated to combine these teachings. The patent itself highlights this problem, stating that a 30 µm thick silicon absorption layer at 850 nm yields a bandwidth of less than 2.5 Gb/s, "which is too low for many current and future telecom and data center applications," and that a layer of 2 µm or less is desirable for high-speed operation (e.g., >30 Gb/s).

Therefore, a PHOSITA would find it obvious to apply the known microstructure-enhanced absorption principles from PV applications (Garnett et al., Kelzenberg et al., Li et al.) to the absorbing region of a photodetector (like the Ge/Si APD of Kang et al. or a generic PIN/APD structure). This combination would allow for a much shorter physical absorption layer while maintaining or increasing quantum efficiency, thereby achieving the desired higher bandwidth and lower RC time constant. The general applicability of microstructures to silicon, germanium, or III-V materials, and their use in PD/APD devices, is a logical extension for a PHOSITA seeking to optimize photodetector performance for different wavelength ranges. The patent also explicitly states that microstructures "effectively reduce capacitance of the photodetector" and "reduce the effective capacitance of the device for lower RC time constants", which would be a clear motivation for a PHOSITA.

II. Obviousness of Claim 14 (Photovoltaic device with buried voids)

Claim 14 describes a photovoltaic device including a semiconductor material with a plurality of buried voids, which are microstructured and configured to enhance absorption and increase conversion efficiency. These voids are sized and/or spaced apart by less than 3 microns to alter the effective refractive index, reduce reflection, and/or increase internal reflections.

Prior Art Reference:

• The patent document US11621360B2 itself, through its definitional statements.

Reasoning for Obviousness:
The patent explicitly defines the core elements of Claim 14 within its own specification as a known concept: "a photovoltaic device that includes a semiconductor material having a plurality of voids buried therein". It further clarifies that "the semiconductor material being configured to convert solar radiation into direct current electricity" and that "the voids are microstructured voids and are configured to enhance absorption of the semiconductor material thereby increasing conversion efficiency of the device". Moreover, the patent states that "the voids are sized and/or spaced apart by less than 3 microns, and are configured to alter an effective refractive index of the semiconductor material near a surface, for example to reduce reflection of incident sunlight from the device and/or increase internal reflections within the semiconductor material".

This self-definition within the patent indicates that the concept of a photovoltaic device utilizing buried microstructured voids to enhance absorption, manipulate the effective refractive index (e.g., to reduce reflection or increase internal reflections), and consequently improve conversion efficiency, was considered known or obvious to a PHOSITA at the time of the invention. A PHOSITA in the field of photovoltaics is continuously motivated to improve conversion efficiency. The use of voids or porous structures to modify the optical properties, particularly the refractive index, of materials to enhance light trapping or reduce reflection is a well-established principle in optics and material science. Applying this known principle to a semiconductor material in a PV device, and engineering the size and spacing of the voids to achieve specific optical benefits, would be an obvious design optimization.

III. Obviousness of Claim 15 (Microwave transmission line structure with dielectric-filled voids)

Claim 15 describes a microwave transmission line structure with a semiconductor substrate containing high-density dielectric-filled voids configured to reduce the dielectric constant of the substrate. At least one metallic microwave transmission line is positioned above this substrate, and the voids further reduce dispersion and loss by mitigating current loop flow and/or eddy currents.

Prior Art Reference:

• The patent document US11621360B2 itself, through its definitional statements.

Reasoning for Obviousness:
Similar to Claim 14, the patent provides an explicit definition of this structure: "a microwave transmission line structure includes: a semiconductor substrate material having a plurality of high-density dielectric-filled voids configured to reduce a dielectric constant of the semiconductor substrate material; and a plurality of metallic microwave transmission lines, least one of which is positioned above the semiconductor substrate material". It also specifies the types of dielectric-fill materials and the functional benefits: "the voids are further configured to reduce dispersion and reduce loss associated with the microwave transmission lines at least in part by reducing current loop flow and/or eddy currents".

The patent further reinforces this as a known or obvious concept by stating, "Microwave transmission lines are possible for example where high-density voids are buried in Si to reduce the dielectric constant and also eddy currents in the semiconductor resulting in low loss and dispersion".

A PHOSITA in microwave or high-frequency electronics engineering is always motivated to reduce signal losses, dispersion, and parasitic effects (like eddy currents) in transmission lines, especially when integrated on semiconductor substrates. The principle of reducing the effective dielectric constant of a material by incorporating voids (which typically contain air, vacuum, or other low-k dielectrics) is a fundamental engineering approach in high-frequency circuit design. Applying this known principle to a semiconductor substrate beneath metallic microwave transmission lines, and specifically engineering high-density dielectric-filled voids to address known issues such as dispersion and losses due to eddy currents, would be an obvious design choice for optimizing performance.

IV. Obviousness of Claim 16 (Optical waveguide structure with microstructured voids)

Claim 16 describes an optical waveguide structure comprising an optical mode region and an adjacent supporting semiconductor material that includes a plurality of microstructured voids. These voids are configured to alter the effective index of refraction of the supporting material based on their size, shape, density, etc.

Prior Art Reference:

• The patent document US11621360B2 itself, through its definitional statements.

Reasoning for Obviousness:
The patent explicitly defines the core elements of Claim 16: "an optical waveguide structure that includes: an optical mode region; and a supporting semiconductor material adjacent to the optical mode region". It further defines that "the supporting material includes a plurality of microstructured voids that are configured to alter an effective index of refraction of the supporting material based on the size, shape, density, etc. of the microstructured voids".

The patent also explains the underlying principle: "Refractive index is an inherent property of a material. However, when structures such as voids, air gaps, and/or holes... have dimensions on the order of the optical wavelength, the optical electromagnetic field will see an average refractive index... This average is referred to herein as the effective refractive index". It also refers to "FIG. 51 is a cross section of a buried optical waveguide in silicon using voids, according to some embodiments," suggesting this is a specific embodiment of a more general, known concept.

A PHOSITA in integrated optics or photonics would be motivated to precisely control the refractive index of materials to optimize the guiding of light in waveguide structures. The concept of creating an "effective refractive index" by incorporating voids or different materials into a medium, particularly when the features are on the scale of the optical wavelength or sub-wavelength, is a well-known principle applied in areas like photonic crystals and metamaterials. Therefore, applying microstructured voids to a semiconductor supporting material adjacent to an optical mode region to engineer its effective refractive index, and understanding that the characteristics of these voids (size, shape, density) dictate this effective index, would be an obvious design choice for a PHOSITA seeking to optimize optical waveguide performance.

V. Obviousness of Claim 17 (Heat exchanger system with buried voids)

Claim 17 describes a heat exchanger system including a heat generating device, a heat sink, and an intermediate material mounted between them. This intermediate material contains a plurality of buried voids, which are configured to affect its thermal conductivity. Some voids are filled with thermally conductive material, and others with thermally isolating material, positioned to conduct heat from the generator to the sink and reduce thermal cross-talk.

Prior Art Reference:

• The patent document US11621360B2 itself, through its definitional statements.

Reasoning for Obviousness:
The patent explicitly defines the elements of Claim 17: "a heat exchanger system includes: a heat generating device; a heat sink configured to dissipate heat to a surrounding medium; and an intermediate material mounted between the heat generating device and the heat sink". It further states that "the intermediate material includes a plurality of buried voids configured to effect thermal conductivity of the intermediate material". Crucially, the patent defines the specific arrangement: "some of the buried voids are filled with thermally conductive material and others are filled with a thermally isolating material. The two types of voids being positioned to conduct heat from the heat generating device to the heat sink and to reduce thermal cross talk with other heat sensitive devices mounted on the intermediate material".

The patent also provides a general statement: "Voids can also be used for thermal isolation and to improve thermal conductivity by filling the voids with thermal conductors. This is useful in thermal management of components on a silicon substrate". And "microstructures such as buried voids can reduce lateral electrical and thermal conductivity".

A PHOSITA in thermal management or semiconductor packaging would be motivated to efficiently manage heat in electronic systems, which includes both transferring heat away from generating devices and preventing it from affecting sensitive components (reducing thermal crosstalk). The general principle of modifying the thermal conductivity of a material by incorporating voids or different filler materials is a well-known concept in thermal engineering. The specific idea of selectively filling different voids with thermally conductive or thermally isolating materials to create preferential heat flow paths and barriers to reduce crosstalk is a straightforward application of fundamental heat transfer principles and material science. Designing the positioning of these filled voids to optimize heat flow and minimize thermal crosstalk would be an obvious engineering solution for a PHOSITA. The patent's own definitions strongly suggest these concepts are known or obvious in the art.

US Patent 11,621,360: Term Adjustments, Family Members, and Expiration

Patent Term Adjustments (PTA) and Patent Term Extensions (PTE):
US Patent 11,621,360 shows a "Legal status: Active, expires 2034-05-22" on its Google Patents page. This "Adjusted expiration" date already incorporates any Patent Term Adjustment (PTA) applied due to delays during the patent's prosecution by the USPTO. The specific breakdown of the PTA duration is not provided in this summary view. No Patent Term Extensions (PTE), which are typically related to regulatory review periods for certain products (e.g., pharmaceuticals), are explicitly mentioned for this patent.

Continuation Applications, Divisional Applications, and Related Family Members:
US Patent 11,621,360 (application number US17/707,429) is part of an extensive patent family, demonstrating a complex lineage through various priority claims and application types.

Key related applications and patents in its family include:

• Earliest Priority and Prior Art Date: May 22, 2013, stemming from PCT/US2014/039208 (international publication WO2014190189A2).
• Continuations-in-Part (CIPs):
  • US16/528,958 (issued as US11121271B2) is a CIP of several applications: US16/296,985 (issued as US10468543), US16/042,535 (issued as US10700225), PCT/US18/57963, and PCT/US18/43289.
  • US15/797,821 (issued as US10446700B2) is a CIP of PCT/US16/67977 and US15/309,922 (issued as US9818893).
• Continuations (CONTs):
  • US16/296,985 is a continuation of US15/797,821.
  • US15/309,922 is a continuation of US14/943,898 (issued as US9530905) and US14/945,003 (issued as US9525084).
• National Stage Application: US15/309,922 is also the National Stage of PCT/US15/61120.
• Other Priority Claims: The patent also claims priority from subsequent applications: US17/182,954 (issued as US11791432B2), US17/532,831 (issued as US11309444B1), US18/113,474 (published as US20230215962A1), US18/385,213 (issued as US12087871B2), and US18/822,880 (issued as US12243948B2).
• Publication: US20220246775A1 is another published version of a related application.

Projected Expiration Date:
The projected expiration date for US Patent 11621360 is May 22, 2034.

Defensive Disclosure Document: Derivatives of US Patent 11,621,360

This document outlines derivative variations of the inventions described in US Patent 11,621,360, "Microstructure enhanced absorption photosensitive devices." The purpose is to establish prior art for potential future incremental improvements by competitors, rendering such advancements obvious or non-novel.

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Derivatives of Claim 1: Photodetector with Microstructure-Enhanced Photoabsorption

Claim 1 Summary: A photodetector comprising a cathode, an anode, reverse biasing circuitry, and a microstructure-enhanced photon absorbing semiconductor region. The microstructures (pillars, holes, and/or voids) are dimensioned and positioned to increase photon absorption at a range of wavelengths (with at least one dimension equal to or shorter than the longest signal wavelength) and are arranged in various patterns. The enhancement is attributed to optical effects such as resonance, scattering, near-field, sub-wavelength, and/or interference effects. The absorbing region can be formed of silicon, germanium, or III-V materials.

1. Material & Component Substitution

Derivative 1.1: Organic Semiconductor Microstructure Photodetector

Enabling Description: A photodetector employing an active layer composed of a bulk heterojunction (BHJ) blend of organic donor-acceptor semiconductors (e.g., Poly(3-hexylthiophene-2,5-diyl) (P3HT) as donor and-phenyl-C61-butyric acid methyl ester (PCBM) as acceptor). Microstructures, specifically an array of polymer pillars or holes within the BHJ active layer, are formed via nanoimprint lithography into a spin-coated film. These microstructures are dimensioned with lateral features (e.g., pillar diameter, hole pitch) between 50 nm and 500 nm, and depths corresponding to the film thickness (50-200 nm), which are equal to or shorter than typical visible to near-infrared signal wavelengths. The interface area for exciton dissociation is significantly increased, and light trapping effects (resonance, scattering) within the organic microstructures enhance photon absorption, leading to higher external quantum efficiency. The device operates under reverse bias, with transparent conductive oxide (TCO) electrodes (e.g., ITO, PEDOT:PSS) for charge collection.

flowchart TD
    A[Transparent Electrode] --> B(Hole Transport Layer)
    B --> C{Organic BHJ Active Layer w/ Microstructures}
    C --> D(Electron Transport Layer)
    D --> E[Opaque Electrode]
    F[Reverse Biasing Circuitry] --> A
    F --> E
    subgraph Microstructure Detail
        C1(Polymer Pillars/Holes) --- C2(Organic Semiconductor Blend)
    end

Derivative 1.2: Perovskite Quantum Dot Microstructure Photodetector

Enabling Description: A photodetector utilizing a photon absorbing region composed of cesium lead bromide (CsPbBr3) perovskite quantum dots (PQDs) dispersed within a transparent, high-refractive-index polymer matrix (e.g., poly(methyl methacrylate) (PMMA) or a cross-linked epoxy). The PQDs are synthesized to emit in specific narrow spectral ranges (e.g., green, red, near-infrared). Microstructures in the form of regularly spaced inverse-pyramid voids or nanocones are etched into the PQD-polymer composite layer using electron-beam lithography and reactive ion etching. These microstructures, with feature sizes from 20 nm to 200 nm, are designed to induce localized surface plasmon resonance (LSPR) effects by incorporating metallic nanoparticles (e.g., 10 nm gold nanoparticles) at their apexes or bases, further enhancing light absorption and promoting efficient charge separation from the PQDs. The quantum dot emission/absorption wavelength itself is the reference for sizing.

classDiagram
    class Photodetector {
        +Cathode
        +Anode
        +ReverseBiasingCircuitry
        +AbsorbingRegion
    }
    class AbsorbingRegion {
        +PerovskiteQuantumDots
        +PolymerMatrix
        +MicrostructuredVoids
    }
    class MicrostructuredVoids {
        +InversePyramidShape
        +NanoconeShape
        +MetallicNanoparticles
        +Dimensions: 20-200nm
    }
    Photodetector --> AbsorbingRegion
    AbsorbingRegion --> MicrostructuredVoids

Derivative 1.3: Plasmonic Nanoparticle-Enhanced Dielectric Microstructure Photodetector

Enabling Description: A photodetector comprising a weakly absorbing silicon intrinsic layer (i-Si) as the primary photon absorbing semiconductor region. Embedded within this i-Si layer, an array of sub-wavelength dielectric pillars (e.g., SiO2, SiN) is fabricated. These dielectric pillars are surface-functionalized with an ordered arrangement of plasmonic silver (Ag) nanodiscs or gold (Au) nanorods (e.g., 20-50 nm diameter/width, 50-100 nm length). The period of the dielectric pillars (e.g., 150-300 nm) and the dimensions of the plasmonic nanoparticles are tuned to resonate with incident photons at target wavelengths (e.g., 850 nm, 1310 nm). This plasmonic resonance generates highly confined local electromagnetic fields, which in turn significantly enhance absorption within the adjacent i-Si material, effectively increasing the i-Si absorption coefficient for higher quantum efficiency despite the weak inherent absorption of bulk silicon at longer wavelengths.

graph TD
    A[Incident Photons] --> B(Transparent Electrode)
    B --> C(P-Si Layer)
    C --> D{I-Si Absorbing Region}
    D --> E(N-Si Layer)
    E --> F[Opaque Electrode]
    D -- Contains --> G[Dielectric Pillars]
    G -- Surface Functionalized With --> H[Plasmonic Nanoparticles (Ag/Au)]
    H -- Enhances Local Field --> D

Derivative 1.4: Carbon Nanotube (CNT) Array Microstructure Photodetector

Enabling Description: A photodetector with a photon absorbing semiconductor region composed of an array of vertically aligned single-walled carbon nanotubes (SWCNTs) or multi-walled carbon nanotubes (MWCNTs). These CNTs form the microstructures (pillars) themselves, grown directly on a conductive substrate (e.g., n-doped silicon) via chemical vapor deposition (CVD) using patterned catalyst nanoparticles (e.g., Fe, Co). The length of the CNTs (e.g., 500 nm to 5 µm) and their spacing (e.g., 100 nm to 1 µm) are engineered for optimal broadband light absorption from visible to short-wave infrared (SWIR) due to their high aspect ratio and black body-like absorption characteristics. The CNT array acts as the intrinsic (i) region of a PIN photodiode, with a p-type polymer coating (e.g., PEDOT:PSS) acting as the anode and the n-doped substrate as the cathode. The high carrier mobility within CNTs ensures fast charge collection and high bandwidth.

flowchart TD
    A[Incident Photons] --> B(P-type Polymer Coating / Anode)
    B --> C{Vertically Aligned CNT Array Microstructures (i-region)}
    C --> D[N-type Substrate / Cathode]
    C1(CNT Diameter: 1-100nm) --- C2(CNT Spacing: 100nm-1µm) --- C3(CNT Length: 500nm-5µm)
    subgraph Absorbing Region
        C
    end

2. Operational Parameter Expansion

Derivative 1.5: Terahertz (THz) Range Photodetector with Metamaterial Microstructures

Enabling Description: A photodetector designed for the terahertz (THz) frequency range (0.1-10 THz, corresponding to wavelengths from 30 µm to 3 mm). The photon absorbing semiconductor region consists of a heavily doped silicon (n-Si) substrate. The microstructures are formed as sub-wavelength periodic arrays of metallic split-ring resonators (SRRs) or electric-field-coupled (EFC) resonators fabricated directly on the Si surface via photolithography and metal deposition (e.g., gold, niobium for cryogenic operation). The dimensions of the SRRs (e.g., 10-100 µm diameter, 1-10 µm gap) are tailored to resonate strongly with specific THz frequencies, creating localized electromagnetic field enhancements that dramatically increase the free-carrier absorption in the heavily doped silicon. The device is operated at cryogenic temperatures (e.g., 4 K) to minimize thermal noise and maximize responsivity, with contacts configured for THz photoconductive detection.

graph TD
    A[THz Radiation] --> B(Metallic Metamaterial Microstructures on Si)
    B -- Local Field Enhancement --> C(Heavily Doped Si Substrate / Absorbing Region)
    C -- Free Carrier Absorption --> D(Photocurrent Generation)
    D --> E[Cryogenic Bias Circuitry]
    subgraph Metamaterial Microstructures
        B1(Split-Ring Resonators) --- B2(EFC Resonators)
        B3(Dimensions: 10-100µm)
    end

Derivative 1.6: High-Power, High-Temperature Radiation Detector

Enabling Description: A photodetector designed for operation in extreme radiation and high-temperature environments (e.g., up to 500°C). The photon absorbing semiconductor region is formed from wide-bandgap materials such as silicon carbide (SiC) or gallium nitride (GaN). Microstructures, in the form of deep etching of hexagonal pillars or inverted conical holes (e.g., 1-5 µm diameter, 5-20 µm depth) into the SiC/GaN intrinsic absorption layer, are implemented. These robust microstructures enhance the absorption of high-energy photons (e.g., X-rays, gamma rays) by increasing the interaction volume and optical path length. The pillars/holes are passivated with thermally stable dielectrics (e.g., AlN, HfO2) to prevent surface recombination at high temperatures. The device is reverse-biased with high-temperature stable ohmic contacts (e.g., refractory metals like W, TiN), ensuring stable operation and charge collection under harsh conditions.

stateDiagram-V2
    [*] --> Standby
    Standby --> Operating: High Temp / Radiation
    Operating --> Detect_XRay: X-ray/Gamma Pulse
    Operating --> Detect_Gamma: X-ray/Gamma Pulse
    Detect_XRay --> Signal_Output: Photons absorbed in SiC/GaN microstructures
    Detect_Gamma --> Signal_Output: Photons absorbed in SiC/GaN microstructures
    Signal_Output --> Operating: Continue Detection
    Operating --> Shutdown: Overload / Maintenance
    Shutdown --> [*]
    state SiC_GaN_Microstructures {
        High_Temp_Stability
        Radiation_Hardened
        Enhanced_Absorption
    }

Derivative 1.7: Deep-UV/EUV Photodetector Array

Enabling Description: A photodetector array optimized for deep-ultraviolet (DUV, 100-280 nm) or extreme-ultraviolet (EUV, 10-120 nm) photon detection. The absorbing semiconductor region is composed of an intrinsic aluminum gallium nitride (AlGaN) layer with a high Al content (e.g., Al0.6Ga0.4N) or nanocrystalline diamond. Microstructures are fabricated as very shallow (e.g., 50-200 nm deep) sub-wavelength gratings or periodic hole arrays (e.g., 50-150 nm period, 20-80 nm hole diameter) on the incident surface of the AlGaN/diamond. These structures are designed to function as absorbing-mode high-contrast gratings, minimizing reflection and efficiently coupling DUV/EUV photons into the material for absorption while reducing the active layer thickness for ultra-fast response. The array operates in high vacuum (e.g., 10^-8 Torr) or ultra-high vacuum (UHV) and can be cooled to cryogenic temperatures (e.g., 77 K) to suppress dark current.

graph LR
    A[DUV/EUV Photons] --> B(Surface Microstructures)
    B -- Light Coupling & Absorption --> C(Intrinsic AlGaN/Diamond Layer)
    C -- Electron-Hole Pair Generation --> D(Charge Collection)
    D --> E[Signal Processing]
    subgraph Microstructures
        B1(Sub-wavelength Gratings)
        B2(Periodic Hole Arrays)
        B3(Depth: 50-200nm, Period: 50-150nm)
    end

3. Cross-Domain Application

Derivative 1.8: Environmental Sensing (Gas Detection)

Enabling Description: A gas sensor integrating a microstructure-enhanced absorption photodetector for selective, real-time environmental monitoring. The core is a mid-infrared (MIR) photodetector (e.g., InGaAs, HgCdTe). The absorbing semiconductor region features a periodic array of functionalized silicon pillars, each coated with a gas-selective adsorbent polymer or metal-organic framework (MOF) (e.g., for CO2, methane). The dimensions of the pillars (e.g., 1-10 µm diameter, 5-50 µm length) and their spacing are tuned for resonance with specific vibrational absorption bands of target gas molecules in the MIR range (2-12 µm). When gas molecules are adsorbed onto the functionalized microstructures, they locally alter the refractive index and absorption characteristics within the evanescent field of the microstructures, causing a detectable change in the photodetector's current output.

flowchart TD
    A[Gas Sample] --> B{Functionalized Si Pillars w/ Adsorbent Layer}
    C[MIR Source Signal] --> D(Microstructure-Enhanced MIR Photodetector)
    B -- Adsorption Alters Optical Properties --> D
    D --> E[Electrical Signal]
    E --> F[Gas Concentration Analysis Unit]
    subgraph Photodetector Components
        D1(Pillars tuned for gas absorption)
        D2(Photodetector Core)
    end

Derivative 1.9: Biomedical Imaging (Flexible Endoscopic Photodetector)

Enabling Description: A flexible photodetector array designed for endoscopic biomedical imaging applications. The photon absorbing semiconductor region consists of a flexible membrane of organic semiconductors (e.g., D-A polymers optimized for fluorescent biomarker detection) or ultrathin silicon-on-polymer. Microstructures, in the form of regularly spaced nanodisk or nanoring arrays (e.g., 100-500 nm diameter/outer diameter) are patterned directly into the absorbing membrane. These microstructures enhance the detection of specific fluorescent signals (e.g., 600-900 nm) from targeted biomarkers or contrast agents in biological tissues by increasing light collection efficiency and localized field enhancement, even in low-light environments. The entire array is encapsulated in a biocompatible, flexible polymer (e.g., parylene) for insertion into endoscopic catheters.

sequenceDiagram
    participant Laser as Laser Source
    participant Tissue as Biological Tissue
    participant Biomarker as Fluorescent Biomarker
    participant Endoscope as Flexible Endoscope
    participant Photodetector as Microstructured Photodetector Array
    participant ImageProc as Image Processing Unit

    Laser->>Tissue: Illuminates Tissue
    Tissue->>Biomarker: Absorbs Laser Light
    Biomarker->>Photodetector: Emits Fluorescence (600-900nm)
    Photodetector->>Endoscope: Detects Fluorescence via Microstructures
    Endoscope->>ImageProc: Transmits Electrical Signal
    ImageProc->>ImageProc: Reconstructs Biomedical Image
    Note right of Photodetector: Microstructures enhance collection

Derivative 1.10: Automotive LiDAR (Solid-State APD Array)

Enabling Description: A solid-state LiDAR receiver based on an avalanche photodiode (APD) array, where each APD element incorporates a microstructure-enhanced photon absorbing region. The absorbing region is a Ge-on-Si PIN structure. Microstructures, specifically deep trenches forming an array of square-lattice pillars (e.g., 1-3 µm side length, 5-10 µm depth), are etched into the Ge absorption layer. These pillars enhance absorption of 1550 nm LiDAR pulses by extending the optical path length and acting as an anti-reflection grating. The Ge layer is epitaxially grown on a silicon multiplication layer, which itself contains microstructured voids in its intrinsic region to minimize capacitance and transit time for high bandwidth (e.g., >10 Gb/s per pixel). This allows for high quantum efficiency and fast response crucial for object detection and ranging in autonomous vehicles.

flowchart LR
    A[LiDAR Pulse (1550nm)] --> B(Ge Absorption Layer with Microstructured Pillars)
    B -- Photons --> C(Silicon Multiplication Layer)
    C -- Avalanche Gain --> D(Electrical Signal)
    D --> E[Readout Circuitry]
    subgraph Microstructures
        B1(Ge Pillars: 1-3µm side, 5-10µm depth)
        C1(Si Multiplication Layer with Voids for low C)
    end
    style B fill:#f9f,stroke:#333,stroke-width:2px
    style C fill:#ccf,stroke:#333,stroke-width:2px

4. Integration with Emerging Tech

Derivative 1.11: AI-Optimized Microstructure Photodetector

Enabling Description: A photodetector system where the design and operational parameters of its microstructure-enhanced absorbing region are dynamically optimized by an artificial intelligence (AI) model. During fabrication, a generative AI (e.g., a deep learning model trained on FDTD simulations and experimental data) predicts optimal microstructure geometries (e.g., pillar diameter, pitch, shape, depth, and filler material permittivity) for target wavelength ranges (e.g., 700-1700 nm) to achieve maximum quantum efficiency and bandwidth. In operation, an embedded AI (e.g., a reinforcement learning agent) continuously monitors real-time performance metrics (e.g., photocurrent, dark current, temperature) via integrated IoT sensors. The AI adjusts device parameters such as reverse bias voltage and selects optimal signal processing algorithms to compensate for environmental fluctuations, component aging, or varying input optical power, maintaining peak performance across its lifespan.

sequenceDiagram
    participant AI_Design as AI Design Engine
    participant FabProcess as Fabrication Process
    participant Photodetector as Microstructured Photodetector
    participant IoT_Sensors as IoT Sensors
    participant AI_Ops as AI Operations Controller

    AI_Design->>FabProcess: Optimize Microstructure Geometry (Pillar, Hole, Void)
    FabProcess->>Photodetector: Fabricate Device
    Photodetector->>IoT_Sensors: Generate Photocurrent
    IoT_Sensors->>AI_Ops: Send Real-time Performance Data (I_phot, I_dark, Temp)
    AI_Ops->>AI_Ops: Analyze Data & Predict Performance
    AI_Ops-->>Photodetector: Adjust Reverse Bias / Signal Processing
    Photodetector->>AI_Ops: Update Performance

Derivative 1.12: IoT-Enabled Smart Photodetector Network

Enabling Description: A distributed network of miniature, low-power, microstructure-enhanced photodetectors (e.g., Si PIN photodiodes with porous Si microstructures). Each photodetector node incorporates integrated Internet of Things (IoT) sensors for environmental parameters (e.g., ambient light intensity, spectral composition, temperature, humidity) and a low-power wireless communication module (e.g., Bluetooth Low Energy (BLE) or LoRaWAN). The microstructure design enhances absorption across a broad spectrum (e.g., visible light for smart lighting, near-infrared for occupancy sensing), allowing the device to operate with minimal power consumption, potentially harvesting energy from ambient light. Data collected from the network is aggregated by a central gateway for analysis, enabling dynamic lighting control, precise environmental monitoring in smart buildings, or discreet security surveillance.

graph TD
    A[Ambient Light/IR] --> B(Microstructured Photodetector)
    B --> C(Integrated IoT Sensors)
    C --> D(Low-Power Wireless Module)
    D -- BLE/LoRaWAN --> E(IoT Gateway)
    E --> F[Cloud/Local Server]
    F -- Data Analysis --> G[Smart Application (Lighting, HVAC, Security)]
    subgraph Photodetector Node
        B
        C
        D
    end

Derivative 1.13: Blockchain-Verified Photon Detection for Quantum Key Distribution (QKD)

Enabling Description: A quantum key distribution (QKD) system utilizing microstructure-enhanced single-photon avalanche photodiodes (SPADs) for secure communication. Each SPAD's absorbing region consists of a silicon-on-insulator (SOI) wafer with deep etched silicon nanowires forming the microstructures, optimized for high quantum efficiency at 1550 nm and extremely low dark count rates. Every detected single-photon event triggers a cryptographic hash function, generating a unique digital fingerprint of the event including timestamp, detector ID, and polarization state. This event data is then immutably recorded as a transaction on a distributed ledger (blockchain). This blockchain integration provides cryptographically verifiable proof of each photon detection, ensuring the integrity and authenticity of the QKD process against eavesdropping or tampering, which is critical for highly secure communication channels.

flowchart TD
    A[Single Photons (QKD)] --> B(Microstructured SPAD)
    B -- Detection Event --> C(Cryptographic Hash Generator)
    C -- Event Data (Timestamp, ID, Polarization) --> D(Blockchain Network)
    D -- Immutable Record --> E[Verified QKD Key]
    subgraph SPAD
        B1(SOI Si Nanowires)
        B2(Low Dark Count)
    end

5. The "Inverse" or Failure Mode

Derivative 1.14: Fail-Safe Low-Sensitivity Photodetector for Radiation Overload Protection

Enabling Description: A photodetector with a microstructure-enhanced photon absorbing region designed for fail-safe operation under radiation overload conditions. The microstructures (e.g., silicon pillars or holes) are coated with a thermochromic or photochromic polymer. Under normal operating photon flux, the polymer is transparent. However, when exposed to excessively high photon intensities (e.g., an intense laser pulse, gamma burst), the polymer undergoes a rapid, reversible or irreversible phase transition or chemical change, causing it to become highly absorptive or reflective at the signal wavelength. This change in optical properties within the microstructures drastically reduces the effective quantum efficiency of the photodetector, limiting the photocurrent output and preventing saturation or permanent damage to the subsequent readout electronics. The device thus enters a safe, low-sensitivity mode, signaling an overload event without catastrophic failure.

stateDiagram-V2
    state Normal_Operation {
        Photodetector_Active
        Polymer_Transparent
        High_QE
    }
    state Overload_Condition {
        Radiation_Overload
        Polymer_Transforms
        Low_QE
        Signal_Limited
    }
    Normal_Operation --> Overload_Condition: Excessive Photon Flux
    Overload_Condition --> Normal_Operation: Overload Removed (if reversible)
    Overload_Condition --> Fail_Safe_State: Permanent Damage (if irreversible)
    Fail_Safe_State --> [*]

Derivative 1.15: Limited-Functionality "Harvesting Mode" Photodetector

Enabling Description: A dual-mode device functioning as both a limited-functionality ambient light harvester and a high-speed photodetector. The microstructure-enhanced absorbing region employs silicon (or amorphous silicon) pillars or voids, specifically designed for broadband light absorption across the visible spectrum. In "harvesting mode" (zero or low bias voltage), the microstructures are configured to maximize the generation and collection of electron-hole pairs as a photovoltaic device, providing minimal power to integrated low-power electronics (e.g., IoT sensors). When a specific electrical trigger or command signal is received, reverse biasing circuitry is engaged, transitioning the device to "detection mode." In this mode, the same microstructures facilitate rapid charge collection for high-bandwidth signal detection, leveraging their enhanced absorption properties for communication or sensing.

flowchart LR
    A[Ambient Light] --> B{Microstructured Absorbing Region}
    B -- No Bias --> C{Harvesting Mode (PV)}
    C --> D[Low Power Electronics]
    D -- Trigger Signal --> E(Switch to Reverse Bias)
    E --> F{Detection Mode (PD)}
    F -- High Speed Signal --> G[High Speed Readout]

Derivative 1.16: Degraded-Absorption Calibration Photodetector

Enabling Description: A photodetector with a microstructure-enhanced absorbing region designed for internal calibration and self-diagnosis of degradation. The absorbing semiconductor region (e.g., silicon) is fabricated with an array of microstructured pillars or holes. However, these microstructures are intentionally designed with a controlled, pre-defined gradient of manufacturing defects (e.g., varying aspect ratios, non-uniform etching depths, or programmed inclusion of light-scattering impurities within specific pillars) across the detector area. This creates zones of predictably degraded absorption efficiency. By periodically illuminating different zones with a known reference light source, the device can measure its varying photocurrent output across the array. This allows for continuous, in-situ calibration of the detector's quantum efficiency, tracking degradation over time, and compensating for non-uniformities caused by aging or environmental factors.

graph TD
    A[Reference Light Source] --> B(Microstructured Photodetector Array)
    B -- Zone 1 --> C(Nominal Absorption)
    B -- Zone 2 --> D(Slightly Degraded Absorption)
    B -- Zone 3 --> E(Significantly Degraded Absorption)
    B --> F[Readout & Calibration Unit]
    F -- Compares Outputs --> G[Generates Degradation Map & Correction Factors]
    subgraph Microstructure Degradation
        B1(Varying Aspect Ratios)
        B2(Non-uniform Etching)
        B3(Programmed Impurities)
    end

---

Derivatives of Claim 14: Photovoltaic Device with Buried Voids

Claim 14 Summary: A photovoltaic device comprising a semiconductor material having a plurality of buried voids therein. These voids are microstructured and configured to enhance absorption of the semiconductor material, thereby increasing conversion efficiency. The voids are sized and/or spaced apart by less than 3 microns to alter an effective refractive index of the semiconductor material near a surface, for example, to reduce reflection of incident sunlight from the device and/or increase internal reflections within the semiconductor material.

1. Material & Component Substitution

Derivative 14.1: Multi-junction PV with Buried Interfacial Voids

Enabling Description: A multi-junction photovoltaic device (e.g., triple-junction cell using GaAs/InGaAs/Ge sub-cells). Buried microstructured voids are strategically introduced at the interfaces between specific sub-cells (e.g., between the GaAs top cell and InGaAs middle cell). These voids are filled with a low-refractive-index aerogel (e.g., silica aerogel, n~1.05-1.1) or a selective dielectric material. The voids, with dimensions (e.g., 200 nm to 1 µm) and spacing optimized, function as internal Bragg reflectors or spectrally selective scattering centers. They redirect photons of specific wavelengths that would otherwise be inefficiently absorbed by the current sub-cell, channeling them to the deeper sub-cells (e.g., longer wavelength photons to the InGaAs or Ge cell), thereby improving overall spectral utilization and conversion efficiency of the multi-junction device.

graph TD
    A[Incident Sunlight] --> B(Top Cell: GaAs)
    B -- Photons Passed --> C{Buried Interfacial Voids 1}
    C --> D(Middle Cell: InGaAs)
    D -- Photons Passed --> E{Buried Interfacial Voids 2}
    E --> F(Bottom Cell: Ge)
    F --> G[Electrodes & Output]
    subgraph Voids at Interface
        C1(Aerogel/Dielectric Filled)
        C2(Dimensions: 200nm-1µm)
        C3(Function: Bragg Reflector/Scattering)
    end

Derivative 14.2: Flexible Thin-Film PV on Polymer with Buried Voids

Enabling Description: A flexible thin-film photovoltaic device (e.g., CIGS or organic PV) fabricated on a conformable polymer substrate (e.g., polyimide, polyethylene naphthalate (PEN)). The polymer substrate itself is engineered to contain a plurality of buried, microstructured voids. These voids, sized between 500 nm and 2 µm, are filled with a soft dielectric gel or low-density polymer foam. This specific void-filled substrate serves multiple functions: it reduces the effective refractive index of the substrate for backside reflection enhancement, increases the overall mechanical flexibility and resilience of the device against bending or impact, and provides a barrier against moisture ingress. The embedded voids allow the entire PV module to be highly conformable for integration into irregular surfaces.

flowchart TD
    A[Incident Sunlight] --> B(Transparent Encapsulant)
    B --> C(Thin-Film PV Absorber)
    C --> D(Back Contact)
    D --> E{Flexible Polymer Substrate with Buried Voids}
    E --> F[Output Leads]
    subgraph Buried Voids
        E1(Filled with Soft Dielectric Gel/Foam)
        E2(Dimensions: 500nm-2µm)
        E3(Functions: Flexibility, Reflection, Moisture Barrier)
    end

Derivative 14.3: Perovskite Solar Cell with Buried Voids in Transport Layers

Enabling Description: A perovskite solar cell (PSC) structure incorporating microstructured voids within its electron transport layer (ETL, e.g., mesoporous TiO2, SnO2) and/or hole transport layer (HTL, e.g., Spiro-OMeTAD). The voids, with characteristic dimensions between 100 nm and 500 nm and filled with inert gas (e.g., N2) or vacuum, are formed via templating (e.g., colloidal crystal assembly) or selective etching of sacrificial components. These buried voids specifically reduce the effective refractive index of the transport layers, minimizing parasitic light absorption within these layers and enhancing internal reflections (light trapping) within the primary perovskite active layer. This leads to a higher photocurrent generation within the perovskite, improving overall device conversion efficiency and potentially mitigating issues like long-term stability by reducing stress on the perovskite interface.

graph TD
    A[Incident Sunlight] --> B(Transparent Electrode)
    B --> C{Electron Transport Layer (ETL) w/ Buried Voids}
    C --> D(Perovskite Active Layer)
    D --> E{Hole Transport Layer (HTL) w/ Buried Voids}
    E --> F(Back Electrode)
    F --> G[Output]
    subgraph ETL/HTL Voids
        C1(Gas/Vacuum Filled)
        C2(Dimensions: 100-500nm)
        C3(Functions: Low n_eff, Light Trapping)
    end

2. Operational Parameter Expansion

Derivative 14.4: High-Concentration Photovoltaic (HCPV) Receiver with Graded Void Density

Enabling Description: A high-concentration photovoltaic (HCPV) receiver utilizing a multi-junction semiconductor stack (e.g., InGaP/GaAs/Ge). The bottom Ge sub-cell incorporates a semiconductor material with a precisely engineered, graded density of buried microstructured voids. The void density is highest near the incident light surface (e.g., >50% void fraction) and gradually decreases with depth. These voids (e.g., 500 nm to 2 µm in diameter, filled with low-index dielectric) create a continuously graded effective refractive index profile. This gradient minimizes reflection losses at the entrance aperture, especially under high solar concentration (e.g., >500x suns), and also enhances light trapping within the absorber. Furthermore, the void structure can be tailored to assist in passive thermal management, by incorporating thermally conductive filler materials (e.g., diamond nanoparticles in a dielectric) in specific void pathways to dissipate concentrated heat, preventing efficiency drop at high temperatures.

graph TD
    A[Concentrated Sunlight] --> B(Top Cell)
    B --> C(Middle Cell)
    C --> D{Ge Bottom Cell with Graded Buried Voids}
    D --> E[Heat Spreader/Sink]
    D --> F[Output]
    subgraph Graded Voids
        D1(High Density (Top)) --> D2(Low Density (Bottom))
        D3(Low n_eff for AR)
        D4(Thermal Management Pathways)
    end

Derivative 14.5: Space-Hardened PV Array with Vacuum-Buried Voids

Enabling Description: A photovoltaic array designed for deep-space missions, requiring extreme radiation hardness and thermal stability. The semiconductor material (e.g., radiation-tolerant InP or SiC) of the solar cells contains a plurality of buried microstructured voids, meticulously created and maintained at near-perfect vacuum (e.g., <10^-9 Torr). These voids, sized from 100 nm to 1 µm, are precisely patterned to enhance light absorption (reducing material thickness and thus radiation damage cross-section) while simultaneously providing superior thermal isolation between critical layers or components. This vacuum-voided structure prevents thermal short circuits and maintains optimal operating temperatures across extreme temperature gradients in space, offering robust protection against thermal shock and minimizing degradation from trapped gases under prolonged high-radiation exposure.

classDiagram
    class PVArray_SpaceHardened {
        +RadiationTolerantSemiconductor
        +BuriedVacuumVoids
        +ExtremeThermalIsolation
        +EnhancedLightAbsorption
    }
    class BuriedVacuumVoids {
        +Size: 100nm-1µm
        +VacuumLevel: <10^-9 Torr
        +Function: Thermal Isolation, Light Trapping
    }
    PVArray_SpaceHardened --> BuriedVacuumVoids

Derivative 14.6: Underwater Thermophotovoltaic (TPV) Device with Hydrogel-Filled Voids

Enabling Description: A thermophotovoltaic (TPV) device for underwater energy harvesting from thermal gradients (e.g., hydrothermal vents, industrial discharge). The TPV cell's semiconductor material (e.g., InGaAs optimized for MIR emission from heat source) incorporates buried microstructured voids filled with a specialized transparent hydrogel (e.g., polyacrylamide-based). These voids, with dimensions from 500 nm to 3 µm, are precisely engineered to match the refractive index of the surrounding seawater (n~1.33) and the TPV semiconductor, ensuring efficient coupling of thermal radiation into the active layer while minimizing reflection. The hydrogel-filled voids provide mechanical stability against hydrostatic pressure at depth, reduce biofouling adherence, and offer a degree of self-healing capability against minor physical damage, ensuring long-term operation in marine environments.

graph TD
    A[Underwater Heat Source] --> B(Thermal Radiation)
    B --> C{TPV Semiconductor w/ Hydrogel-Filled Voids}
    C --> D[Electrical Energy Output]
    subgraph Buried Voids
        C1(Hydrogel-Filled)
        C2(Dimensions: 500nm-3µm)
        C3(Function: Index Matching, Pressure Stability, Anti-biofouling)
    end

3. Cross-Domain Application

Derivative 14.7: Smart Window with Tunable Void Optical Properties

Enabling Description: A smart window system integrating a transparent photovoltaic device with buried, tunable microstructured voids. The semiconductor material is a transparent oxide semiconductor (e.g., amorphous InGaZnO) or a quantum-dot-sensitized solar cell. The buried voids, sized from 100 nm to 1 µm, are filled with an electro-optically active material such as liquid crystals or an electrowetting fluid. Applying an external electric field or voltage dynamically alters the refractive index or light scattering properties of the fluid within the voids. This enables real-time control over the window's transparency, glare reduction, and solar absorption for electricity generation. For example, in a "privacy mode," the voids scatter light, while in a "power generation mode," they are optimized for broadband absorption. This allows buildings to dynamically adjust energy balance and occupant comfort.

flowchart TD
    A[Incident Sunlight] --> B(Transparent PV Layer)
    B --> C{Buried Voids w/ Tunable Electro-Optic Fluid}
    C --> D(Transparent Electrode)
    D --> E[Control Circuitry]
    E -- Voltage/Field --> C
    E --> F[Energy Storage/Grid]
    subgraph Smart Window Features
        C1(Liquid Crystal/Electrowetting Fluid)
        C2(Dimensions: 100nm-1µm)
        C3(Function: Tunable Transparency, Glare Control, PV)
    end

Derivative 14.8: Self-Powered Biosensor with Integrated PV

Enabling Description: A disposable biosensor (e.g., for glucose or pathogen detection) that is self-powered by an integrated microstructure-enhanced photovoltaic (PV) device. The PV device's semiconductor material (e.g., amorphous silicon or organic PV) incorporates buried microstructured voids, sized from 50 nm to 500 nm, filled with a biocompatible, low-index polymer. These voids enhance the absorption of ambient light (e.g., indoor lighting, daylight), generating sufficient direct current electricity (e.g., tens of microwatts) to power the biosensor's low-power electronics (e.g., microcontroller, optical detector, potentiostat) for signal acquisition and processing. The self-powered nature eliminates the need for external batteries, enabling compact, low-cost, and environmentally friendly point-of-care diagnostics.

graph TD
    A[Ambient Light] --> B{Integrated PV with Buried Voids}
    B -- DC Power --> C(Biosensor Electronics)
    C --> D[Sensor Element (e.g., Enzyme, Antibody)]
    D -- Biomarker Detection --> E(Output Signal)
    subgraph PV Device
        B1(Amorphous Si / Organic PV)
        B2(Voids filled w/ biocompatible polymer)
        B3(Dimensions: 50-500nm)
    end

Derivative 14.9: Architectural Cladding with Integrated Solar Panels

Enabling Description: Architectural façade elements (e.g., glass or polymer panels) serving as integrated solar collectors. These panels comprise a transparent or semi-transparent substrate into which a patterned semiconductor material (e.g., thin-film c-Si, amorphous Si, or CIGS) with buried microstructured voids is integrated. The voids, sized between 1 µm and 5 µm and optionally filled with gas or a low-emissivity material, enhance solar radiation absorption for electricity generation. Simultaneously, these voids are positioned and optimized to provide thermal insulation for the building envelope and/or control light transmission into the interior for glare management. The resulting cladding is aesthetically pleasing, generates power, and contributes to the building's energy efficiency.

flowchart TD
    A[Sunlight] --> B(Outer Glazing)
    B --> C{Architectural PV Cladding w/ Buried Voids}
    C --> D(Inner Glazing)
    D --> E[Building Interior]
    C --> F[Electricity Output]
    subgraph Buried Voids in Cladding
        C1(Gas/Low-E Filled)
        C2(Dimensions: 1-5µm)
        C3(Functions: PV Absorption, Thermal Insulation, Light Control)
    end

4. Integration with Emerging Tech

Derivative 14.10: AI-Predictive Maintenance for PV Arrays

Enabling Description: A photovoltaic (PV) array where each module, equipped with US11621360's buried void technology, integrates a suite of Internet of Things (IoT) sensors. These sensors continuously monitor the module's performance (e.g., current-voltage curves, temperature, irradiance, spectral response) and internal conditions, including the integrity of the buried voids (e.g., through embedded micro-acoustic sensors or optical interferometry measuring refractive index changes). An AI model (e.g., a recurrent neural network) deployed on a local edge device or in the cloud analyzes this real-time data to predict degradation patterns specific to the void morphology (e.g., void collapse, filler material degradation, moisture ingress). This enables proactive maintenance scheduling, early fault detection before catastrophic failure, and dynamic adjustment of array operation to maximize overall energy yield and extend the lifespan of the PV installation.

graph TD
    A[PV Module w/ Buried Voids] --> B(IoT Sensors: I-V, Temp, Irrad, Void Integrity)
    B -- Real-time Data --> C(Edge/Cloud AI Model)
    C -- Anomaly Detection & Prediction --> D[Predictive Maintenance Alerts]
    D --> E[Operational Optimization (Grid Control, Energy Storage)]
    subgraph AI Model Functions
        C1(RNN for Degradation Patterns)
        C2(Early Fault Detection)
        C3(Lifetime Prediction)
    end

Derivative 14.11: Supply Chain Tracking of PV Modules via Blockchain

Enabling Description: A system for ensuring the provenance and integrity of photovoltaic (PV) modules that incorporate US11621360's buried void technology. At each critical stage of manufacturing (e.g., raw material sourcing, semiconductor deposition, void formation, module assembly, quality control), key parameters specific to the buried voids (e.g., material composition, dimensions, spacing, filler type) and overall module performance are recorded. This data is cryptographically hashed and immutably stored as transactions on a public or consortium blockchain. Each PV module is assigned a unique digital identity (NFT). Consumers, installers, and recycling facilities can scan a QR code on the module to access its verified history, confirming authenticity, material origins, and environmental impact (e.g., for carbon credits), combating counterfeiting and facilitating efficient end-of-life recycling by providing detailed material breakdown.

sequenceDiagram
    participant RawMaterials as Raw Materials Supplier
    participant Manufacturer as PV Module Manufacturer
    participant QC as Quality Control
    participant Blockchain as Blockchain Network
    participant EndUser as End User/Recycler

    RawMaterials->>Manufacturer: Supply Verified Materials (incl. void fillers)
    Manufacturer->>Blockchain: Record Material Batch & Void Specs
    Manufacturer->>QC: Module Assembly & Void Inspection
    QC->>Blockchain: Record QC Data (Void Morphology, Performance)
    Manufacturer->>EndUser: Deliver Certified PV Module
    EndUser->>Blockchain: Verify Module History (QR Code)
    Note right of Blockchain: Immutable record of void technology parameters

Derivative 14.12: Real-time, Self-Adjusting PV for Grid Stability

Enabling Description: A grid-connected photovoltaic (PV) system incorporating US11621360's buried void technology, enhanced for dynamic response to grid demands. Each PV module integrates micro-inverters with embedded IoT sensors for real-time monitoring of power output, internal temperature, and spectral irradiance. An AI algorithm, either centralized or distributed across the inverters, processes this data. This AI dynamically adjusts the electrical operating point of the PV cells, and if the voids are composed of electro-tunable materials (e.g., electrowetting liquids), it can also fine-tune their optical properties (e.g., reflection, absorption) to optimize power generation for grid stability. For instance, during peak demand, the AI maximizes power output, while during oversupply, it might slightly reduce output or shift absorption spectrum to reduce stress on grid infrastructure, acting as a smart, self-regulating energy source.

graph TD
    A[Sunlight] --> B(PV Module w/ Buried Voids & IoT Sensors)
    B -- Power Output & Data --> C(Micro-inverter w/ Embedded AI)
    C -- Aggregated Data --> D(Grid Management System)
    D -- Demand Signals/Feedback --> C
    C -- Control Signals --> B(Adjust Operating Point / Void Properties)
    B --> E[Grid]

5. The "Inverse" or Failure Mode

Derivative 14.13: Controlled-Degradation PV for End-of-Life Recycling

Enabling Description: A photovoltaic (PV) device incorporating US11621360's buried void technology, where the voids are filled with a sacrificial polymer material engineered for controlled degradation. This filler material (e.g., a specific polylactic acid (PLA) blend or a UV-sensitive polymer) is designed to rapidly depolymerize or dissolve under specific end-of-life recycling conditions (e.g., elevated temperature, exposure to a dilute acid, or intense UV radiation). Upon degradation of the filler, the voids either collapse or become filled with a liquid solvent, facilitating the physical separation of the PV semiconductor material (e.g., silicon) from the encapsulant and electrode layers. This controlled degradation mechanism simplifies the dismantling and recycling process, enabling more efficient recovery of valuable semiconductor materials and reducing the environmental footprint of PV waste.

stateDiagram-V2
    [*] --> Operational_PV: Energy Generation
    Operational_PV --> End_of_Life: Service Life Completed
    End_of_Life --> Recycling_Process: Apply Trigger (Heat, UV, Chemical)
    Recycling_Process --> Void_Degradation: Sacrificial Filler Degrades
    Void_Degradation --> Material_Separation: Layers Dissociate
    Material_Separation --> Component_Recovery: Semiconductor, Glass, Metals
    Component_Recovery --> [*]

Derivative 14.14: "Dormant" PV with Inactivated Voids

Enabling Description: A photovoltaic (PV) device incorporating US11621360's buried void technology, designed for prolonged storage or transport in a "dormant" state. In this dormant state, the microstructured voids are initially filled with a thermally reversible phase-change material (PCM) or a refractive-index-matching liquid. This filler temporarily deactivates the light-trapping and absorption enhancement properties of the voids by making them optically indistinguishable from the surrounding semiconductor or encapsulant. To activate the PV device, a thermal stimulus (e.g., heating above a specific transition temperature) is applied, causing the PCM to solidify into a low-index porous structure or the liquid to drain, thereby creating the functional voids. This "dormant" state protects the sensitive void structures during transport, extends shelf-life, and allows for on-demand activation upon deployment, preventing premature degradation.

flowchart TD
    A[Manufactured PV Device] --> B{Dormant State: Voids Inactivated}
    B -- PCM Solidified / Liquid Present --> C(Transport/Storage)
    C -- Thermal Activation --> D(PCM Melts / Liquid Drains)
    D --> E{Active State: Voids Functional}
    E --> F[PV Power Generation]

Derivative 14.15: Limited-Power "Shadow-Resilient" PV

Enabling Description: A photovoltaic (PV) device with US11621360's buried void technology, engineered for enhanced performance under partial shading conditions. The semiconductor material contains a distributed pattern of microstructured voids. Instead of uniform optimization, some regions of the PV cell have voids optimally designed for maximum absorption enhancement, while adjacent regions have deliberately non-optimal voids (e.g., larger spacing, non-ideal shapes, or partially filled) or even fewer voids. This creates a spatial variation in absorption efficiency across the cell. Under partial shading, the optimally designed void regions continue to contribute maximum power, while the non-optimally designed regions still provide a baseline, albeit reduced, power output. This localized resilience prevents entire cell failure under shading, improving the overall power output and stability of the PV module compared to conventional uniform designs, and mitigating "hot spot" formation.

graph TD
    A[Incident Sunlight (Partial Shade)] --> B{PV Cell with Varied Void Patterns}
    B -- Unshaded Area --> C(Optimal Voids: High Power)
    B -- Shaded Area --> D(Non-Optimal Voids: Limited Power)
    C --> E[Combined Power Output]
    D --> E
    subgraph Void Pattern
        C1(Region 1: Optimal Density/Size)
        D1(Region 2: Reduced Density/Larger Spacing)
        D2(Region 3: Partially Filled Voids)
    end

---

Derivatives of Claim 15: Microwave Transmission Line Structure with Dielectric-Filled Voids

Claim 15 Summary: A microwave transmission line structure comprising a semiconductor substrate material having a plurality of high-density dielectric-filled voids configured to reduce a dielectric constant of the semiconductor substrate material; and a plurality of metallic microwave transmission lines, at least one of which is positioned above the semiconductor substrate material. The voids are further configured to reduce dispersion and reduce loss associated with the microwave transmission lines at least in part by reducing current loop flow and/or eddy currents.

1. Material & Component Substitution

Derivative 15.1: High-Frequency Interposer with Air-Gap Voids

Enabling Description: A silicon interposer for 3D integrated circuits operating in the millimeter-wave (mmWave) band (30-300 GHz). The interposer substrate is fabricated with a high density of buried microstructured air-gap voids (i.e., dielectric-filled with air/vacuum). These voids are formed by selective etching of sacrificial layers (e.g., amorphous silicon) and subsequent sealing within the silicon bulk. The dimensions of the voids (e.g., 5-50 µm diameter) and their volumetric fraction (e.g., >50%) are precisely controlled to significantly reduce the effective dielectric constant (ε_eff < 5) of the silicon substrate. Metallic microwave transmission lines (e.g., coplanar waveguides, microstrip lines) are patterned on the surface of this low-ε_eff interposer, minimizing signal propagation delay, crosstalk between adjacent lines, and reducing substrate losses for high-bandwidth interconnects between stacked ICs.

flowchart TD
    A[High-Speed IC 1] --> B(Through-Silicon Vias - TSVs)
    B --> C{Silicon Interposer with Buried Air-Gap Voids}
    C --> D(Metallic Microwave Transmission Lines)
    D --> E(TSVs)
    E --> F[High-Speed IC 2]
    subgraph Air-Gap Voids
        C1(Selective Etch & Seal)
        C2(Dimensions: 5-50µm)
        C3(Function: Low ε_eff, Reduced Loss)
    end

Derivative 15.2: Flexible Microwave Circuit on Polymer with Ceramic Nanoparticle-Filled Voids

Enabling Description: A flexible microwave circuit (e.g., a patch antenna, a flexible filter) fabricated on a liquid crystal polymer (LCP) substrate. Microstructured voids are created within the LCP substrate using localized laser ablation or sacrificial polymer templating. These voids, sized from 500 nm to 5 µm, are selectively filled with a composite dielectric material consisting of high-permittivity ceramic nanoparticles (e.g., BaTiO3, SrTiO3) dispersed within a low-k polymer matrix. This approach allows for precise, localized tuning of the effective dielectric constant of the substrate beneath specific metallic microwave transmission lines. This localized control enables dynamic impedance matching, frequency tuning of resonant structures, and beam steering for flexible antennas, enhancing the performance and reconfigurability of conformal microwave devices.

graph TD
    A[Metallic Microwave TL] --> B{LCP Substrate with Ceramic-Filled Voids}
    B --> C[Flexible Backing Layer]
    subgraph Voids
        B1(Ceramic Nanoparticle-Filled)
        B2(Dimensions: 500nm-5µm)
        B3(Function: Localized ε_eff Tuning)
    end

Derivative 15.3: Graphene-Enhanced Semiconductor Waveguide with Tunable Ionic Liquid Voids

Enabling Description: A microwave transmission line structure integrating a silicon-on-insulator (SOI) waveguide with buried microstructured voids. These voids, sized between 1 µm and 10 µm, are filled with an ionic liquid whose dielectric constant can be dynamically tuned by an external electric field. Furthermore, the internal surfaces of these voids are coated with a monolayer or few-layer graphene. The graphene acts as an electrically addressable gate, allowing for fine-tuning of the ionic liquid's permittivity by controlling the ion distribution within the void. Metallic microwave transmission lines are patterned above this waveguide. This configuration enables active control over the phase velocity, impedance, and dispersion characteristics of the microwave signals, allowing for real-time adjustments for optimal signal integrity and reducing losses due to changing environmental conditions or operational frequencies.

classDiagram
    class MicrowaveTLS {
        +SemiconductorSubstrate
        +DielectricFilledVoids
        +MetallicTLs
    }
    class SemiconductorSubstrate {
        +SOI_Waveguide
    }
    class DielectricFilledVoids {
        +IonicLiquidFiller
        +GrapheneCoating
        +Dimensions: 1-10µm
        +ElectricallyTunable
    }
    MicrowaveTLS --> SemiconductorSubstrate
    SemiconductorSubstrate --> DielectricFilledVoids

2. Operational Parameter Expansion

Derivative 15.4: Cryogenic Quantum Computing Interconnects with Superfluid Helium Voids

Enabling Description: A microwave transmission line structure for interconnecting superconducting qubits in a quantum computing system, operating at millikelvin temperatures (e.g., 10 mK). The semiconductor substrate material (e.g., ultra-pure silicon or sapphire) contains a precisely engineered array of buried microstructured voids, sized between 10 µm and 100 µm. These voids are filled with superfluid helium-4 (4He), which possesses an extremely low dielectric constant (ε_r ≈ 1.05) and superior thermal conductivity. Metallic microwave transmission lines (e.g., superconducting coplanar waveguides made of Niobium) are fabricated on the surface of this voided substrate. The superfluid helium voids provide ultra-low loss and low dispersion signal propagation, minimize parasitic capacitance, and simultaneously act as efficient local heat sinks, drawing away heat from the qubits to the dilution refrigerator while preserving quantum coherence.

graph TD
    A[Superconducting Qubit 1] --> B(Niobium Microwave TL)
    B --> C{Substrate w/ Superfluid Helium Voids}
    C --> D(Niobium Microwave TL)
    D --> E[Superconducting Qubit 2]
    C --> F[Dilution Refrigerator]
    subgraph Cryogenic Voids
        C1(Superfluid Helium-4 Filled)
        C2(Dimensions: 10-100µm)
        C3(Function: Ultra-low ε_eff, Thermal Conduct)
    end

Derivative 15.5: High-Power RF GaN-on-Si Transistor Modules with Thermally Conductive Voids

Enabling Description: A high-power radio-frequency (RF) module incorporating gallium nitride (GaN) transistors grown on a silicon substrate. The silicon substrate directly beneath the GaN active region and RF transmission lines (e.g., microstrip lines connecting to drain/gate) features buried microstructured voids. These voids, sized from 1 µm to 20 µm, are precisely filled with an electrically insulating, highly thermally conductive material (e.g., diamond-like carbon (DLC), aluminum nitride (AlN) nanoparticles in a polymer matrix). This structure simultaneously reduces the effective dielectric constant of the underlying silicon, minimizing RF signal losses and dispersion, and creates highly efficient heat dissipation pathways directly from the hot GaN devices through the conductive voids to a heat sink. This enables stable operation of high-power GaN transistors at higher frequencies and power levels without detrimental thermal degradation.

flowchart TD
    A[High Power GaN Transistor] --> B(GaN Active Layer)
    B --> C(Silicon Substrate)
    C -- Contains --> D{Buried Thermally Conductive Voids}
    D --> E[Heat Sink]
    C --> F(Metallic RF Transmission Lines)
    F --> G[RF Output]
    subgraph Voids
        D1(Filled w/ DLC/AlN)
        D2(Dimensions: 1-20µm)
        D3(Functions: Low ε_eff, High Thermal Conduct)
    end

Derivative 15.6: Deep-Space Communication Links with Radiation-Hardened Voided Substrates

Enabling Description: A microwave transmission line structure for deep-space communication systems, requiring extreme radiation hardness and thermal stability. The semiconductor substrate material is made of radiation-tolerant silicon carbide (SiC). Buried microstructured voids, sized between 2 µm and 50 µm, are created within the SiC substrate and filled with a radiation-hardened, low-permittivity polymer (e.g., specific polyimides, epoxies) or simply maintained as vacuum voids. Metallic microwave transmission lines (e.g., gold microstrip lines) are patterned on this voided SiC. This design ensures that the effective dielectric constant and signal integrity remain stable over prolonged exposure to cosmic radiation (e.g., high-energy protons, heavy ions), minimizing RF signal loss, dispersion, and phase noise, which are critical for maintaining robust communication links over vast distances.

classDiagram
    class DeepSpaceCommunication {
        +RadiationHardenedSiCSubstrate
        +BuriedRadiationHardenedVoids
        +MetallicMicrowaveTLs
    }
    class BuriedRadiationHardenedVoids {
        +Filler: Radiation-Hardened Polymer/Vacuum
        +Dimensions: 2-50µm
        +Function: Stable ε_eff, Low Loss in Radiation
    }
    DeepSpaceCommunication --> BuriedRadiationHardenedVoids

3. Cross-Domain Application

Derivative 15.7: Structural Health Monitoring (SHM) Sensors with Embedded Wireless

Enabling Description: A structural health monitoring (SHM) system integrating passive microwave sensors embedded within civil infrastructure (e.g., concrete bridges, aircraft composite panels). Each sensor node comprises a metallic microwave resonant circuit (e.g., split-ring resonator, dipole antenna) fabricated on a small semiconductor substrate (e.g., silicon). This substrate contains buried high-density dielectric-filled voids, typically air-gaps or low-k polymer-filled voids, to reduce its effective dielectric constant. When mechanical stress (e.g., micro-cracks, strain) or environmental factors (e.g., moisture ingress) alter the permittivity of the surrounding material or deform the substrate, the resonant frequency of the embedded microwave circuit shifts. This shift is wirelessly interrogated by an external radar system, providing real-time, non-destructive assessment of the structure's integrity with minimal signal attenuation from the embedded sensor.

flowchart TD
    A[External Radar Interrogator] --> B(Microwave Signal)
    B --> C{Embedded Passive Microwave Sensor}
    C -- Resonant Frequency Shift --> B
    B --> A
    subgraph Sensor
        C1(Metallic Resonant Circuit)
        C2(Voided Semiconductor Substrate)
        C3(Environmental Change Detection)
    end

Derivative 15.8: Advanced Driver-Assistance Systems (ADAS) Radar Modules

Enabling Description: Millimeter-wave (mmWave) radar modules for Advanced Driver-Assistance Systems (ADAS) in autonomous vehicles. The radar module's monolithic microwave integrated circuit (MMIC) is fabricated on a silicon or SiGe substrate with engineered buried dielectric-filled voids. These voids, precisely patterned beneath on-chip antennas (e.g., patch antennas, Vivaldi antennas) and critical transmission lines (e.g., coplanar waveguides), are filled with air or a low-k dielectric to reduce the effective dielectric constant of the substrate. This reduction minimizes substrate-induced losses and radiation leakage, enhancing antenna efficiency, reducing interference (e.g., from other radar units), and improving the overall range and resolution of the radar system for robust obstacle detection, adaptive cruise control, and blind-spot monitoring.

graph TD
    A[Radar Wave (mmWave)] --> B(On-Chip Antenna)
    B --> C{MMIC Substrate with Buried Voids}
    C --> D(Radar Signal Processing Unit)
    D --> E[ADAS Control Unit]
    subgraph MMIC Substrate
        C1(Si/SiGe)
        C2(Air/Low-k Filled Voids)
        C3(Function: Enhance Antenna Efficiency, Reduce Losses)
    end

Derivative 15.9: High-Density Data Center Interconnects for Optical/Electrical Co-Integration

Enabling Description: An integrated platform for high-density data center interconnects, featuring co-integrated optical waveguides and high-speed electrical microwave transmission lines on a single silicon substrate. The electrical transmission lines (e.g., strip lines, coplanar waveguides) are patterned on regions of the silicon substrate specifically engineered with high-density buried dielectric-filled voids (e.g., air-gaps or low-k porous silicon). These voided regions drastically reduce the effective dielectric constant and inductive coupling between adjacent electrical lines, enabling ultra-low-latency, multi-terabit electrical signaling over short distances. This minimizes crosstalk and power consumption for electrical data transfer, allowing for seamless co-integration and reduced interference with adjacent silicon photonic optical waveguides also present on the same platform, facilitating dense chip-to-chip and board-to-board communication.

flowchart LR
    A[Electrical Data Input] --> B(Microwave TLs on Voided Si)
    B --> C(Electrical Output)
    D[Optical Data Input] --> E(Optical Waveguide on Si)
    E --> F(Optical Output)
    subgraph Co-integrated Platform
        B
        E
        C
        F
        style B fill:#fcf,stroke:#333,stroke-width:2px
        style E fill:#ccf,stroke:#333,stroke-width:2px
    end

4. Integration with Emerging Tech

Derivative 15.10: AI-Adaptive Impedance Matching for 6G Wireless

Enabling Description: A microwave transmission line structure for 6G wireless communication systems, featuring AI-adaptive impedance matching. The semiconductor substrate contains an array of buried microstructured voids, where selected voids are filled with electro-tunable dielectric materials (e.g., barium strontium titanate (BST) ferroelectrics or electrowetting fluids). Metallic microwave transmission lines are patterned above this substrate. An integrated AI controller, receiving real-time feedback on signal reflection (S11 parameter) and frequency characteristics, dynamically adjusts the electrical bias applied to the tunable voids. This enables active, real-time control over the local effective dielectric constant and, consequently, the impedance of the transmission lines. The AI continuously optimizes impedance matching across wide frequency bands or varying environmental conditions, allowing for robust, low-loss signal delivery in cognitive radio and dynamic spectrum access scenarios for 6G.

sequenceDiagram
    participant 6G_Transceiver as 6G Transceiver
    participant MicrowaveTL as Microwave TL w/ Tunable Voids
    participant AI_Controller as AI Controller
    participant RF_Sensors as RF Sensors

    6G_Transceiver->>MicrowaveTL: Transmit RF Signal
    MicrowaveTL->>RF_Sensors: Reflect S11, Frequency Data
    RF_Sensors->>AI_Controller: Send Real-time RF Data
    AI_Controller->>AI_Controller: Analyze Data, Compute Optimal Impedance
    AI_Controller->>MicrowaveTL: Adjust Voltage to Tunable Voids
    MicrowaveTL->>6G_Transceiver: Optimized Signal Transmission

Derivative 15.11: IoT-Enabled RFIDs with Enhanced Read Range

Enabling Description: Ultra-compact, low-cost radio-frequency identification (RFID) tags for Internet of Things (IoT) applications, featuring enhanced read range. The RFID tag's antenna and matching network are fabricated as metallic microwave transmission lines directly on a silicon substrate containing high-density buried microstructured air-gap voids. These voids (e.g., 1-10 µm) are created to significantly reduce the effective dielectric constant of the silicon substrate, thereby minimizing dielectric losses and enabling higher antenna efficiency for a given form factor. This reduction in loss and increase in efficiency extends the effective read range of passive RFID tags, allowing for more reliable asset tracking, inventory management, and sensor data acquisition across wider areas without requiring active power at the tag itself.

graph TD
    A[RFID Reader] --> B(RF Signal)
    B --> C{IoT RFID Tag w/ Voided Substrate}
    C -- Backscattered Signal --> B
    B --> A
    subgraph RFID Tag
        C1(Metallic Antenna/Matching Network)
        C2(Si Substrate w/ Air-Gap Voids)
        C3(Function: Enhanced Read Range)
    end

Derivative 15.12: Blockchain-Secured Communication Channels

Enabling Description: A system for ensuring the physical layer security and integrity of high-frequency communication channels using US11621360's voided substrate technology. The metallic microwave transmission lines are fabricated on a semiconductor substrate with buried dielectric-filled voids (e.g., air, low-k polymer). Integrated micro-sensors (e.g., piezoresistive sensors, thermal sensors) within the substrate continuously monitor physical parameters such as void integrity, dielectric constant stability, and any subtle structural deformations or temperature anomalies that could indicate tampering or environmental attack. Any detected deviation from baseline parameters generates an alert. These alerts, along with timestamped sensor data, are cryptographically signed and recorded as immutable transactions on a distributed ledger (blockchain), providing an auditable and tamper-proof log of the communication channel's physical security state.

flowchart TD
    A[Microwave TX/RX] --> B{Communication Channel (Microwave TL on Voided Substrate)}
    B -- Physical Parameters --> C(Integrated Micro-Sensors)
    C -- Anomaly Detection --> D(Cryptographic Hashing Unit)
    D -- Signed Data --> E(Blockchain Network)
    E --> F[Immutable Security Log]
    subgraph Channel Monitoring
        C1(Void Integrity, ε_eff, Deformation, Temp)
        C2(Tamper Detection)
    end

5. The "Inverse" or Failure Mode

Derivative 15.13: Controlled Signal Attenuation for RF Power Limiting

Enabling Description: A microwave transmission line structure designed to act as a self-regulating RF power limiter. The semiconductor substrate beneath the metallic transmission line contains buried microstructured voids filled with a material that exhibits a non-linear increase in dielectric loss tangent or electrical conductivity when exposed to RF fields exceeding a predetermined threshold power density. This filler material could be a composite embedded with field-sensitive nanoparticles or a phase-change material. When the incident RF power surpasses the threshold, the filler material within the voids dynamically becomes lossy, causing a rapid and controlled attenuation of the propagating microwave signal. This passive, fail-safe mechanism protects sensitive downstream RF components from damage due to excessive input power without requiring external control circuitry.

stateDiagram-V2
    state Normal_Operation {
        RF_Signal_Propagates
        Voids_LowLoss
    }
    state Overload_Condition {
        RF_Power_Exceeds_Threshold
        Void_Filler_Becomes_Lossy
        Signal_Attenuation
        Downstream_Protection
    }
    Normal_Operation --> Overload_Condition: High RF Power Density
    Overload_Condition --> Normal_Operation: RF Power Below Threshold (if reversible)
    Overload_Condition --> Protected_Shutdown: Critical Overload (if irreversible)
    Protected_Shutdown --> [*]

Derivative 15.14: "Stealth Mode" Microwave Circuits with Tunable Lossy Voids

Enabling Description: A microwave circuit with transmission lines on a semiconductor substrate containing buried microstructured voids. These voids are filled with a reconfigurable material whose dielectric properties (specifically, its loss tangent and/or permittivity) can be dynamically tuned (e.g., via an external electric field, optical stimulus, or temperature change). In a "normal" operational mode, the voids are configured to be low-loss. However, upon activation into a "stealth mode," the filler material is tuned to become highly absorptive and/or impedance-mismatched. This intentionally maximizes signal attenuation and minimizes signal reflection (reducing its radar cross-section), making the circuit nearly undetectable by external RF sensors or signal sniffers. This mode could also be used for self-testing by absorbing reflected signals without external loads or for secure, short-range, non-radiating internal communication.

flowchart TD
    A[RF Input] --> B{Microwave TL on Substrate w/ Tunable Voids}
    B -- Control Signal --> C(Toggle Mode: Normal / Stealth)
    C -- Normal Mode --> D[Low Loss Output]
    C -- Stealth Mode --> E[High Loss / Low Reflection]
    subgraph Tunable Voids
        B1(Electrically/Optically Tunable Filler)
        B2(Function: Adjustable Loss Tangent/ε_eff)
    end

Derivative 15.15: Environmental Degradation Indicator for Space Assets

Enabling Description: A microwave transmission line structure designed for space applications, integrating a built-in environmental degradation indicator. The semiconductor substrate (e.g., GaAs) beneath the metallic transmission lines contains buried microstructured voids filled with a sacrificial dielectric material specifically engineered to predictably degrade (e.g., change permittivity, become electrically conductive, or physically collapse) when exposed to specific levels of cosmic radiation (e.g., cumulative dose of protons, heavy ions) or extreme thermal cycling. This degradation manifests as a measurable change in the characteristic impedance, insertion loss, or reflection coefficient of the transmission line. By periodically performing on-chip time-domain reflectometry (TDR) measurements, the extent of degradation can be precisely quantified, providing a passive, real-time "health indicator" for the microwave component and predicting its remaining operational lifespan in the harsh space environment.

graph TD
    A[Cosmic Radiation/Thermal Stress] --> B{Substrate w/ Degradable Void Filler}
    B -- Degradation --> C(Change in TL Impedance/Loss)
    C --> D(On-Chip TDR Measurement)
    D --> E[Health Indicator Output]
    E --> F[Predicted Remaining Lifespan]
    subgraph Degradable Voids
        B1(Sacrificial Dielectric Filler)
        B2(Function: Environmental Health Indicator)
    end

---

Derivatives of Claim 16: Optical Waveguide Structure with Microstructured Voids

Claim 16 Summary: An optical waveguide structure comprising an optical mode region; and a supporting semiconductor material adjacent to the optical mode region, the supporting material including a plurality of microstructured voids that are configured to alter an effective index of refraction of the supporting material based on the size, shape, density, etc. of the microstructured voids.

1. Material & Component Substitution

Derivative 16.1: Polymer Waveguide with Air-Gap Microstructured Cladding

Enabling Description: An optical waveguide structure where the optical mode region is a transparent polymer core (e.g., cyclo-olefin polymer, PMMA) fabricated using direct-write lithography or extrusion. The supporting material, acting as the cladding, is also a polymer (e.g., a UV-curable resin or a thermoplastic) into which a high-density array of microstructured air-gaps (voids) is introduced via selective etching or 3D printing techniques. These air-gap voids, with characteristic dimensions between 500 nm and 5 µm, significantly reduce the effective refractive index of the cladding (ε_eff < 1.3), creating a very high refractive index contrast with the polymer core. This high contrast leads to superior optical confinement, minimizing propagation losses and enabling tightly bent waveguides for high-density flexible optical interconnects in consumer electronics or data communications.

flowchart TD
    A[Optical Signal Input] --> B(Polymer Waveguide Core)
    B -- Light Confinement --> C{Polymer Cladding with Air-Gap Microstructured Voids}
    C --> B
    B --> D[Optical Signal Output]
    subgraph Cladding Voids
        C1(Air-Gap Microstructures)
        C2(Dimensions: 500nm-5µm)
        C3(Function: Low n_eff, High Confinement)
    end

Derivative 16.2: III-V Semiconductor Waveguide with Tunable Liquid Crystal Voids

Enabling Description: An optical waveguide structure fabricated from a III-V semiconductor material (e.g., InP or GaAs) designed for telecommunication wavelengths (e.g., 1310 nm, 1550 nm). The supporting semiconductor material adjacent to the optical mode region contains a plurality of buried microstructured voids, sized between 1 µm and 10 µm. These voids are filled with a liquid crystal (LC) material whose refractive index is anisotropic and can be tuned by an external electric field. Applying voltage to micro-electrodes flanking the waveguide dynamically alters the orientation of the LC molecules within the voids, thereby changing the effective refractive index of the supporting material. This active tuning enables reconfigurable optical functions such as variable optical attenuators, switches, modulators, or dynamic wavelength filters within integrated photonic circuits.

classDiagram
    class OpticalWaveguide {
        +OpticalModeRegion
        +SupportingSemiconductor
    }
    class SupportingSemiconductor {
        +III_V_Material (InP/GaAs)
        +MicrostructuredLCVoids
    }
    class MicrostructuredLCVoids {
        +LiquidCrystalFiller
        +Dimensions: 1-10µm
        +ElectricallyTunable
    }
    OpticalWaveguide --> SupportingSemiconductor
    SupportingSemiconductor --> MicrostructuredLCVoids

Derivative 16.3: Ceramic Waveguide with Metamaterial-Enhanced Void Array

Enabling Description: An optical waveguide structure (e.g., for high-power laser applications) where the optical mode region is guided within a transparent ceramic material (e.g., YAG, Alumina). The supporting ceramic material adjacent to the core incorporates a periodically patterned array of sub-wavelength microstructured voids (e.g., 100-300 nm pitch, 50-150 nm void diameter). These voids are filled with a composite material containing sub-wavelength metallic resonators (e.g., gold split-ring resonators, silver nanorods) embedded in a low-index dielectric matrix. This forms a metamaterial within the voids, allowing for precise engineering of the effective refractive index, group velocity dispersion, and even non-linear optical properties of the supporting material. This enables advanced waveguide functionalities such as tailored dispersion compensation, enhanced non-linear optical interactions, or extreme light confinement beyond conventional dielectric limits.

graph TD
    A[Optical Signal] --> B(Ceramic Waveguide Core)
    B -- Light Guiding --> C{Ceramic Supporting Material w/ Metamaterial Voids}
    C --> B
    C -- Dispersion/n_eff Control --> D[Tailored Waveguide Functionality]
    subgraph Metamaterial Voids
        C1(Sub-wavelength Resonators)
        C2(Filler: Metallic Nanostructures + Dielectric)
        C3(Dimensions: Sub-wavelength)
    end

2. Operational Parameter Expansion

Derivative 16.4: High-Power Laser Delivery Waveguide with Damage-Resistant Voids

Enabling Description: An optical waveguide designed for high-power laser delivery (e.g., multi-kilowatt industrial lasers, medical surgery lasers). The waveguide core is made of high-purity fused silica or sapphire. The surrounding supporting material (cladding) incorporates microstructured voids, typically elongated or elliptical in cross-section (e.g., 5-50 µm major axis) and filled with an inert gas (e.g., argon) or high vacuum. These voids are strategically shaped and positioned to minimize internal field enhancement at the waveguide boundaries, preventing laser-induced damage (LID) phenomena. The low refractive index of the gas/vacuum-filled voids ensures strong optical confinement while the unique void geometry reduces stress concentrations, making the waveguide robust against high peak powers and thermal loads, significantly increasing the laser damage threshold.

flowchart TD
    A[High Power Laser Input] --> B(Fused Silica/Sapphire Waveguide Core)
    B -- Light Propagation --> C{Cladding with Damage-Resistant Voids}
    C --> B
    B --> D[High Power Laser Output]
    subgraph Damage-Resistant Voids
        C1(Inert Gas/Vacuum Filled)
        C2(Geometry: Elongated/Elliptical)
        C3(Function: Prevent LID, Stress Reduction)
    end

Derivative 16.5: Cryogenic Quantum Photonic Circuit with Superconducting-Clad Voids

Enabling Description: An integrated optical waveguide for quantum photonic circuits operating at millikelvin temperatures (e.g., <100 mK). The waveguide (e.g., silicon nitride on silicon) incorporates microstructured voids in its supporting material. These voids, sized between 200 nm and 2 µm, are precisely lined with a thin film of superconducting material (e.g., Niobium Nitride, NbN, or Aluminum, Al). This superconducting cladding around the voids creates an ultra-low-loss optical confinement medium for guided photons by minimizing dielectric absorption losses at cryogenic temperatures. Furthermore, if adjacent to superconducting qubits, these voids can be part of a cavity quantum electrodynamics (cQED) architecture, allowing for strong light-matter interaction while simultaneously providing thermal isolation and mitigating quantum decoherence effects due to stray electromagnetic fields by acting as effective Faraday cages at the quantum level.

stateDiagram-V2
    state Quantum_Photonic_Circuit {
        Optical_Waveguide_Core
        Supporting_Material
        Superconducting_Clad_Voids
    }
    state Superconducting_Clad_Voids {
        Low_Loss_Confinement
        Thermal_Isolation
        Decoherence_Mitigation
        NbN_or_Al_Lining
    }
    Quantum_Photonic_Circuit --> Superconducting_Clad_Voids: Integrated Design
    Superconducting_Clad_Voids --> Quantum_Information_Processing: Enhanced Coherence

Derivative 16.6: Deep-UV Photolithography Waveguide with Voids for Dispersion Compensation

Enabling Description: An optical waveguide structure for deep-ultraviolet (DUV, e.g., 193 nm) photolithography, requiring precise dispersion control. The supporting material adjacent to the waveguide core (e.g., high-purity fused silica) incorporates a carefully designed array of microstructured voids. These voids, with sub-wavelength dimensions (e.g., 50-150 nm period, 20-80 nm diameter), are patterned with varying geometries (e.g., elliptical, asymmetric) and/or filled with specific low-dispersion dielectric gases. This enables tailoring the effective refractive index of the supporting material with a specific wavelength dependency, allowing for highly localized dispersion compensation and chromatic aberration correction within the waveguide. This control is critical for maintaining ultra-high resolution and pattern fidelity in advanced photolithography systems by preventing pulse broadening and spatial distortion of DUV light.

graph TD
    A[DUV Laser Input] --> B(Waveguide Core)
    B -- Light Propagation --> C{Supporting Material w/ Dispersion-Compensating Voids}
    C --> D[DUV Output to Lithography Tool]
    subgraph Voids
        C1(Sub-wavelength, Varied Geometry)
        C2(Low-Dispersion Gas Filled)
        C3(Function: Chromatic Aberration Correction)
    end

3. Cross-Domain Application

Derivative 16.7: Chemical Sensing Waveguide for In-Situ Monitoring

Enabling Description: An optical waveguide structure integrated into a microfluidic lab-on-a-chip platform for in-situ chemical detection. The optical mode region is guided adjacent to a supporting semiconductor material (e.g., silicon nitride) which contains microstructured voids. These voids, typically sub-micron in size, are functionalized with specific chemical recognition elements (e.g., antibodies, enzymes, catalytic nanoparticles) and are designed to be fluidically accessible to sample analytes. When a target chemical binds to the recognition element within the void or undergoes a reaction, it causes a localized change in the refractive index or absorption spectrum within the void. The evanescent field of the guided light interacts with these changes, leading to a detectable shift in the waveguide's transmission spectrum or intensity, providing real-time chemical analysis of the fluid sample.

flowchart TD
    A[Sample Input] --> B(Microfluidic Channel)
    B --> C{Microstructured Void Waveguide (Sensor Area)}
    C -- Chemical Reaction --> C
    D[Light Source] --> E(Optical Waveguide Input)
    E --> C
    C --> F(Optical Waveguide Output)
    F --> G[Spectrometer/Detector]
    G --> H[Chemical Analysis]
    subgraph Voids
        C1(Fluidically Accessible)
        C2(Functionalized for Analytes)
        C3(Changes n_eff/Absorption)
    end

Derivative 16.8: Smart Textile with Embedded Optical Fibers for Health Monitoring

Enabling Description: A smart textile product incorporating embedded flexible optical fibers (waveguides) for continuous health monitoring. The optical fiber core is a standard polymer fiber, but its surrounding polymer cladding (supporting material) is engineered with microstructured voids. These voids, sized from 500 nm to 5 µm, are filled with a stimuli-responsive material (e.g., a hydrogel that swells/shrinks with temperature or pH, a photochromic dye that changes with UV exposure). When the textile is worn, physiological changes (e.g., body temperature, perspiration pH, skin deformation causing strain) cause the filler material within the voids to alter its refractive index or scattering properties. This change is detected as a modulation of light propagation through the embedded optical fiber, providing non-invasive, real-time physiological data for health monitoring.

graph TD
    A[Physiological Stimuli (Temp, pH, Strain)] --> B(Smart Textile)
    B --> C{Embedded Optical Fiber with Voided Cladding}
    C -- Light Modulation --> D[Optical Sensor Unit]
    D --> E[Health Monitoring System]
    subgraph Voided Cladding
        C1(Stimuli-Responsive Filler)
        C2(Dimensions: 500nm-5µm)
        C3(Function: n_eff modulation)
    end

Derivative 16.9: Space Communication Waveguide Array for CubeSats

Enabling Description: A compact, robust optical waveguide array for inter-CubeSat communication, fabricated on a silicon-on-insulator (SOI) platform. The silicon waveguide core is surrounded by supporting silicon material where microstructured voids are introduced. These voids, typically air-gaps or vacuum-sealed structures ranging from 200 nm to 1 µm, are designed to create low-loss, high-confinement optical waveguides that are inherently resistant to wide temperature fluctuations and radiation effects prevalent in the space environment. The vacuum voids prevent material degradation from outgassing and minimize thermal stress-induced refractive index changes. This enables a stable and high-bandwidth optical communication link between CubeSats, allowing for data relay, distributed sensing, or formation flying in low Earth orbit.

classDiagram
    class CubeSat_Comm {
        +SOI_Platform
        +OpticalWaveguideArray
        +MicrostructuredVoids
    }
    class MicrostructuredVoids {
        +Air_Gap_or_Vacuum_Filled
        +Dimensions: 200nm-1µm
        +Function: Low Loss, Radiation Hardened, Thermal Stable
    }
    CubeSat_Comm --> OpticalWaveguideArray
    OpticalWaveguideArray --> MicrostructuredVoids

4. Integration with Emerging Tech

Derivative 16.10: AI-Driven Self-Calibrating Photonic Integrated Circuits (PICs)

Enabling Description: A Photonic Integrated Circuit (PIC) incorporating optical waveguides with microstructured voids, integrated with an AI core for self-calibration and performance optimization. The voids, sized and filled with electro-optically tunable materials (e.g., liquid crystals, MEMS-actuated air-gaps), allow for dynamic adjustment of the local effective refractive index of the supporting waveguide material. The PIC includes integrated optical power monitors and spectral analyzers (IoT sensors). An embedded AI model (e.g., a PID controller or a reinforcement learning algorithm) continuously monitors the PIC's optical output. The AI then autonomously adjusts the void properties via electrical signals to compensate for manufacturing variations, environmental drift (e.g., temperature changes), or long-term component aging, ensuring optimal spectral response, path routing, and coupling efficiency for complex optical computations or communication functions.

sequenceDiagram
    participant OpticalSignal as Optical Signal Input
    participant PIC as Microstructured Void PIC
    participant IoT_Sensors as Integrated Optical Sensors
    participant AI_Core as Embedded AI Core

    OpticalSignal->>PIC: Enters PIC
    PIC->>IoT_Sensors: Optical Output Monitored
    IoT_Sensors->>AI_Core: Send Real-time Performance Data (Power, Spectrum)
    AI_Core->>AI_Core: Analyze Data, Identify Deviations
    AI_Core-->>PIC: Adjust Electrical Signals to Tunable Voids
    PIC->>PIC: Self-Calibrates
    PIC->>Output as Optical Output: Optimized Optical Output

Derivative 16.11: IoT-Enabled Fiber Optic Sensor Network

Enabling Description: A distributed fiber optic sensing network for large-scale infrastructure monitoring (e.g., pipelines, bridges), where each segment of the fiber contains an optical waveguide structure with microstructured voids. The supporting material (e.g., polymer cladding, specialized glass) around the fiber core has voids filled with a material sensitive to external physical or chemical stimuli (e.g., strain, temperature, pH, gas presence). When a stimulus is applied, the filler material in the voids changes its refractive index or scattering properties, modulating the light propagating through the fiber. IoT gateways at various points in the network collect the optical signals. Local processing units (edge devices) with embedded analytics parse these modulations to pinpoint the location and nature of events (e.g., leaks, cracks, temperature anomalies), providing real-time, high-spatial-resolution monitoring data wirelessly.

graph TD
    A[Light Source] --> B(Fiber Optic Cable Segment 1)
    B -- Stimuli --> B1{Microstructured Void Waveguide (Sensor Node)}
    B1 --> C(Fiber Optic Cable Segment 2)
    C -- Stimuli --> C1{Microstructured Void Waveguide (Sensor Node)}
    C1 --> D(IoT Gateway)
    D -- Wireless --> E[Cloud/Local Server]
    E -- Data Analysis --> F[Infrastructure Monitoring Application]

Derivative 16.12: Blockchain for Secure Photonic Circuit Verification

Enabling Description: A system for ensuring the design integrity and manufacturing authenticity of photonic integrated circuits (PICs) featuring optical waveguides with microstructured voids. At each stage of the PIC's lifecycle, from initial design (e.g., GDSII layout, FDTD simulation parameters for voids) to fabrication (e.g., etching depths, void fill materials, refractive index measurements), metrology data and unique identifiers are cryptographically hashed. These hashes, along with timestamped operational data (e.g., performance metrics, environmental conditions), are recorded as immutable transactions on a distributed ledger (blockchain). This provides a transparent and verifiable audit trail of the PIC's entire history, ensuring that the critical void structures and their optical properties have not been tampered with or counterfeited, which is vital for high-assurance photonic components used in secure communication, defense, or quantum computing.

sequenceDiagram
    participant Design as PIC Design (Void Specs)
    participant Fab as Fabrication (Void Etch, Fill)
    participant Metrology as Metrology (n_eff, Dimensions)
    participant QC as Quality Control (Performance)
    participant Blockchain as Blockchain Network
    participant User as Certified User

    Design->>Blockchain: Commit Design Hash
    Fab->>Blockchain: Record Fab Parameters (Void Creation)
    Metrology->>Blockchain: Log Void Metrology Data
    QC->>Blockchain: Verify Performance & Integrity
    Blockchain->>User: Provide Immutable Verification
    Note right of Blockchain: Traceability of void-enabled waveguide features

5. The "Inverse" or Failure Mode

Derivative 16.13: Controlled Optical Loss for "Dark Mode" Waveguides

Enabling Description: An optical waveguide structure designed for a "dark mode" operation where light propagation is intentionally suppressed for safety or security. The supporting material adjacent to the waveguide core contains microstructured voids filled with a photochromic or thermochromic material (e.g., spiropyran-based dyes, vanadium dioxide). Under normal operation, this filler is transparent. However, upon a specific trigger (e.g., intense UV light pulse, local heating, or an applied electric field), the filler material undergoes a reversible phase transition or chemical change, causing it to become highly absorptive or highly scattering at the waveguide's operating wavelength. This rapidly increases the optical loss within the waveguide, effectively switching it to a "dark mode" to prevent signal propagation, for example, for laser safety during maintenance, preventing unauthorized data exfiltration, or signaling a system fault.

stateDiagram-V2
    state Normal_Propagation {
        Waveguide_Active
        Voids_Transparent
        Low_Loss
    }
    state Dark_Mode_Active {
        Trigger_Applied
        Voids_Absorptive/Scattering
        High_Loss
        Signal_Suppressed
    }
    Normal_Propagation --> Dark_Mode_Active: External Trigger
    Dark_Mode_Active --> Normal_Propagation: Trigger Removed (if reversible)
    Dark_Mode_Active --> Safe_State: Permanent Activation (if irreversible)
    Safe_State --> [*]

Derivative 16.14: "Reflective Shutdown" Waveguide for Laser Safety

Enabling Description: An optical waveguide structure designed for fail-safe laser safety, implementing a "reflective shutdown" mechanism. The supporting material adjacent to the waveguide core contains a periodic array of microstructured voids. These voids are filled with a liquid metal alloy (e.g., Galinstan) or a dielectric that undergoes a rapid, temperature-dependent phase transition (e.g., to a highly reflective metallic state). Upon detection of an over-power optical signal (e.g., catastrophic laser spike), a localized micro-heater or optical fuse integrated near the voids rapidly raises their temperature. This causes the void filler to transform, becoming highly reflective at the signal wavelength. The incoming light is then rapidly reflected away from sensitive components or personnel, acting as a passive, non-resetting optical fuse to prevent laser-induced damage.

sequenceDiagram
    participant LaserSource as High Power Laser
    participant Waveguide as Optical Waveguide with Voids
    participant Sensor as Over-power Sensor
    participant Microheater as Integrated Microheater
    participant ReflectedLight as Reflected Light
    participant SafetySystem as Safety System

    LaserSource->>Waveguide: Transmit Optical Signal
    Sensor->>Waveguide: Detects Over-power
    Sensor->>Microheater: Activates Microheater
    Microheater->>Waveguide: Heats Voids
    Waveguide->>ReflectedLight: Voids become Reflective, Reflects Light
    ReflectedLight->>SafetySystem: Trigger Safety Protocols

Derivative 16.15: "Soft-Failure" Waveguide for Graceful Degradation

Enabling Description: An optical waveguide structure engineered for graceful degradation, minimizing catastrophic failure under extreme conditions. A subset of the microstructured voids within the supporting waveguide material (e.g., polymer cladding) are intentionally designed with a lower mechanical strength or are filled with a reversible phase-change material that softens at elevated temperatures. Under excessive mechanical stress (e.g., bending beyond design limits) or thermal overload, these specific voids would predictably deform or undergo a phase transition, leading to a controlled, gradual increase in optical loss (e.g., through increased scattering or mode leakage) rather than an abrupt, total waveguide fracture. This "soft-failure" mode allows for a predictable and measurable reduction in signal quality, enabling system warnings, graceful shutdown, or remote re-routing of optical signals before complete system failure occurs.

graph TD
    A[Normal Operation] --> B(Low Optical Loss)
    B -- Mechanical Stress/Thermal Overload --> C(Soft-Failure Voids Deform/Change Phase)
    C --> D(Gradual Increase in Optical Loss)
    D --> E[Degradation Warning/System Graceful Shutdown]
    subgraph Soft-Failure Voids
        C1(Lower Mechanical Strength)
        C2(Reversible Phase-Change Filler)
    end

---

Derivatives of Claim 17: Heat Exchanger System with Buried Voids

Claim 17 Summary: A heat exchanger system comprising a heat generating device; a heat sink configured to dissipate heat to a surrounding medium; and an intermediate material mounted between the heat generating device and the heat sink. The intermediate material includes a plurality of buried voids configured to effect thermal conductivity of the intermediate material. Some of the buried voids are filled with thermally conductive material and others are filled with a thermally isolating material. The two types of voids being positioned to conduct heat from the heat generating device to the heat sink and to reduce thermal cross talk with other heat sensitive devices mounted on the intermediate material.

1. Material & Component Substitution

Derivative 17.1: Graphene-Foam Intermediate Layer with Liquid Metal Voids

Enabling Description: A heat exchanger system where the intermediate material is a three-dimensional (3D) graphene foam, fabricated via chemical vapor deposition (CVD) on a nickel template and subsequent etching. This graphene foam is a highly porous scaffold. Buried microstructured voids within the graphene foam are selectively filled. Some voids are injected with a liquid metal alloy (e.g., Galinstan, a eutectic alloy of gallium, indium, and tin) to create ultra-high thermal conductivity pathways (k > 50 W/mK). Other adjacent voids are filled with an aerogel (e.g., graphene aerogel, silica aerogel) or simply left as vacuum/air to create highly thermally insulating barriers (k < 0.1 W/mK). This anisotropic arrangement within the graphene foam intermediate layer provides tailored heat conduction from a heat-generating device (e.g., CPU, GPU) to a heat sink, while simultaneously isolating adjacent heat-sensitive components from thermal crosstalk.

graph TD
    A[Heat Generating Device] --> B{3D Graphene Foam Intermediate Layer}
    B --> C[Heat Sink]
    subgraph Graphene Foam Voids
        B1(Liquid Metal Filled Voids: High k)
        B2(Aerogel/Vacuum Filled Voids: Low k)
        B3(Anisotropic Heat Flow)
    end

Derivative 17.2: Ceramic-Polymer Composite with Phase Change Material (PCM) Voids

Enabling Description: An intermediate material in a heat exchanger system composed of a ceramic-polymer composite matrix (e.g., alumina nanoparticles dispersed in an epoxy resin). Buried microstructured voids within this composite are selectively filled with Phase Change Materials (PCMs) such as paraffin waxes or hydrated salts. These PCM-filled voids (e.g., 10-100 µm in diameter) are strategically positioned to absorb and release latent heat at specific operating temperatures (e.g., 60°C-80°C), providing dynamic thermal buffering for the heat-generating device (e.g., power electronics). Adjacent voids are filled with a highly porous silica foam or vacuum to act as passive thermal insulation. This combination allows for precise temperature stabilization, preventing thermal spikes and reducing cross-talk by buffering transient heat loads and isolating sensitive areas.

flowchart TD
    A[Heat Generating Device] --> B{Ceramic-Polymer Composite}
    B --> C[Heat Sink]
    subgraph Voids in Composite
        B1(PCM-Filled Voids: Thermal Buffering)
        B2(Porous Silica/Vacuum Voids: Thermal Isolation)
        B3(Dynamic Temperature Control)
    end

Derivative 17.3: Anisotropic Graphite Sheet with Carbon Nanotube-Filled Voids

Enabling Description: A heat exchanger system employing an intermediate material made of highly anisotropic pyrolytic graphite sheets. Microstructured voids are created and patterned within this graphite sheet using laser ablation or focused ion beam (FIB) etching. Select voids are then filled with vertically aligned carbon nanotube (CNT) arrays, grown in situ via CVD, creating ultra-high thermal conductivity pathways (k > 1000 W/mK in the aligned direction) from a heat-generating device to the heat sink. Other voids, adjacent to these CNT pathways, are filled with a low-thermal-conductivity polymer foam (e.g., polyimide foam) to establish strong lateral thermal barriers. This precise, anisotropic engineering of thermal pathways and barriers optimizes heat spreading and localization, effectively directing heat away from critical components while preventing thermal cross-talk to sensitive devices.

graph TD
    A[Heat Generating Device] --> B{Anisotropic Graphite Sheet Intermediate Layer}
    B --> C[Heat Sink]
    subgraph Voids in Graphite
        B1(Vertically Aligned CNT-Filled: Ultra High k)
        B2(Polymer Foam-Filled: Low k Lateral Barriers)
        B3(Anisotropic Heat Flow Control)
    end

2. Operational Parameter Expansion

Derivative 17.4: Cryogenic Heat Exchanger for Superconducting Qubits

Enabling Description: A heat exchanger system for superconducting qubits in a quantum computer, operating at millikelvin temperatures. The intermediate material, fabricated from a low-thermal expansion material like silicon or sapphire, contains buried microstructured voids, sized between 10 µm and 100 µm. Some voids are filled with ultra-high purity copper powder or solid diamond microparticles embedded in a low-Teflon matrix for conducting heat from the qubits to a dilution refrigerator's cold stage. Other voids, strategically placed around individual qubits, are evacuated to near-perfect vacuum or filled with aerogels (e.g., silica aerogel) to provide extreme thermal isolation. This precise thermal management prevents quantum decoherence by maintaining stable millikelvin temperatures for the qubits while efficiently routing parasitic heat to the cryocooler.

stateDiagram-V2
    [*] --> Qubit_Operating: mK Temperatures
    Qubit_Operating --> Heat_Generated
    Heat_Generated --> Intermediate_Material
    state Intermediate_Material {
        Conductive_Voids: High Purity Copper/Diamond
        Isolating_Voids: Vacuum/Aerogel
        Thermal_Routing
    }
    Intermediate_Material --> Dilution_Refrigerator: Heat Removal
    Intermediate_Material --> Qubit_Isolation: Prevent Crosstalk

Derivative 17.5: High-Temperature Thermoelectric Generator (TEG) with Graded Thermal Voids

Enabling Description: A thermoelectric generator (TEG) designed for high-temperature waste heat recovery (e.g., 500-1000°C). The intermediate material, composed of a high-ZT thermoelectric alloy (e.g., SiGe, Half-Heusler alloys), incorporates buried microstructured voids with a graded density and filler composition. Voids near the hot side are fewer and filled with a high-thermal-conductivity material (e.g., micro-diamond powder) to maximize heat transfer across the junction. Voids near the cold side are more numerous and filled with a low-thermal-conductivity, high-temperature stable material (e.g., porous ceramic, vacuum) to maintain a steep thermal gradient. Laterally, voids filled with insulating material prevent thermal cross-talk between individual TEG elements, thereby enhancing the overall thermoelectric conversion efficiency and power density by optimizing the temperature differential and isolating elements.

graph TD
    A[Hot Side (Waste Heat)] --> B{Intermediate TEG Material w/ Graded Voids}
    B --> C[Cold Side (Heat Sink)]
    B --> D[Electrical Output]
    subgraph Graded Voids
        B1(Hot Side: High k fillers, low density)
        B2(Cold Side: Low k fillers, high density)
        B3(Lateral isolation)
    end

Derivative 17.6: Spacecraft Radiator Panel with Evacuated Multi-Layer Voids

Enabling Description: A spacecraft radiator panel for thermal control in extreme space environments. The panel's intermediate material is a lightweight composite (e.g., carbon fiber reinforced polymer) with embedded, precisely structured, evacuated multi-layer insulation (MLI) within microstructured voids. These voids, sized from 1 mm to 1 cm, are meticulously evacuated to ultra-high vacuum and contain multiple thin, low-emissivity radiation shields (e.g., aluminized Mylar). This MLI-in-voids configuration drastically reduces all three modes of heat transfer: conduction (vacuum), convection (no medium), and radiation (MLI shields), achieving extreme thermal isolation (e.g., effective k < 0.001 W/mK). The voids are positioned to isolate heat-generating components from heat-sensitive ones, and to direct waste heat to specific radiator surfaces while preventing heat leakage to other parts of the spacecraft.

classDiagram
    class SpacecraftRadiator {
        +HeatGeneratingDevice
        +HeatSink
        +IntermediateMaterial
    }
    class IntermediateMaterial {
        +LightweightComposite
        +EvacuatedMultiLayerVoids
        +ExtremeThermalIsolation
    }
    class EvacuatedMultiLayerVoids {
        +Size: 1mm-1cm
        +Vacuum
        +MultiLayerInsulation
        +Function: Reduce Conduction, Convection, Radiation
    }
    SpacecraftRadiator --> IntermediateMaterial
    IntermediateMaterial --> EvacuatedMultiLayerVoids

3. Cross-Domain Application

Derivative 17.7: Smart Packaging for Temperature-Sensitive Pharmaceuticals

Enabling Description: Smart packaging for temperature-sensitive pharmaceuticals (e.g., vaccines, biologics) during transport and storage. The packaging's intermediate material is a biodegradable polymer matrix containing buried microstructured voids. Some voids are filled with a cryogel (e.g., cross-linked poly(N-isopropylacrylamide) (PNIPAm) hydrogel) designed to maintain a specific low temperature range (e.g., 2-8°C) by absorbing heat. Other adjacent voids are filled with a high-performance insulating foam (e.g., polyurethane foam) or vacuum to prevent external temperature fluctuations from affecting the internal microclimate. This creates localized, stable temperature zones around the medication, ensuring drug efficacy and reducing spoilage. Integrated temperature sensors communicate data wirelessly to a monitoring system, enabling dynamic adjustment of void properties if active elements are used.

flowchart TD
    A[External Temperature Fluctuations] --> B{Smart Packaging Intermediate Material}
    B --> C[Temperature Sensitive Pharmaceutical]
    B -- Maintains Temp --> C
    B -- Blocks Heat --> C
    subgraph Buried Voids
        B1(Cryogel Filled: Cooling/Temp Buffering)
        B2(Insulating Foam/Vacuum Filled: Thermal Isolation)
    end

Derivative 17.8: Automotive Battery Thermal Management System

Enabling Description: A thermal management system for electric vehicle (EV) battery packs. The intermediate material is placed between individual battery cells and/or between cell modules. This material comprises a ceramic-polymer composite with buried microstructured voids. Some voids are strategically filled with a highly thermally conductive, electrically insulating dielectric fluid (e.g., mineral oil, silicone oil with boron nitride nanoparticles) to efficiently wick and distribute heat away from localized hotspots on the battery cells. Other adjacent voids are filled with a fire-retardant, thermally isolating foam (e.g., aerogel-impregnated foam) to prevent thermal runaway propagation between cells. This precise thermal zoning ensures uniform temperature distribution across the battery pack, prolongs battery lifespan, and enhances safety.

graph TD
    A[Battery Cell (Heat Source)] --> B{Intermediate Material w/ Buried Voids}
    B --> C[Adjacent Battery Cell / Heat Sink]
    subgraph Buried Voids
        B1(Conductive Dielectric Fluid: Heat Spreading)
        B2(Fire-Retardant Insulating Foam: Thermal Isolation)
        B3(Prevents Thermal Runaway)
    end

Derivative 17.9: Building Envelope Insulation with Tunable Thermal Voids

Enabling Description: Building envelope insulation panels incorporating an intermediate material with buried microstructured voids for dynamic thermal management. Some voids are filled with a phase-change material (PCM) (e.g., salt hydrates, paraffin waxes) to provide significant thermal mass, absorbing heat during the day and releasing it at night to stabilize indoor temperatures. Other voids, adjacent to these, are vacuum-sealed or filled with a low-conductivity noble gas (e.g., argon, krypton) to act as highly efficient static thermal insulators. The positioning and filling of these voids are optimized to dynamically adjust the building's thermal resistance (R-value) based on ambient conditions. This reduces energy consumption for heating and cooling, improving building efficiency and occupant comfort.

flowchart TD
    A[Outdoor Temperature] --> B{Building Insulation Panel w/ Tunable Voids}
    B --> C[Indoor Temperature]
    subgraph Buried Voids
        B1(PCM-Filled Voids: Thermal Mass)
        B2(Vacuum/Noble Gas Voids: Insulation)
        B3(Dynamic R-value Adjustment)
    end

4. Integration with Emerging Tech

Derivative 17.10: AI-Controlled Active Thermal Management Unit

Enabling Description: An active thermal management unit for high-performance computing (HPC) or power electronics, utilizing an intermediate material with electro-thermally tunable voids. The voids are filled with electro-rheological fluids (ERFs) or contain micro-electromechanical systems (MEMS) actuated shutters. An array of IoT temperature sensors embedded within the heat-generating device and the intermediate material feeds real-time thermal data to a centralized AI controller. The AI (e.g., a neural network with predictive capabilities) analyzes this data to anticipate thermal hotspots and dynamically adjusts the thermal conductivity profile of the voids. For ERF-filled voids, the AI applies electrical fields to change the fluid's viscosity and thus thermal conductivity. For MEMS-shutter voids, the AI opens/closes shutters to control heat flow, precisely guiding heat to the heat sink and preventing thermal cross-talk, optimizing component lifespan and performance.

sequenceDiagram
    participant HeatDevice as Heat Generating Device
    participant IoT_Sensors as IoT Temperature Sensors
    participant Intermediate as Intermediate Material w/ Tunable Voids
    participant AI_Controller as AI Controller
    participant HeatSink as Heat Sink

    HeatDevice->>IoT_Sensors: Generates Heat
    IoT_Sensors->>AI_Controller: Send Real-time Thermal Data
    AI_Controller->>AI_Controller: Analyze Data, Predict Hotspots
    AI_Controller->>Intermediate: Adjust Electrical Signals to Voids (ERF/MEMS)
    Intermediate->>HeatSink: Dynamically Route Heat
    Intermediate->>HeatDevice: Maintain Optimal Temp

Derivative 17.11: Blockchain-Enabled Thermal Footprint Tracking for Servers

Enabling Description: A data center thermal management system incorporating server racks with intermediate materials that use US11621360's void-based thermal management. Each server unit has embedded IoT sensors that monitor its thermal profile (e.g., CPU, memory, PSU temperatures, airflow), energy consumption, and the operational status of the void-based intermediate materials (e.g., thermal conductivity state, void integrity). This real-time, comprehensive data is cryptographically hashed and recorded as immutable transactions on a consortium blockchain. This provides a transparent and verifiable audit trail for the server's thermal footprint, energy efficiency, and compliance with environmental regulations. It also enables dynamic capacity planning, optimization of cooling strategies, and robust tracking for carbon credit schemes and component lifecycle management.

graph TD
    A[Server Unit w/ Voided TIM & IoT Sensors] --> B(Real-time Thermal Data)
    B --> C(Cryptographic Hashing Unit)
    C -- Signed Data --> D(Blockchain Network)
    D --> E[Immutable Thermal Footprint Log]
    E --> F[Data Center Optimization / Compliance]

Derivative 17.12: Self-Healing Thermal Interface Material (TIM) with Responsive Voids

Enabling Description: A heat exchanger system incorporating a self-healing thermal interface material (TIM) as the intermediate layer between a heat-generating device and a heat sink. The TIM consists of a polymer matrix with buried microstructured voids. These voids are filled with a liquid metal alloy (e.g., Galinstan) or a low-viscosity, thermally conductive self-healing polymer. When a micro-crack or delamination occurs in the TIM due to thermal cycling or mechanical stress, the liquid filler material within the voids is released into the damaged region. This self-healing action rapidly restores the thermal pathway, either by refilling the void with a high-conductivity liquid metal or by chemically bonding with the polymer to repair the matrix. This prolongs the operational lifespan of the device by maintaining optimal thermal contact and preventing catastrophic thermal runaway.

flowchart TD
    A[Heat Generating Device] --> B{Self-Healing TIM w/ Responsive Voids}
    B -- Crack/Delamination --> C(Void Filler Release)
    C -- Self-Repair --> B
    B --> D[Heat Sink]
    subgraph Voids
        B1(Liquid Metal/Self-Healing Polymer Filler)
        B2(Function: Restore Thermal Pathway)
    end

5. The "Inverse" or Failure Mode

Derivative 17.13: Thermal Fuse Intermediate Material for Overheat Protection

Enabling Description: A heat exchanger system incorporating an intermediate material designed to act as a passive thermal fuse for overheat protection. The intermediate material, made of a ceramic or polymer composite, contains buried microstructured voids. These voids are filled with a sacrificial material (e.g., low-melting-point wax, a sublimable polymer) engineered to undergo a rapid phase change (melting or sublimation) at a specific critical temperature (e.g., 10-20°C above normal operating temperature). Upon reaching this critical temperature, the sacrificial material within the voids transforms, creating a network of air gaps or vacuum pockets that drastically increase the thermal resistance of the intermediate layer. This irreversible change effectively decouples the heat-generating device from the heat sink, passively limiting the maximum temperature and preventing catastrophic thermal damage to the heat-generating device.

stateDiagram-V2
    [*] --> Normal_Operation: Heat Flows
    Normal_Operation --> Overheat_Condition: Temperature Exceeds Threshold
    Overheat_Condition --> Void_Filler_Transforms: Sacrificial Material Changes Phase
    Void_Filler_Transforms --> Thermal_Decoupling: Air Gaps Increase Thermal Resistance
    Thermal_Decoupling --> Fail_Safe_Shutdown: Device Protected, Irreversible
    Fail_Safe_Shutdown --> [*]

Derivative 17.14: Low-Power "Idle Mode" Thermal Management

Enabling Description: A heat exchanger system for electronic devices (e.g., laptops, smartphones) that features an intermediate material with voids designed for "idle mode" thermal management. The buried microstructured voids within the intermediate material (e.g., a silicone matrix) are filled with a thermoreversible material that solidifies into a highly insulating state when the heat-generating device (e.g., CPU) is in a low-power "idle mode" (i.e., operating below a certain temperature threshold). This solidification creates highly insulating barriers around the inactive components, passively reducing heat leakage from the device to the ambient environment. When the device transitions to active mode and generates more heat, the filler material melts or becomes more conductive, allowing efficient heat transfer. This passive switching mechanism conserves energy by minimizing thermal losses during idle periods.

flowchart TD
    A[Heat Generating Device (CPU)] --> B{Intermediate Material w/ Thermoreversible Voids}
    B -- Idle Mode (Low Temp) --> C(Filler Solidifies: High Insulation)
    C --> D[Reduced Heat Leakage / Energy Conservation]
    B -- Active Mode (High Temp) --> E(Filler Melts: High Conductivity)
    E --> F[Efficient Heat Dissipation]

Derivative 17.15: De-Coupling Intermediate Layer for Catastrophic Failure Isolation

Enabling Description: A heat exchanger system designed to prevent the propagation of catastrophic thermal runaway. The intermediate material (e.g., between a battery cell or a power transistor) incorporates a network of buried microstructured voids. Some of these voids are filled with a frangible, low-melting-point alloy (e.g., Wood's metal, field's metal). In the event of a localized catastrophic thermal runaway (e.g., a short circuit in a battery cell, excessive current in a power transistor) that rapidly exceeds a critical temperature threshold, the alloy within these specific voids quickly melts. This melting creates a physical gap and a highly insulating air/vacuum barrier, effectively de-coupling the failing component from adjacent devices and the heat sink. This localized thermal isolation prevents the runaway event from spreading, enhancing system safety and preventing widespread damage.

sequenceDiagram
    participant Component as Heat Generating Component
    participant Intermediate as Intermediate Layer w/ Frangible Voids
    participant Neighbor as Adjacent Component
    participant HeatSink as Heat Sink

    Component->>Intermediate: Generates Heat
    Component->>Component: Catastrophic Thermal Runaway
    Intermediate->>Intermediate: Frangible Voids Melt
    Intermediate->>Component: Thermal Decoupling (Isolation)
    Intermediate->>Neighbor: Prevents Runaway Propagation
    Intermediate->>HeatSink: Remaining Heat Dissipation

---

Combination Prior Art Scenarios

Here are three combination prior art scenarios where US Patent 11,621,360 is combined with existing open-source standards, demonstrating obviousness for certain applications.

Scenario 1: Microstructure-Enhanced Silicon Photodetector + IEEE 802.3 Ethernet Standard for Optical Transceivers

Enabling Description: The development of high-speed optical transceivers compliant with the IEEE 802.3 Ethernet standard (e.g., 10GbE, 25GbE, 100GbE for multimode fiber links at 850 nm) traditionally requires photodiodes (PDs) or avalanche photodiodes (APDs) made of III-V semiconductors (e.g., GaAs, InGaAs) due to their high direct bandgap absorption at these wavelengths and fast response. However, these are often more expensive and less CMOS-compatible than silicon.
The microstructure-enhanced silicon photodetector described in US Patent 11,621,360 (Claim 1) teaches the use of silicon microstructures (pillars, holes, voids) to dramatically increase the effective absorption coefficient of silicon at wavelengths like 850 nm, enabling high quantum efficiency with a thin absorption layer. This thin layer directly addresses the transit-time limitations for high bandwidth (e.g., >10 Gb/s) and reduces capacitance for lower RC time constants, overcoming key limitations of conventional bulk silicon detectors.

A person having ordinary skill in the art (PHOSITA) in optoelectronics and network hardware, seeking to reduce the cost and improve the manufacturability of 850 nm optical transceivers, would find it obvious to integrate such a microstructure-enhanced silicon photodetector as the receiver component into an optical transceiver module. The direct motivation is to leverage silicon's low cost and CMOS compatibility while meeting the stringent performance requirements (e.g., minimum responsivity, bandwidth, jitter) specified by the open IEEE 802.3 standard for short-reach optical links. This combination allows for a high-performance, cost-effective silicon-based alternative to III-V detectors for standard compliant Ethernet applications.

flowchart TD
    A[IEEE 802.3 Optical Signal] --> B(Optical Transceiver Module)
    B --> C{Microstructure-Enhanced Si Photodetector (Claim 1)}
    C --> D(Transimpedance Amplifier)
    D --> E(CDR / Electrical Interface)
    E --> F[Standard Ethernet Link]
    subgraph Photodetector
        C1(Si Microstructures: Pillars/Holes/Voids)
        C2(Enhanced Absorption @ 850nm)
        C3(High QE, Low Capacitance)
    end

Scenario 2: Photovoltaic Device with Buried Voids + Open-Source Energy Management System (e.g., OpenEMS)

Enabling Description: US Patent 11,621,360 (Claim 14) describes a photovoltaic (PV) device with a semiconductor material having buried microstructured voids to enhance absorption and increase conversion efficiency. This improves the fundamental performance of the solar cell itself.
OpenEMS (Open Energy Management System) is an open-source software platform for monitoring, controlling, and optimizing energy systems, including solar PV installations. It provides interfaces for data acquisition, analytics, and control strategies to manage energy flow in smart grids or microgrids.

A PHOSITA in renewable energy systems and software integration, motivated to deploy more efficient and intelligently managed solar power, would find it obvious to integrate these two technologies. Specifically, PV modules incorporating the buried void technology (Claim 14) would be equipped with standard communication interfaces (e.g., Modbus TCP, MQTT) to transmit their enhanced power output and detailed performance metrics (e.g., module temperature, efficiency, irradiance levels, possibly even void integrity diagnostics via embedded sensors) to an OpenEMS instance. OpenEMS would then leverage this high-fidelity data from the efficient PV cells to perform advanced optimizations, such as load balancing, grid synchronization, and predictive maintenance algorithms. This combination results in a highly efficient and intelligently managed solar energy generation system, utilizing the enhanced energy capture from the buried voids and the open-source platform's robust control capabilities.

flowchart TD
    A[Sunlight] --> B{PV Module w/ Buried Voids (Claim 14)}
    B -- Enhanced Power Output --> C(Module Controller/Data Logger)
    C -- Data (Modbus/MQTT) --> D[OpenEMS (Open-Source EMS)]
    D --> E(Grid/Local Load Management)
    subgraph PV Module
        B1(Semiconductor Material)
        B2(Microstructured Buried Voids)
        B3(Enhanced Conversion Efficiency)
    end

Scenario 3: Optical Waveguide with Microstructured Voids + W3C WebAssembly (Wasm) for Edge Processing in Photonic AI

Enabling Description: US Patent 11,621,360 (Claim 16) teaches an optical waveguide structure where microstructured voids in the supporting semiconductor material are configured to alter its effective refractive index. This precise refractive index engineering is crucial for guiding light efficiently and implementing complex optical functions in Photonic Integrated Circuits (PICs).
WebAssembly (Wasm) is a W3C standard for a portable binary instruction format designed for efficient execution, often used for high-performance client-side logic on the web or in embedded/edge environments due to its small size and near-native speed.

A PHOSITA in integrated photonics and edge computing, aiming to develop energy-efficient and flexible AI accelerators, would find it obvious to combine these two concepts. An optical waveguide structure (Claim 16), utilizing microstructured voids for optimized light routing and manipulation, would be integrated into a photonic AI accelerator chip (e.g., for optical neural networks). The control logic for this photonic AI chip, including dynamic adjustments to the void properties (if tunable) for reconfigurable optical pathways, or the execution of inference models using the photonic compute units, would be implemented via WebAssembly modules. These Wasm modules could run on an embedded microcontroller co-located with the PIC. This combination enables highly efficient, low-latency AI inference directly at the optical layer, with the flexibility and portability of WebAssembly for deploying and updating AI algorithms on edge devices.

sequenceDiagram
    participant Wasm as WebAssembly Module (AI Control Logic)
    participant Edge_MCU as Edge Microcontroller
    participant PIC as Photonic Integrated Circuit (Optical Waveguide w/ Voids)
    participant Sensors as Optical/Input Sensors
    participant Output as AI Inference Result

    Sensors->>PIC: Input Optical Data
    Edge_MCU->>Wasm: Load AI Control Logic
    Wasm->>PIC: Send Control Signals (e.g., tune void properties)
    PIC->>PIC: Perform Optical AI Computation
    PIC->>Edge_MCU: Send Processed Optical Data
    Edge_MCU->>Wasm: Execute Inference Algorithm
    Wasm->>Output: Produce AI Inference Result
    Note right of PIC: Microstructured voids enable precise light control