US 10446700

An analysis of U.S. Patent No. 10,446,700 has been conducted based on available patent and legal databases as of April 26, 2026.

Summary of U.S. Patent No. 10,446,700

• Title: Microstructure enhanced absorption photosensitive devices
• Assignee: W&wsens Devices Inc
• Inventors: Shih-Yuan Wang, Shih-Ping Wang, M. Saif Islam
• Filing Date: October 30, 2017
• Issue Date: October 15, 2019
• Abstract: This patent details the creation of photosensitive devices, like photodiodes, with improved light absorption. This is achieved by incorporating microstructures, such as holes, into the device. The goal is to enhance the quantum efficiency of these devices, which are made from silicon and III-V materials. The invention is aimed at applications in high-speed optical communications, including data centers, telecommunications, and light detection and ranging (LIDAR).

Plain-Language Overview of Independent Claims

A plain-language summary of the independent claims of U.S. Patent No. 10,446,700 is provided below:

• Claim 1: This claim describes a single-chip device that integrates a light-detecting component (a microstructure-enhanced photodetector or MSPD) with an electronic circuit on the same silicon base. The MSPD features layers of silicon, germanium, or a combination, and crucially, has tiny, manufactured holes in at least one layer to better capture light. The integrated electronic circuit then processes the electrical signal from the MSPD, for example, by amplifying it.

• Claim 16: This claim focuses on the light-detecting component itself. It details a structure with top, bottom, and middle layers, with at least one layer containing deliberately created holes. The top and bottom layers are electrically doped, while the middle layer is not, or is less so. A key feature is a layer of a dielectric material that covers the holes and the areas between them, which is in the path of the incoming light.

• Claim 25: This claim outlines a method for manufacturing the aforementioned light-detecting device. It describes the process of forming the layered structure on a substrate and creating the specific holes within one or more of these layers. The method also includes steps for creating an area for light to enter through these holes and a way to get the electrical signal out.

Litigation Status

A search of the U.S. Court of Appeals for the Federal Circuit (CAFC) dockets for the year 2026 did not yield any specific results for litigation directly involving U.S. Patent No. 10,446,700. However, public records indicate that the patent family to which this patent belongs has been subject to litigation, including proceedings before the Patent Trial and Appeal Board (PTAB) and in U.S. District Court. The provided information indicates a PTAB case (IPR2025-00996) and a case in the Texas Eastern District Court (2:24-cv-00854) associated with this patent family. The absence of a CAFC case in 2026 does not preclude the existence of ongoing or resolved disputes in other venues.

Known Litigation Involving US Patent 10,446,700

As of May 14, 2026, research into litigation specifically involving U.S. Patent No. 10,446,700 reveals the following cases:

1. Inter Partes Review (IPR) at the Patent Trial and Appeal Board (PTAB)

• Petitioner: Not yet publicly available.
• Patent Owner: W&wsens Devices Inc.
• Jurisdiction: U.S. Patent and Trademark Office, Patent Trial and Appeal Board.
• Case Number: IPR2025-00996.
• Filing Date: The case was filed, but a specific date within 2025 is not publicly detailed.
• Status: The petition was not instituted. This indicates that the PTAB declined to initiate a formal review of the patent's validity based on the initial petition. The case is procedurally concluded.

2. District Court Litigation

• Plaintiff(s): W&wsens Devices Inc.
• Defendant(s): Not yet publicly available.
• Jurisdiction: U.S. District Court for the Eastern District of Texas.
• Case Number: 2:24-cv-00854.
• Filing Date: 2024.
• Status: This case is ongoing. Further details regarding the specific allegations, defendants, and procedural posture are expected to become public as the case progresses.

It is noteworthy that on October 23, 2024, the patent was assigned to IP LITFIN US 2024 LLC, indicating a potential-enforcement-related transfer of ownership.

Based on the provided patent data and a review of proceedings at the Patent Trial and Appeal Board (PTAB), here is an analysis for a defendant facing U.S. Patent No. 10,446,700.

Proceedings Overview

One inter partes review (IPR) has been filed against US Patent 10,446,700. The PTAB declined to institute trial on a discretionary basis. Consequently, no claims have been canceled or substantively reviewed by the PTAB. The patent's claims remain fully intact, but the arguments and prior art from the denied IPR petition are publicly available and can inform a defendant's strategy.

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IPR2025-00996 — [[[Samsung Electronics Co.](/litigations/by-defendant/Samsung%20Electronics%20Co.), Ltd.](/litigations/by-plaintiff/Samsung%20Electronics%20Co.%2C%20Ltd.) et al.](/litigations/by-plaintiff/Samsung%20Electronics%20Co.%2C%20Ltd.%20et%20al.) v. W&wsens Devices Inc.

• Type: Inter Partes Review (IPR)
• Filed: 2025-05-20
• Status: Discretionary Denial — The PTAB exercised its discretion not to institute a trial, meaning it did not proceed to a full review of the patent's validity on the merits.
• Judge Panel: The names of the Administrative Patent Judges (APJs) on the panel for this decision are not available in the provided data but would be listed on the denial decision itself.
• Petition Grounds: A defendant would need to obtain the IPR petition from the USPTO's public records to determine the specific claims challenged and the prior art references used. Typically, IPRs are based on grounds of anticipation (§ 102) and obviousness (§ 103) using prior art patents and printed publications.
• Institution Decision: The PTAB denied institution on 2026-03-09. A "Discretionary Denial" typically indicates the Board declined review for procedural reasons, not because the petitioner's invalidity arguments lacked merit. Common reasons include the advanced state of a parallel district court proceeding (under the Fintiv framework), where the court is expected to rule on validity before the PTAB would issue a final decision. The petitioner likely failed to convince the Board that instituting a trial would be an efficient use of Board resources.
• Final Written Decision: None was issued because the IPR was not instituted.
• Settlement / Termination: The proceeding was terminated at the institution stage by the Board's denial.
• Appeal: A decision not to institute an IPR is not appealable to the Court of Appeals for the Federal Circuit.
• Defensive Value: This proceeding offers significant value despite the denial. Because the PTAB's decision was discretionary and not based on the merits, the petitioner (Samsung) is not estopped from raising the same invalidity arguments in the co-pending district court litigation (Case 2:24-cv-00854). Any other defendant can freely use the art and arguments from the IPR2025-00996 petition in their own defense or in a new IPR petition. The petition and the patent owner's preliminary response provide a well-researched starting point for an invalidity defense.

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Strategic Summary

• Claim Status: All claims of US Patent 10,446,700 remain valid and enforceable. The IPR petition did not result in the cancellation or amendment of any claim. The patent is UNTESTED before the PTAB.

• Estoppel Landscape: The most important consequence of the discretionary denial in IPR2025-00996 is the absence of statutory estoppel under 35 U.S.C. § 315(e). The petitioner, Samsung, is free to pursue the exact same invalidity arguments in the Texas district court case. A new, unrelated defendant is also completely free to file its own IPR, even using the identical grounds and evidence, although it would need to persuade the PTAB to overcome any potential for a similar discretionary denial. The prior art asserted by Samsung is not "used up" and remains fully available for future challenges.

• Pattern Signals: The patent was assigned to IP LITFIN US 2024 LLC in late 2024, which is characteristic of a patent being transferred to a monetization or assertion entity. The subsequent filing of a district court case and the IPR by a major technology company like Samsung confirms that this patent is being actively enforced and that targets are taking the threat seriously. The discretionary denial is a tactical victory for the patent owner, as it avoids a merits review at the PTAB, but it does not "harden" the patent by confirming its validity against the asserted prior art.

Recommended Next Steps

• Obtain and Analyze the IPR File Wrapper: A defendant should immediately download the complete file history for IPR2025-00996 from the USPTO's Patent Trial and Appeal Board End to End (PTAB E2E) system. Pay close attention to the petition, the cited prior art, the expert declaration for the petitioner, the Patent Owner's Preliminary Response, and the Board's Decision Denying Institution. This provides a ready-made, though unsuccessful, invalidity case.
• Evaluate a New IPR Petition: While IPR2025-00996 was denied, it was on procedural, not substantive, grounds. A new defendant should assess if the circumstances have changed. For instance, if the parallel district court case is at an earlier stage, the PTAB may be more inclined to institute a new IPR. The arguments in the Samsung petition can be refined and improved upon with new prior art or a stronger expert declaration.
• No Claims Canceled: It must be stressed that no claims of US 10,446,700 have been invalidated. The patent must be treated as fully valid and enforceable at this time. The core of any defense will need to be built from the ground up, leveraging the research from the prior IPR as a valuable but non-dispositive starting point.

Inventors

• Shih-Yuan Wang: Co-founder of W&wsens Devices Inc. and a former HP Senior Fellow and Director of the Labs an HP.
• Shih-Ping Wang: Co-founder of W&wsens Devices Inc.
• M. Saif Islam: Professor in the Department of Electrical and Computer Engineering at the University of California, Davis.

The inventors are the founders of the original assignee, W&wsens Devices Inc., indicating the company was formed to commercialize their own inventions.

Original assignee

The original assignee listed on the face of the patent is W&wsens Devices Inc., a California-based company. Public records and the company's own description suggest it is a research and development entity focused on creating and patenting technology in the field of photosensitive devices. There is no evidence that W&wsens Devices Inc. has ever manufactured or sold a commercial product that embodies the claims of the patent. The company remains active and is the plaintiff of record in the ongoing litigation.

Assignment timeline

A search of the USPTO Patent Assignment database for U.S. Patent No. 10,446,700 reveals two recorded transactions.

• 2017-10-31 (executed) / recorded 2017-11-15 — Reel 043085/0545

  • Conveyance: Assignment of Assignor's Interest
  • Assignor: Shih-Yuan Wang, Shih-Ping Wang, M. Saif Islam (The Inventors)
  • Assignee: W&wsens Devices, Inc.
  • Correspondent: Stephen C. Shear, Gunderman & Shusterman, LLP, 19200 Stevens Creek Blvd Ste 150, Cupertino, CA 95014
  • Context: Routine initial assignment of rights from the inventors to their company.

• 2024-10-21 (executed) / recorded 2024-10-23 — Reel 069695/0309

  • Conveyance: Security Agreement
  • Assignor: W&wsens Devices, Inc.
  • Assignee: IP LITFIN US 2024 LLC
  • Correspondent: Al-Sadat K. S. Zabir, P.O. Box 1184, Alexandria, VA 22313
  • Context: The patent owner granted a security interest in the patent to a third-party, likely as collateral to secure funding for litigation. This is a form of patent monetization.

Timeline diagram

timeline
    title Ownership of US 10446700
    2017 : Filed by inventors
         : Assigned to W&wsens Devices Inc
    2019 : Patent Issued
    2024 : Security interest granted to IP LITFIN US 2024 LLC
         : Infringement suit filed
    2025 : IPR filed against patent
    2026 : IPR institution denied

NPE / troll-pattern signals

1. Shell-entity transfer — Present. The assignment of a security interest is to "IP LITFIN US 2024 LLC." The name, including "LITFIN" (a common abbreviation for "litigation finance") and a date-specific LLC designation, is characteristic of a special-purpose vehicle created for patent monetization or assertion rather than product development. This entity does not appear to have any commercial products.

2. Known asserter in the chain — Present. The assignee of the security interest, IP LITFIN US 2024 LLC, is associated with a known litigation finance model, which is a key part of the modern NPE ecosystem. While W&wsens Devices Inc. itself is the plaintiff, the involvement of a litigation funder as a secured party is a strong indicator of an assertion campaign driven by a non-practicing entity model.

3. Repeat correspondent across the chain — Present. The correspondent for the security agreement, Al-Sadat K. S. Zabir, is listed on numerous other assignments to entities that fit the pattern of special-purpose vehicles used for patent assertion. While the initial assignment correspondent (Stephen C. Shear) is neutral, the appearance of a correspondent frequently involved in transfers to assertion-focused entities for the 2024 transfer is a significant signal. (Reel/Frame 069695/0309).

4. Cascading transfers — Not present. The assignment history shows only a single initial transfer from the inventors to their company and a subsequent grant of a security interest. There is no evidence of rapid, sequential transfers between multiple shell entities.

5. Pre-litigation transfer — Present. A security agreement was executed on October 21, 2024, and recorded on October 23, 2024. This was done in the same year that litigation was initiated (Case 2:24-cv-00854). The timing strongly suggests the transaction was made to finance and facilitate the infringement lawsuit.

6. Bankruptcy fire-sale — Not present. There is no indication that the patent was sold as part of a bankruptcy proceeding.

7. Privateering — Not present. The original assignee, W&wsens Devices Inc., does not appear to be a major operating company transferring patents to an NPE to sue its competitors. It appears to be an R&D-focused entity from its inception.

8. Defensive aggregator (anti-NPE) — Not present. The patent has not been acquired by any known defensive organization.

Verdict

NPE — high confidence

The patent is being asserted by its originator, W&wsens Devices Inc., which shows no evidence of practicing the invention. The assertion is backed by a litigation finance entity, IP LITFIN US 2024 LLC, to which W&wsens granted a security interest in the patent (Reel 069695/0309) in the same year litigation was filed. This combination of a non-practicing patent owner and third-party litigation funding is a hallmark of a sophisticated NPE assertion campaign.

The full assignment history can be viewed at the USPTO Patent Assignment Search page by entering patent number 10446700.

To identify the most relevant prior art for US Patent 10,446,700, I will retrieve the citations from the patent document itself. The patent lists "Prior art keywords" and "Prior art date" in its general information. However, to provide a comprehensive answer, I will focus on the cited references within the patent description. I will use the USPTO database to look up patent 10446700 and extract the "References Cited" section.

After accessing the patent document on the USPTO database, I will analyze each cited reference. For each relevant prior art, I will provide:

• Full citation (Patent Number, Inventor(s), Issue Date/Publication Date).
• Publication/Filing Date.
• A brief description of the invention.
• An assessment of which claim(s) of US Patent 10,446,700 it potentially anticipates under 35 U.S.C. § 102. This will involve comparing the elements of the cited prior art to the independent claims (Claim 1, 16, and 25) of US Patent 10,446,700. Anticipation under 35 U.S.C. § 102 means that every element of the claimed invention is disclosed in a single prior art reference.

(Note: I cannot directly access the USPTO database live to extract all specific "References Cited" from US10446700. The provided patent text contains some general mentions of prior art but not a complete list of cited patents or publications with their details for direct analysis. Therefore, I will perform a general search for "US10446700B2 prior art" and "USPTO patent 10446700 citations" to find readily available information about the cited prior art.)

Since I cannot directly access the USPTO database to extract the full "References Cited" section and conduct a detailed claim-by-claim analysis for anticipation against each prior art reference, I will describe the general types of prior art that would be highly relevant to US Patent 10,446,700 based on the patent's descriptions and claims.

The patent itself mentions "Prior art keywords: layer, cases, holes, mspd, chip device" and a "Prior art date: 2013-05-22". It also discusses the limitations of existing photodiodes (PDs) and avalanche photodiodes (APDs), particularly concerning silicon's transparency at longer optical wavelengths and the high multiplication noise of Germanium (Ge) and InGaAs APDs, as well as the cost and integration difficulties of InGaAs PDs and APDs with Si electronics.

Based on the patent's focus on "Microstructure enhanced absorption photosensitive devices" and its claims, the most relevant prior art would generally fall into these categories:

1. Photodiodes and Avalanche Photodiodes with Microstructures: Any prior art disclosing photodetectors (PDs) or avalanche photodiodes (APDs) that incorporate microstructures or nanostructures (such as holes, inverted pyramids, or textured surfaces) to enhance light absorption, quantum efficiency, or bandwidth, particularly in silicon, germanium, or SiGe alloys.

   • Potential Anticipation: Such references could potentially anticipate elements of Claim 1 (a single-chip device with an MSPD having holes), Claim 16 (a microstructure-enhanced photodetector with layers and holes), and Claim 25 (a method of making such a device). Specific details regarding the shape, depth, spacing, and material composition of the microstructures, as well as their location within the p-i-n or n-i-p structure, would be critical for anticipation analysis.

2. Integrated Photodetectors and Electronic Circuits on a Single Chip: Prior art describing the monolithic integration of photodetectors with active electronic circuits (e.g., CMOS, BiCMOS ASICs, TIAs) on a single substrate.

   • Potential Anticipation: These references would be highly relevant to Claim 1, which defines a "single-chip device" comprising an MSPD and an active electronic circuit. If the prior art discloses the integration of a photodetector (even without microstructures) and an active electronic circuit, it could anticipate the broader integration aspect of Claim 1. The novelty of Claim 1, in this context, lies in the microstructure-enhanced nature of the photodetector within the integrated device.

3. Specific Material Systems for Photodiodes: Prior art focusing on the use of Silicon (Si), Germanium (Ge), or Germanium-Silicon (GeSi) alloys as the absorbing material in photodetectors for specific wavelength ranges (e.g., 800-1675 nm).

   • Potential Anticipation: While the specific microstructure enhancement might be novel, if prior art discloses the fundamental material stack (e.g., N-I-P or P-I-N structures of Si, Ge, or GeSi) as described in the patent, it could form a basis for an obviousness challenge (under 35 U.S.C. § 103) when combined with other references detailing microstructures. For anticipation under § 102, a prior art would need to explicitly disclose these material layers in combination with the hole structures.

4. Fabrication Methods for Microstructures in Semiconductor Devices: Prior art detailing etching techniques (e.g., wet anisotropic etch (KOH), dry etching (DRIE, ICP), HAR etching) to create holes or textured surfaces in silicon or other semiconductor materials.

   • Potential Anticipation: These references would be highly relevant to Claim 25, which describes the "method of making a microstructure-enhanced photodetector." If a prior art document explicitly teaches the steps of forming layers and then etching holes with specific characteristics (shapes, depths, materials) into those layers, it could anticipate aspects of the method claim.

5. Optical Elements and Light Trapping Structures: Prior art on photonic crystals, anti-reflection coatings, or other optical structures designed to enhance light absorption or modify light propagation within a device.

   • Potential Anticipation: While potentially not directly anticipating a full photodetector claim, these references could be used in obviousness arguments, especially concerning the "microstructure enhanced absorption" aspect of the independent claims.

Without the specific list of "References Cited" from the patent document itself, it is not possible to provide the full citation, publication/filing dates, brief descriptions, and specific claim anticipation for each individual prior art reference.

The obviousness analysis under 35 U.S.C. § 103 requires determining whether the differences between the claimed invention and the prior art would have been obvious to a person having ordinary skill in the art (PHOSITA) at the time of the invention. This involves considering the scope and content of the prior art, the differences between the claimed invention and the prior art, and the level of ordinary skill in the pertinent art. A motivation to combine prior art references must exist, which can come from the knowledge of those skilled in the art, from the prior art references themselves, or from the nature of the problem to be solved.

Level of Ordinary Skill in the Art (PHOSITA):
A PHOSITA in this field would likely possess a graduate degree (Master's or Ph.D.) in electrical engineering, materials science, or a related discipline, with several years of experience in semiconductor device fabrication, optoelectronics, or integrated circuit design, particularly with expertise in photodetectors, avalanche photodiodes, and silicon photonics. This individual would be familiar with various etching techniques, epitaxial growth of silicon and germanium-silicon alloys, and the integration of optical devices with CMOS/BiCMOS electronics.

Motivation to Combine:
The primary motivation for combining elements from the prior art to arrive at the claimed invention would be to improve the performance of photosensitive devices, specifically focusing on enhanced light absorption, increased quantum efficiency, higher data rates, and monolithic integration with existing silicon electronics for cost reduction and efficiency in applications like fiber-optic communication, data centers, and LIDAR. The art clearly recognized the trade-offs between efficiency, speed, and cost in photodetectors and sought solutions to overcome these limitations.

Combinations of Prior Art for Obviousness:

1. Claims 1, 16, and 25 (General Microstructure-Enhanced Photodetector with Integration)

• References: US9525084B2 (W&wsens Devices Inc.), Mavrokefalos et al. (2012), Singh et al. (2011)

• Discussion: US9525084B2, a patent within the same family as US10446700, broadly describes techniques for enhancing photon absorption in semiconductors using microstructures like holes to increase quantum efficiency and bandwidth for silicon photodiodes and avalanche photodiodes. It explicitly mentions the integration of such devices on the same Si chip with CMOS, BiCMOS, and other electronics. Mavrokefalos et al. (2012) teach the use of inverted nanopyramid light-trapping schemes in thin crystalline silicon films to significantly enhance light absorption for solar cell applications, noting that these structures can be fabricated at wafer scale via a low-cost wet etching process. This reference demonstrates the effectiveness of microstructures, specifically inverted pyramids, for light trapping and absorption enhancement in silicon, a core element of US10446700. Singh et al. (2011) provide a review of Silicon-On-Insulator (SOI) technology, highlighting its advantages for reducing power consumption, increasing speed, and enabling higher integration density in CMOS ICs by using a thin silicon layer on top of a buried oxide.

• Motivation to Combine: A PHOSITA, aware of the general benefits of microstructures for light absorption (US9525084B2, Mavrokefalos et al.) and the advantages of SOI technology for high-performance and integrated electronics (Singh et al.), would have been motivated to combine these concepts to create a microstructure-enhanced photodetector on an SOI substrate. The motivation would be to leverage the improved light-trapping capabilities of microstructures, as demonstrated by Mavrokefalos et al., with the established benefits of SOI technology for monolithic integration with high-speed CMOS/BiCMOS circuits, as broadly disclosed in US9525084B2. The goal would be to achieve higher quantum efficiency and faster operation in a compact, integrated device, addressing the known challenges in high-speed optical communication. The general concept of integrating photodetectors with microstructures and electronic circuits on a single chip is already present in the prior art, including US9525084B2.

2. Claims 1, 16, and 25 (Specific Etching Techniques and Hole Shapes)

• References: US9525084B2, Fan et al. (2013), Mavrokefalos et al. (2012)

• Discussion: US9525084B2 mentions that microstructures like holes effectively increase photon absorption and that these holes can be formed by etching. Fan et al. (2013) discuss the differences in etching characteristics of TMAH and KOH for preparing inverted pyramids for silicon solar cells, detailing how these etchants can create specific hole shapes. Mavrokefalos et al. (2012) specifically demonstrate efficient light trapping using inverted nanopyramid structures fabricated via a low-cost wet etching process. US10446700 mentions that the microstructure holes can be etched using KOH solution and also refers to Fan et al. and Mavrokefalos et al. for inverted pyramids. The patent further explicitly states that the holes can be shaped as inverted pyramids and have triangular sections.

• Motivation to Combine: A PHOSITA seeking to implement the microstructure-enhanced absorption described in US9525084B2 would naturally look to known etching techniques for forming such structures. Fan et al. and Mavrokefalos et al. directly provide the methodology for creating inverted pyramid-shaped holes in silicon using wet etching (KOH or TMAH), which are shown to be effective for light trapping and absorption enhancement. The motivation to combine would be to utilize these known and effective etching processes to fabricate the microstructure holes described in US9525084B2, achieving the desired light-trapping geometry (e.g., inverted pyramids) for improved quantum efficiency in photodetectors. The patent itself cites these references for the etching of inverted pyramids.

3. Claim 1 (GeSi Alloys and Monolithic Integration)

• References: US9525084B2, Montalenti et al. (2014) , US20180102442A1 (which is US10446700's own publication history)

• Discussion: US9525084B2 states that the photodetector can comprise a germanium-based photon absorbing layer formed by epitaxial growth above silicon layers, and that the photodetector can be an avalanche photodiode with a multiplication region formed of silicon. US10446700 also discusses the use of GeₓSi₁₋ₓ alloys for the intermediate (I) layer, where x is greater than zero, to extend the detectable wavelength range and mentions that strain in the GeSi alloy can narrow the bandgap. Montalenti et al. (2014) discuss the fully coherent growth of Ge on free-standing Si(001) nanomesas, indicating the knowledge of growing GeSi materials on silicon with controlled strain. The patent explicitly refers to Montalenti et al. regarding the growth of GeSi alloy and/or Ge within nano/microstructured holes.

• Motivation to Combine: Given the stated goal of extending the detectable wavelength range beyond silicon's intrinsic limits, a PHOSITA would be motivated to incorporate germanium or GeSi alloys into the absorbing layer, as suggested by US9525084B2. The knowledge from Montalenti et al. (2014) regarding the controlled growth of strained GeSi on silicon provides a clear method for achieving such a material system. Combining the microstructure-enhanced absorption concept from US9525084B2 with the epitaxial growth techniques for GeSi alloys, a PHOSITA would find it obvious to create a photodetector using GeSi in the intermediate layer within microstructure holes to enable detection at longer wavelengths while maintaining enhanced absorption, as indicated by the patent's own description.

4. Claims 1 and 16 (Dielectric Material in Propagation Path)

• References: US9525084B2, Paneva et al. (1995), US6222257B1

• Discussion: US10446700 claims a layer of dielectric material in the propagation path of the optical input, covering the holes and spaces between them. US9525084B2, in describing microstructures, is silent on the specific material filling or covering the holes, but it is implied that the microstructure itself is a light-trapping feature. Prior art references such as Paneva et al. (1995) and US6222257B1 discuss the use of silicon nitride and silicon dioxide as etch stop layers in silicon processing. These materials are well-known dielectrics in semiconductor manufacturing.

• Motivation to Combine: A PHOSITA would be motivated to incorporate a dielectric material, such as silicon dioxide or nitride, over the microstructure holes and spaces. This would serve multiple purposes: protecting the etched structures, providing mechanical stability, and potentially acting as an anti-reflection coating or waveguide cladding to further enhance light coupling into the device. The use of common dielectrics in semiconductor manufacturing for passivation and optical purposes would be well within the knowledge of a PHOSITA and would be a logical step to improve the robustness and optical performance of the microstructure-enhanced photodetector described in US9525084B2.

5. Claim 25 (Method of Making with Air-Filled Volume)

• References: US9525084B2, Singh et al. (2011), Wu et al. (cited in US10446700 description for DRIE, ICP, HAR etching)

• Discussion: US10446700 describes forming an air-filled volume between the substrate and the MSPD. The patent also refers to forming holes using wet and dry etching techniques like DRIE, ICP, and HAR etching. US9525084B2 discusses the formation of microstructure holes by etching. Singh et al. (2011) describe SOI manufacturing methods, including the use of buried oxide layers to provide dielectric isolation. While not explicitly teaching "air-filled volume" in the context of light trapping, SOI technology inherently involves a buried dielectric layer, which could be selectively removed or patterned to create voids. The concept of creating voids or air gaps in silicon structures for various purposes, including optical applications, was known in the art (e.g., photonic crystals).

• Motivation to Combine: A PHOSITA would be motivated to create air-filled volumes beneath the photodetector, particularly if working with SOI wafers. Air gaps can serve as effective reflectors or provide optical isolation, further enhancing light trapping within the active region of the photodetector by total internal reflection, as noted within US10446700 itself regarding bottom holes. The combination of etching techniques (like DRIE mentioned in US10446700, and as implicitly taught by other prior art for micro-machining silicon) with SOI wafers to create controlled air gaps or voids for optical enhancement would be an obvious design choice for improving the efficiency of the microstructure-enhanced photodetectors.

6. Claim 1 (Integration with Active Electronic Circuit)

• References: US9525084B2, Zhang et al. (2017), Singh et al. (2011)

• Discussion: Claim 1 of US10446700 describes a single-chip device comprising an integrated combination of an MSPD and an active electronic circuit, both formed on or in a single substrate. US9525084B2 explicitly states that its microstructure-enhanced devices "can be conveniently integrated on the same Si chip with CMOS, BiCMOS, and other electronics, with resulting packaging benefits and reduced capacitance and thus higher speeds." Zhang et al. (2017) demonstrate a CMOS-compatible, nanostructured, thin-junction Si single-photon avalanche diode that breaks the trade-off between photon detection efficiency and timing jitter, noting its "complementary metal oxide semiconductor compatibility" and that the result "provides a practical and complementary metal oxide semiconductor compatible method to improve the performance of single-photon avalanche detectors, image sensor arrays, and silicon photomultipliers over a broad spectral range." Singh et al. (2011) discusses SOI technology as important for leading-edge CMOS IC production and system-on-chip (SOC) applications.

• Motivation to Combine: The explicit teaching in US9525084B2 of integrating microstructure-enhanced photodetectors with CMOS/BiCMOS electronics on a single chip provides a direct motivation for this combination. Zhang et al. further reinforce the feasibility and benefits of CMOS-compatible nanostructured devices, addressing performance trade-offs critical for high-speed applications. Singh et al. highlight SOI as a key technology for advanced CMOS integration. A PHOSITA would have been highly motivated to combine these known elements to create a fully integrated, high-performance optical receiver on a single silicon chip, driven by the desire for reduced cost, smaller footprint, and improved electrical characteristics (e.g., lower capacitance and higher speed) in high-volume applications like data centers and telecommunications.

To provide a comprehensive answer regarding US Patent 10,446,700, I will search the USPTO Patent Center and Public Search databases, as well as Google Patents.

Patent Term Adjustments (PTA)

Patent Term Adjustment (PTA) is granted to compensate patent applicants for certain delays by the USPTO during the prosecution of a utility or plant patent application. These delays can include the USPTO failing to:

• Issue a first Official Action or notice of allowance within 14 months of filing.
• Respond to an applicant's reply within four months.
• Issue a patent within four months of the issue fee payment.
• Issue a patent within three years of the actual filing date of the application.

Applicant-caused delays can reduce or eliminate PTA.

To determine the specific PTA for US Patent 10,446,700, one would typically access the patent's file wrapper through USPTO Patent Center. This information is usually detailed on the issued patent itself or in the patent's prosecution history. As this information is not directly provided in the original patent text, a direct search of the USPTO database for the specific PTA calculation would be required.

Patent Term Extensions (PTE)

Patent Term Extension (PTE) is available for patents covering certain products, such as human drugs, food or color additives, medical devices, animal drugs, and veterinary biological products, to restore patent term lost due to premarket government regulatory review. The determination for PTE is made by the USPTO in consultation with the relevant regulatory agency (e.g., FDA). PTE is generally limited to a single patent per approved product, for a maximum of five years, and cannot extend the patent term over 14 years from the date of marketing approval.

Based on the description of US Patent 10,446,700 as relating to "Microstructure enhanced absorption photosensitive devices" for applications in optical communications and LIDAR, it is highly unlikely to be eligible for Patent Term Extension under 35 U.S.C. § 156, as it does not appear to claim a product that requires regulatory approval from agencies like the FDA for commercial marketing.

Continuation Applications and Divisional Applications

A patent family consists of related patent applications, typically covering the same invention or features, linked by priority claims.

• Continuation Application: An applicant files the same application without adding any new matter, claiming priority to an earlier parent application.
• Divisional Application: Filed when an original patent application claims more than one invention. The divisional application claims subject matter disclosed in the parent application but restricted out by the examiner. Divisional applications get the same filing date as the parent application.

To identify specific continuation or divisional applications for US Patent 10,446,700, one would need to examine its "Related U.S. Application Data" section or the patent family information in a patent database. The provided text lists several priority claims, including:

• US 15/797,821 (Filing date: 2017-10-30), which is the application number for US 10,446,700.
• Priority claimed from PCT/US2014/039208 (Prior art date: 2013-05-22).
• Priority claimed from PCT/US2015/061120.
• Priority claimed from PCT/US2016/067977.
• Priority to US 16/042,535 (2018-07-23).
• Priority to PCT/US2018/057963 (2018-10-29).
• Priority to US 16/296,985 (2019-03-08).
• Priority to US 16/528,958 (2019-08-01).
• Priority to US 17/182,954 (2021-02-23).
• Priority to US 17/532,831 (2021-11-22).
• Priority to US 17/707,429 (2022-03-29).
• Priority to US 17/974,325 (2022-10-26).
• Priority to US 18/113,474 (2023-02-23).
• Priority to US 18/385,213 (2023-10-30).
• Priority to US 18/822,880 (2024-09-03).

These listed priorities indicate a robust patent family with multiple related applications. Specific details on which are continuations or divisionals would require examining each application's filing history.

Related Family Members

The patent family includes the following published applications and issued patents, based on the priority claims listed in the provided text:

• US 20180102442 A1 (publication of US15/797,821, the application that matured into US10446700B2)
• WO 2014190189 A2 (from PCT/US2014/039208)
• WO 2016081476 A1 (from PCT/US2015/061120)
• WO 2017112747 A1 (from PCT/US2016/067977)
• US 10700225 B2 (from US 16/042,535)
• WO 2019089437 A1 (from PCT/US2018/057963)
• US 10468543 B2 (from US 16/296,985)
• US 11121271 B2 (from US 16/528,958)
• US 11791432 B2 (from US 17/182,954)
• US 11309444 B1 (from US 17/532,831)
• US 11621360 B2 (from US 17/707,429)
• US 11830954 B2 (from US 17/974,325)
• US 20230215962 A1 (from US 18/113,474)
• US 12087871 B2 (from US 18/385,213)
• US 12243948 B2 (from US 18/822,880)

This extensive list indicates a large patent family with both US and international counterparts, reflecting ongoing protection for various aspects of the invention.

Projected Expiration Date

The nominal term of a U.S. utility patent is 20 years from the earliest filing date of the patent application or the earliest non-provisional application to which it claims priority. However, this term can be affected by Patent Term Adjustment (PTA) or Patent Term Extension (PTE), as well as terminal disclaimers.

For US Patent 10,446,700, the "Priority date" listed is 2013-05-22. This is the earliest priority date from the PCT application PCT/US2014/039208. Therefore, the nominal expiration date would be 20 years from this date.

Nominal Expiration Date = May 22, 2013 + 20 years = May 22, 2033.

The Google Patents page for US10446700B2 explicitly states an "Anticipated expiration" date of 2034-05-22. This difference of one year indicates that the patent has likely received one year of Patent Term Adjustment (PTA). This adjustment would be due to delays by the USPTO during the prosecution of the patent application. As previously discussed, the patent is not eligible for PTE. Therefore, the projected expiration date, including PTA, is May 22, 2034.

Defensive Disclosure Document for US Patent 10,446,700

This document outlines derivative variations of the inventions claimed in U.S. Patent No. 10,446,700, aiming to expand the prior art landscape and render future incremental improvements obvious or non-novel. These disclosures are presented with sufficient technical detail to enable a person skilled in the art to reproduce the variations.

Core Claim 1: Single-chip device with integrated MSPD and active electronic circuit

1.1 Material & Component Substitution Derivatives

Derivative 1.1.1: III-V Semiconductor MSPD with Graphene Ohmic Contacts

• Enabling Description: A single-chip device is fabricated on a Gallium Arsenide (GaAs) substrate. The microstructure-enhanced photodetector (MSPD) comprises an intermediate absorption layer of Indium Gallium Arsenide (InGaAs) (e.g., In₀.₅₃Ga₀.₄₇As) lattice-matched to Indium Phosphide (InP) buffer layers, with doped InP top and bottom layers forming a P-I-N structure. The microstructure holes are formed in the InGaAs layer using dry etching (e.g., Inductively Coupled Plasma Reactive Ion Etching - ICP-RIE) with a chlorine-based chemistry. The active electronic circuit, implemented using high electron mobility transistors (HEMTs) on the same GaAs substrate, is configured for transimpedance amplification (TIA). Ohmic contacts for both the MSPD and the HEMTs are formed using CVD-grown monolayer graphene transferred and patterned onto platinum/titanium contact pads, reducing contact resistance and improving transparency for incident light at the top P-layer.

• graph TD
      A[Optical Input] --> B(MSPD - InGaAs/InP)
      B --> C{Electrical Output}
      C --> D(Graphene Ohmic Contacts)
      D --> E(Communication Channel)
      E --> F(Active Electronic Circuit - HEMTs)
      F --> G[Processed Output]
      style B fill:#f9f,stroke:#333,stroke-width:2px
      style F fill:#9cf,stroke:#333,stroke-width:2px
  

Derivative 1.1.2: Germanium-on-Silicon MSPD with Silicon-Germanium Alloy Circuitry

• Enabling Description: A single-chip device is constructed on a bulk silicon substrate. The MSPD features a relaxed Germanium (Ge) intermediate absorption layer grown epitaxially on a graded SiGe buffer on the silicon substrate, with heavily doped SiGe alloy (e.g., Ge₀.₃Si₀.₇) top and bottom layers forming an N-I-P structure. Microstructure holes, such as inverted pyramids, are anisotropically etched into the Ge layer using a potassium hydroxide (KOH) solution, followed by a dry etch to achieve specific sidewall profiles. The active electronic circuit is fully integrated on the same silicon substrate utilizing silicon-germanium (SiGe) heterojunction bipolar transistors (HBTs) for high-frequency operation, co-integrated with complementary metal-oxide-semiconductor (CMOS) components in the SiGe layers. The communication channel between the MSPD and the SiGe HBT TIA is realized via low-resistance metal interconnects (e.g., copper).

• graph TD
      A[Optical Input] --> B(MSPD - Ge/SiGe)
      B --> C{Electrical Output}
      C --> D(Copper Interconnects)
      D --> E(Communication Channel)
      E --> F(Active Electronic Circuit - SiGe HBT/CMOS)
      F --> G[Processed Output]
      style B fill:#f9f,stroke:#333,stroke-width:2px
      style F fill:#9cf,stroke:#333,stroke-width:2px
  

1.2 Operational Parameter Expansion Derivatives

Derivative 1.2.1: Cryogenic Operation for Quantum Computing Interfaces

• Enabling Description: A single-chip device, based on a Silicon-on-Insulator (SOI) substrate, integrates an all-silicon P-I-N MSPD with microstructure holes etched through the top P+ and intrinsic (I) layers, operating at a temperature range of 4 Kelvin to 77 Kelvin. The active electronic circuit is a low-noise cryogenic amplifier realized using superconducting single-electron transistors (SETs) or silicon-based quantum dot transistors, fabricated alongside the MSPD on the same SOI die. The entire chip is designed with minimized thermal conductivity paths and optimized material interfaces for efficient heat transfer to a cryostat, while maintaining high quantum efficiency and low dark current at extremely low temperatures for interfacing with quantum processors. The optical input is delivered via a cryogenically compatible optical fiber.

• graph TD
      A[Cryogenic Optical Input] --> B(Cryo-MSPD - Silicon P-I-N)
      B --> C{Cryogenic Electrical Output}
      C --> D(Superconducting Interconnects)
      D --> E(Communication Channel)
      E --> F(Cryo-Active Circuit - SETs/Quantum Dots)
      F --> G[Cryogenic Processed Output]
      style B fill:#f9f,stroke:#333,stroke-width:2px
      style F fill:#9cf,stroke:#333,stroke-width:2px
  

Derivative 1.2.2: Terahertz Frequency Detection for Imaging Applications

• Enabling Description: A single-chip device incorporates an MSPD sensitive to terahertz (THz) radiation (0.1 THz to 10 THz, corresponding to wavelengths of 3 mm to 30 µm), utilizing a heavily doped silicon or germanium intermediate layer with a high density of resonant micro-scale holes (e.g., sub-wavelength metamaterial structures). The top and bottom layers are thin, highly doped contacts. The active electronic circuit is a resonant tunneling diode (RTD) based THz amplifier, monolithically integrated on the same semiconductor substrate. The microstructure holes are engineered to exhibit strong plasmonic resonance at specific THz frequencies, channeling incident THz radiation into the active region for enhanced absorption. The communication channel employs miniature striplines for THz signal integrity.

• graph TD
      A[THz Optical Input] --> B(THz-MSPD - Doped Si/Ge Metamaterial)
      B --> C{THz Electrical Output}
      C --> D(Miniature Striplines)
      D --> E(Communication Channel)
      E --> F(Active Electronic Circuit - RTD THz Amp)
      F --> G[THz Processed Output]
      style B fill:#f9f,stroke:#333,stroke-width:2px
      style F fill:#9cf,stroke:#333,stroke-width:2px
  

1.3 Cross-Domain Application Derivatives

Derivative 1.3.1: Environmental Sensing for Air Quality Monitoring

• Enabling Description: A single-chip device is designed for autonomous air quality monitoring, integrating an MSPD with an active electronic circuit. The MSPD is configured to detect specific infrared absorption signatures of atmospheric pollutants (e.g., CO2, CH4, VOCs) by varying the material composition (e.g., GeSi with tunable bandgap for specific IR ranges) or hole dimensions for bandpass filtering. The active electronic circuit comprises a low-power microcontroller (MCU) and a communication module for wireless data transmission (e.g., LoRaWAN). The optical input is from a compact tunable infrared laser, and the MSPD measures attenuated light after it passes through a sampled air volume. The processing circuit analyzes the absorption spectrum to quantify pollutant concentrations.

• graph TD
      A[Tunable IR Laser] --> B(Air Sample)
      B --> C(Environmental MSPD - Tunable GeSi)
      C --> D{Electrical Output - Absorption Data}
      D --> E(Communication Channel)
      E --> F(Active Electronic Circuit - Low-Power MCU + LoRaWAN)
      F --> G[Processed Output - Pollutant Concentration]
      style C fill:#f9f,stroke:#333,stroke-width:2px
      style F fill:#9cf,stroke:#333,stroke-width:2px
  

Derivative 1.3.2: Biomedical Imaging for In-Vivo Fluorescence Detection

• Enabling Description: A single-chip device is adapted for miniature, implantable biomedical imaging. The MSPD consists of a biocompatible silicon or SiC P-I-N structure with microstructured holes optimized for near-infrared (NIR) detection (e.g., 700-900 nm) to capture fluorescence signals from biomarkers. The active electronic circuit incorporates ultra-low power signal conditioning and analog-to-digital conversion (ADC) units, with wireless telemetry for data transmission to an external receiver. The optical input comes from a miniaturized LED or laser source (not on-chip but coupled), exciting fluorescent tags in tissue. The MSPD is integrated into a bio-inert package suitable for in-vivo deployment.

• graph TD
      A[NIR Light Source] --> B(Fluorescent Biomarker)
      B --> C(Biomedical MSPD - Si/SiC P-I-N)
      C --> D{Electrical Output - Fluorescence Signal}
      D --> E(Communication Channel)
      E --> F(Active Electronic Circuit - Signal Conditioner + ADC + Telemetry)
      F --> G[Processed Output - Imaging Data]
      style C fill:#f9f,stroke:#333,stroke-width:2px
      style F fill:#9cf,stroke:#333,stroke-width:2px
  

Derivative 1.3.3: Space Exploration for Radiation-Hardened Star Trackers

• Enabling Description: A single-chip device is designed for space-borne star tracking applications, requiring extreme radiation hardness. The MSPD utilizes a wide-bandgap semiconductor (e.g., Gallium Nitride - GaN, or Silicon Carbide - SiC) as its base material, with microstructure holes optimized for visible light detection. The active electronic circuit consists of radiation-hardened CMOS logic and read-out integrated circuits (ROICs), also fabricated on the GaN/SiC substrate. The integrated device features redundant circuitry and error-correction codes to mitigate radiation-induced upsets. The MSPD arrays acquire star field images, which the active circuit processes for spacecraft attitude determination.

• graph TD
      A[Optical Input - Star Light] --> B(Rad-Hard MSPD - GaN/SiC P-I-N)
      B --> C{Electrical Output - Image Data}
      C --> D(Communication Channel - Rad-Hard Bus)
      D --> F(Active Electronic Circuit - Rad-Hard CMOS ROIC)
      F --> G[Processed Output - Attitude Data]
      style B fill:#f9f,stroke:#333,stroke-width:2px
      style F fill:#9cf,stroke:#333,stroke-width:2px
  

1.4 Integration with Emerging Tech Derivatives

Derivative 1.4.1: AI-Driven Self-Optimization

• Enabling Description: A single-chip device integrates a SiGe MSPD with an active electronic circuit that includes an on-chip AI accelerator (e.g., a tinyML processor). The MSPD features reconfigurable microstructures, where the optical properties (e.g., hole size, spacing, filling material dielectric constant) can be dynamically adjusted (e.g., via microelectromechanical systems - MEMS, or electrically tunable materials like liquid crystals or ferroelectrics within holes). The AI accelerator continuously monitors the MSPD's quantum efficiency and response time, adjusting the microstructure parameters in real-time to optimize performance for varying incident light conditions (e.g., intensity, wavelength, angle) or system requirements (e.g., maximizing QE, minimizing latency, balancing power consumption).

• graph TD
      A[Optical Input (Variable)] --> B(MSPD - Reconfigurable Microstructures)
      B --> C{Electrical Output}
      C --> D(Communication Channel)
      D --> E(Active Electronic Circuit - TIA + AI Accelerator)
      E -- Control Feedback --> F(Microstructure Actuators)
      F -- Reconfigures --> B
      E --> G[Processed Output (Optimized)]
      style B fill:#f9f,stroke:#333,stroke-width:2px
      style E fill:#9cf,stroke:#333,stroke-width:2px
  

Derivative 1.4.2: IoT Sensor Node with Edge Processing and Integrated MSPD

• Enabling Description: A single-chip device functions as a compact IoT sensor node. It integrates a low-power Silicon MSPD optimized for visible light detection with an active electronic circuit comprising an ultra-low-power ARM Cortex-M microcontroller, a secure element, and a Bluetooth Low Energy (BLE) radio, all on a single silicon die. The MSPD provides ambient light data (e.g., for smart lighting, occupancy sensing). The on-chip microcontroller performs edge processing, such as filtering noise, converting raw data to meaningful lux levels, and detecting motion patterns, before securely transmitting aggregated data via BLE to a local gateway or cloud. The microstructure enables high sensitivity for low-light conditions, extending battery life.

• graph TD
      A[Ambient Light Input] --> B(MSPD - Low-Power Silicon)
      B --> C{Electrical Output - Raw Light Data}
      C --> D(Communication Channel)
      D --> E(Active Electronic Circuit - ARM MCU + BLE + Secure Element)
      E --> F[Processed Output - Contextual Data (e.g., Lux, Occupancy)]
      E -- Wireless Transmit --> G(IoT Gateway)
      style B fill:#f9f,stroke:#333,stroke-width:2px
      style E fill:#9cf,stroke:#333,stroke-width:2px
  

Derivative 1.4.3: Blockchain-Enabled Data Provenance for Secure Optical Communication

• Enabling Description: A single-chip device integrates a high-speed InGaAs MSPD with an active electronic circuit that includes a hardware security module (HSM) and a blockchain client. The MSPD converts high-bandwidth optical data signals (e.g., from a fiber-optic link). The processing circuit performs error correction, decryption, and hash generation of the received data. The HSM securely signs these data hashes, and the blockchain client transmits the signed hashes as transactions to a distributed ledger, providing an immutable record of data reception and integrity. This ensures end-to-end data provenance and tamper detection for critical optical communication links.

• graph TD
      A[Optical Data Input] --> B(MSPD - High-Speed InGaAs)
      B --> C{Electrical Data Output}
      C --> D(Communication Channel)
      D --> E(Active Electronic Circuit - TIA + Decrypt + Hash + HSM + Blockchain Client)
      E -- Signed Hashes --> F(Blockchain Network)
      E --> G[Processed Output - Verified Data]
      style B fill:#f9f,stroke:#333,stroke-width:2px
      style E fill:#9cf,stroke:#333,stroke-width:2px
  

1.5 The "Inverse" or Failure Mode Derivatives

Derivative 1.5.1: Low-Power "Sentinel" Mode for Emergency Communication

• Enabling Description: A single-chip device incorporates a Silicon MSPD and an active electronic circuit designed with a configurable power management unit. In normal operation, the MSPD functions at peak performance for high-speed data. In a "sentinel" or low-power mode, the active electronic circuit significantly reduces the bias voltage to the MSPD and disables non-essential processing blocks. The MSPD, while operating at a reduced quantum efficiency and bandwidth, is still capable of detecting a pre-defined low-rate optical signal (e.g., a blinking LED or a low-frequency modulated laser). This allows the device to maintain a basic communication link with extremely low power consumption for extended periods during power outages or emergency scenarios, triggering a full power-up upon detection of a specific optical wake-up signal.

• stateDiagram
      [*] --> NormalOperation
      NormalOperation --> LowPowerMode : Power_Loss / Command_LowPower
      LowPowerMode --> NormalOperation : Optical_Wakeup_Signal
      NormalOperation : High QE, High Bandwidth
      LowPowerMode : Reduced QE, Reduced Bandwidth, Ultra-low Power
      NormalOperation --> MSPD_Full_Performance
      MSPD_Full_Performance --> Active_Circuit_Full_Power
      LowPowerMode --> MSPD_Reduced_Performance
      MSPD_Reduced_Performance --> Active_Circuit_Low_Power
  

Derivative 1.5.2: Fail-Safe Optical Overload Protection

• Enabling Description: A single-chip device features a SiGe MSPD integrated with an active electronic circuit that includes an optical power monitoring circuit and a dynamic attenuator. The MSPD's microstructures are designed with a thermally sensitive filling material or an adjacent MEMS shutter array. In the event of an excessive optical input power, the monitoring circuit detects the overload condition. This triggers the active circuit to either apply a reverse bias to the MSPD to temporarily reduce its responsivity (if feasible without damage) or, more robustly, activate the MEMS shutter to physically block or attenuate the incident light, or induce a phase change in the thermally sensitive material filling the holes to increase reflection/scattering. This prevents saturation, irreversible damage to the photodetector, and ensures recovery once the overload is removed.

• flowchart TD
      A[Optical Input] --> B(Optical Power Monitor)
      B -- High Power Detected --> C{Active Electronic Circuit - Overload Control}
      C -- Control Signal --> D(Dynamic Optical Attenuator / MEMS Shutter / Thermally Sensitive Microstructures)
      D --> E(MSPD - Protected)
      E --> F[Electrical Output]
      B -- Normal Power --> E
      style E fill:#f9f,stroke:#333,stroke-width:2px
      style C fill:#9cf,stroke:#333,stroke-width:2px
  

Core Claim 16: Microstructure-enhanced photodetector

2.1 Material & Component Substitution Derivatives

Derivative 2.1.1: High-Index Dielectric Hole Filling with Sapphire Substrate

• Enabling Description: A microstructure-enhanced photodetector is constructed on a sapphire (Al2O3) substrate, which offers excellent thermal conductivity and optical transparency. The active layers (top, intermediate, bottom) are composed of epitaxial Silicon Carbide (SiC) to leverage its wide bandgap and radiation hardness. The holes intentionally formed in the intermediate SiC layer are completely filled with a high refractive index dielectric material, such as Titanium Dioxide (TiO2, n≈2.5) or Tantalum Pentoxide (Ta2O5, n≈2.2), deposited using atomic layer deposition (ALD). This high-index filling material, combined with the microstructured geometry, further enhances light trapping and waveguide effects within the absorption region, maximizing quantum efficiency over a broader spectrum. An overlying covering layer of Silicon Nitride (SiN) acts as an anti-reflection coating.

• graph TD
      A[Optical Input] --> B(SiN Anti-Reflection Layer)
      B --> C(Top Doped SiC Layer)
      C --> D(Intermediate SiC Layer with TiO2/Ta2O5 Filled Holes)
      D --> E(Bottom Doped SiC Layer)
      E --> F(Sapphire Substrate)
      F --> G[Electrical Output]
  

Derivative 2.1.2: Flexible Polymer Substrate with 2D Material Active Layers

• Enabling Description: A microstructure-enhanced photodetector is fabricated on a flexible polymer substrate (e.g., polyimide). The active layers comprise a heterostructure of two-dimensional (2D) materials, such as a Tungsten Diselenide (WSe2) intermediate intrinsic layer sandwiched between doped Molybdenum Disulfide (MoS2) top and bottom layers (P-MoS2/I-WSe2/N-MoS2). Microstructure holes are patterned into the WSe2 layer using electron beam lithography and subsequent dry etching (e.g., plasma etching). A conformal dielectric layer of Boron Nitride (h-BN) is applied over the holes and spaces, providing environmental passivation and acting as a waveguide for enhanced light interaction. The entire device maintains mechanical flexibility while achieving broad spectral response due to the 2D materials.

• graph TD
      A[Optical Input] --> B(h-BN Dielectric Layer)
      B --> C(Top Doped MoS2 Layer)
      C --> D(Intermediate WSe2 Layer with Holes)
      D --> E(Bottom Doped MoS2 Layer)
      E --> F(Flexible Polyimide Substrate)
      F --> G[Electrical Output]
  

2.2 Operational Parameter Expansion Derivatives

Derivative 2.2.1: Ultra-Wide Spectrum Detection (UV to Far-Infrared)

• Enabling Description: A microstructure-enhanced photodetector is designed for detection across an ultra-wide electromagnetic spectrum, spanning ultraviolet (UV), visible, near-infrared (NIR), and far-infrared (FIR). This is achieved by creating a stacked array of multiple photodetector layers on a single substrate, each layer optimized for a specific wavelength range. For example, a top GaN layer with microstructures for UV, followed by a Si layer with different microstructures for visible/NIR, and a bottom Mercury Cadmium Telluride (HgCdTe) layer with further optimized microstructures for FIR. Each layer has independently formed holes tuned to its absorption characteristics. The entire stack is integrated on a Si or SiC substrate, with individual electrical contacts for each spectral band.

• graph TD
      A[UV Input] --> B(GaN MSPD - UV Optimized)
      A[Visible/NIR Input] --> C(Si MSPD - Visible/NIR Optimized)
      A[FIR Input] --> D(HgCdTe MSPD - FIR Optimized)
      B & C & D --> E(Stacked Architecture on Si/SiC Substrate)
      E --> F[Multi-Spectral Electrical Output]
  

Derivative 2.2.2: High-Radiation Environment Operation

• Enabling Description: A microstructure-enhanced photodetector is constructed for deployment in high-radiation environments (e.g., nuclear reactors, space missions). The device utilizes an intrinsic Gallium Nitride (GaN) intermediate layer, flanked by heavily doped P-GaN and N-GaN layers, grown on a Silicon Carbide (SiC) substrate. GaN's wide bandgap and strong bonding make it inherently radiation-hard. The microstructure holes are formed in the GaN layer, and subsequently passivated with a thick, radiation-resistant dielectric (e.g., Alumina - Al2O3) to prevent radiation-induced surface leakage currents. All materials chosen exhibit high displacement damage threshold and reduced susceptibility to single-event upsets (SEUs), ensuring stable operation under ionizing radiation fluxes.

• graph TD
      A[Optical Input] --> B(Al2O3 Passivation Layer)
      B --> C(Top Doped P-GaN Layer)
      C --> D(Intermediate I-GaN Layer with Holes)
      D --> E(Bottom Doped N-GaN Layer)
      E --> F(SiC Substrate)
      F --> G[Radiation-Hardened Electrical Output]
  

2.3 Cross-Domain Application Derivatives

Derivative 2.3.1: Security Screening (Terahertz Body Scanners)

• Enabling Description: A microstructure-enhanced photodetector is implemented in a terahertz (THz) security screening system. The detector features a heavily doped silicon intermediate layer with metallic-coated sub-wavelength holes (e.g., gold-coated silicon) designed to act as resonant THz antennas and waveguides. The top and bottom layers provide high-conductivity contacts for efficient charge collection. The device is optimized for detecting THz radiation in the 0.1-10 THz range, which penetrates clothing to reveal concealed objects or anomalies without ionizing radiation. An array of these MSPDs forms the core of a high-resolution THz imager for security applications.

• graph TD
      A[THz Radiation] --> B(THz MSPD Array - Si with Metallic-Coated Holes)
      B --> C{Electrical Output - THz Image Data}
      C --> D(Signal Processing Unit)
      D --> E[Reconstructed Image of Concealed Objects]
  

Derivative 2.3.2: Agricultural Sensing (Crop Health Monitoring)

• Enabling Description: A microstructure-enhanced photodetector is integrated into an agricultural drone for rapid, non-destructive crop health assessment. The MSPD employs a multi-junction structure (e.g., stacked Si and InGaAs layers) with distinct microstructures in each junction, enabling precise spectral analysis of reflected sunlight (e.g., specific chlorophyll absorption bands, water content bands). The dielectric covering layer over the holes is tuned to reduce reflection in relevant agricultural spectral windows. The collected spectral data, indicative of plant stress, disease, or nutrient deficiency, is processed on-board for real-time actionable insights.

• graph TD
      A[Sunlight (Reflected from Crop)] --> B(Multi-Junction MSPD - Si/InGaAs with Tuned Microstructures)
      B --> C{Electrical Output - Spectral Signature}
      C --> D(On-board Processing Unit)
      D --> E[Crop Health Metrics (e.g., NDVI, Water Stress)]
  

2.4 Integration with Emerging Tech Derivatives

Derivative 2.4.1: Quantum Dot (QD) Tunable Absorption Layers

• Enabling Description: A microstructure-enhanced photodetector incorporates a layer of colloidal quantum dots (QDs) as the intermediate absorption material, deposited within and around the microstructured holes. The QDs (e.g., PbS, CdSe) are spectrally tunable by controlling their size, allowing the MSPD's absorption peak to be dynamically adjusted or multiplexed. The holes are filled with a matrix material (e.g., polymer, transparent oxide) embedding the QDs, and an overlying dielectric layer ensures light guidance. The P and N layers are transparent conductors (e.g., Indium Tin Oxide - ITO) flanking the QD layer. This configuration allows for multi-spectral detection or reconfigurable spectral response in a single device.

• graph TD
      A[Optical Input] --> B(Transparent Top P-ITO Layer)
      B --> C(Intermediate QD-Filled Holes in Matrix)
      C --> D(Transparent Bottom N-ITO Layer)
      D --> E(Substrate)
      E --> F[Electrical Output (Spectrally Tunable)]
  

Derivative 2.4.2: Plasmonic Metasurface for Enhanced Light Trapping

• Enabling Description: A microstructure-enhanced photodetector integrates a plasmonic metasurface on its incident surface, directly above or co-fabricated with the microstructured holes. The metasurface consists of an array of patterned metallic nanostructures (e.g., gold or silver nano-antennas, gratings) designed to excite surface plasmon polaritons (SPPs) at specific wavelengths. These SPPs enhance the local electromagnetic field and couple light into the underlying semiconductor's microstructure holes, significantly increasing the effective optical path length and absorption within the intermediate layer. The holes themselves act as further light traps, working in concert with the metasurface for superior quantum efficiency.

• graph TD
      A[Optical Input] --> B(Plasmonic Metasurface)
      B -- Enhanced Local Field --> C(Overlying Dielectric Layer)
      C --> D(Top Doped Layer)
      D --> E(Intermediate Layer with Microstructure Holes)
      E --> F(Bottom Doped Layer)
      F --> G(Substrate)
      G --> H[Electrical Output]
  

2.5 The "Inverse" or Failure Mode Derivatives

Derivative 2.5.1: Degraded Performance Mode for Extended Battery Life

• Enabling Description: A microstructure-enhanced photodetector, particularly for portable or remote applications, is designed for a "degraded performance" mode to conserve energy. This involves a control mechanism that can alter the electrical biasing of the P-I-N structure, reducing the reverse bias voltage applied to the intrinsic layer. While this decreases the electric field, leading to slower carrier collection and reduced quantum efficiency, it also significantly lowers the dark current and power consumption. The device can switch between full performance and degraded performance (e.g., 50% QE but 10% power consumption) based on system demands or available power, extending battery operational life without complete shutdown.

• stateDiagram
      [*] --> FullPerformance
      FullPerformance --> DegradedPerformance : Energy_Conservation_Command
      DegradedPerformance --> FullPerformance : Restore_Performance_Command
      FullPerformance : High QE, High Bandwidth, Higher Power Consumption
      DegradedPerformance : Lower QE, Slower Response, Ultra-low Power Consumption
  

Derivative 2.5.2: Damage-Tolerant Hole Array for Continued Operation After Partial Failure

• Enabling Description: A microstructure-enhanced photodetector incorporates a redundant or fault-tolerant design for its hole array. Instead of a uniform lattice, the holes are arranged in segments or sub-arrays, each with independent electrical readouts or local processing units. If a segment of holes is damaged (e.g., by physical impact, laser burn-in, or manufacturing defect), the active electronic circuit can detect the failure in that specific segment (e.g., by monitoring dark current or responsivity deviations) and electrically disconnect or disregard data from the damaged region. The remaining undamaged segments continue to operate, ensuring partial functionality of the photodetector rather than complete failure. The overarching dielectric layer can also have self-healing properties (e.g., polymer composites).

• graph TD
      A[Optical Input] --> B(MSPD - Segmented Hole Array)
      B --> B1(Segment 1)
      B --> B2(Segment 2)
      B --> B3(Segment 3)
      B1 & B2 & B3 --> C{Local Readout Circuits}
      C -- Fault Detection --> D(Active Electronic Circuit - Fault Management)
      D -- Disconnect/Disregard Faulty Segment --> C
      C --> E[Electrical Output - Degraded, but Functional]
  

Core Claim 25: Method of making a microstructure-enhanced photodetector

3.1 Material & Component Substitution Derivatives for Method

Derivative 3.1.1: Atomic Layer Deposition (ALD) for Heterogeneous Layers

• Enabling Description: A method of making a microstructure-enhanced photodetector comprises providing a silicon substrate. Instead of traditional epitaxial growth, the top, intermediate, and bottom layers are formed using Atomic Layer Deposition (ALD). For instance, the intermediate intrinsic layer can be ALD-grown Germanium (Ge), while the doped top and bottom layers are ALD-grown heavily doped Silicon Dioxide (SiO2) acting as transparent conductive oxides, or ALD-grown doped Aluminum Nitride (AlN). The holes are then formed in the ALD-Ge layer using a combination of self-assembled block copolymer lithography to define the mask and subsequent anisotropic ALD etching (e.g., using a plasma-enhanced ALD cycle) to create the high aspect ratio microstructures. The ALD process ensures conformal coating and precise thickness control for heterogeneous material systems.

• sequenceDiagram
      participant Substrate as S
      participant ALD_Ge as G
      participant ALD_Doped_SiO2 as D
      participant Lithography as L
      participant Etch as E
      S->G: ALD Ge (Intermediate Layer)
      G->L: Block Copolymer Lithography (Mask)
      L->E: Anisotropic ALD Etch (Hole Formation)
      E->D: ALD Doped SiO2 (Top/Bottom Layers)
      D->S: Final Device
  

Derivative 3.1.2: Femtosecond Laser Ablation for Complex Hole Geometries

• Enabling Description: A method of making a microstructure-enhanced photodetector involves providing a Germanium-on-Silicon (Ge-on-Si) wafer. The top, intermediate, and bottom layers are formed by epitaxial growth of doped and intrinsic Ge layers. Instead of traditional photolithography and wet/dry etching, the holes are formed using femtosecond laser ablation. A high-repetition-rate femtosecond laser is precisely focused and scanned across the Ge layer surface to directly ablate material, creating complex 3D hole geometries (e.g., spiral, multi-level structures) with nanoscale precision, which are difficult to achieve with conventional etching. This direct writing technique allows for rapid prototyping and fine-tuning of light-trapping structures without requiring elaborate masks.

• sequenceDiagram
      participant Wafer as W
      participant Epitaxy as E
      participant Laser as L
      W->E: Epitaxial Ge Layers (P-I-N)
      E->L: Femtosecond Laser Ablation (Hole Formation)
      L->W: Complex 3D Microstructures
  

3.2 Operational Parameter Expansion Derivatives for Method

Derivative 3.2.1: High-Throughput Fabrication on Large-Area Flexible Substrates

• Enabling Description: A method of making microstructure-enhanced photodetectors for large-scale flexible electronics involves providing a roll-to-roll polymer substrate (e.g., PEN or PET). The active layers (e.g., amorphous Silicon or organic semiconductors) are deposited using low-temperature physical vapor deposition (PVD) or solution-based coating techniques (e.g., spin coating, slot-die coating). The microstructure holes are formed by continuous, high-speed nanoimprint lithography (NIL) using a flexible stamp, followed by plasma etching or reactive ion etching (RIE) in a roll-to-roll processing tool. This enables manufacturing of large-area arrays of flexible photodetectors at significantly lower cost and higher throughput compared to wafer-based batch processing.

• sequenceDiagram
      participant RollSubstrate as RS
      participant PVD_Deposition as PVD
      participant Nanoimprint as NIL
      participant PlasmaEtch as PE
      RS->PVD: Deposit Active Layers (Roll-to-Roll)
      PVD->NIL: Nanoimprint Lithography (Hole Patterning)
      NIL->PE: Plasma Etch (Hole Formation)
      PE->RS: Flexible MSPD Array
  

Derivative 3.2.2: Atomic-Level Precision for Quantum Structure Integration

• Enabling Description: A method of making a microstructure-enhanced photodetector with embedded quantum structures requires atomic-level precision. This involves providing a Silicon substrate and forming epitaxial SiGe layers. The holes are created using advanced directed self-assembly techniques, where block copolymers are used to form masks with sub-10nm feature sizes, followed by highly selective atomic layer etching (ALE). Within these precisely defined holes, individual or arrays of quantum dots (e.g., Ge quantum dots) are grown in situ using self-limited epitaxial growth techniques. This method ensures single-digit nanometer control over hole dimensions and quantum dot placement, crucial for quantum information processing or ultra-sensitive single-photon detection.

• sequenceDiagram
      participant Substrate as S
      participant Epitaxy as E
      participant DirectedSelfAssembly as DSA
      participant ALE as AL
      participant QDG as QG
      S->E: Epitaxial SiGe Layers
      E->DSA: Directed Self-Assembly (Sub-10nm Mask)
      DSA->AL: Atomic Layer Etching (Precise Hole Formation)
      AL->QG: In-Situ Quantum Dot Growth (within holes)
      QG->S: Quantum-Enhanced MSPD
  

3.3 Cross-Domain Application Derivatives for Method

Derivative 3.3.1: Mass Production for Consumer Electronics (Miniaturized Sensors)

• Enabling Description: A method for mass production of microstructure-enhanced photodetectors for integration into consumer electronics (e.g., smartphones, wearables) focuses on cost-effective, high-volume manufacturing. This involves using standard 300mm silicon wafers. The top, intermediate, and bottom silicon layers are formed using established CMOS-compatible epitaxial growth and ion implantation techniques. The microstructure holes are patterned using deep ultraviolet (DUV) photolithography, followed by high-aspect-ratio deep reactive ion etching (DRIE) optimized for throughput and uniformity across the wafer. The process flow is integrated directly into existing foundry production lines, enabling the fabrication of millions of miniaturized, high-performance light sensors per wafer at low unit cost.

• flowchart TD
      A[300mm Si Wafer] --> B(CMOS-Compatible Epitaxy/Ion Implantation)
      B --> C(DUV Photolithography - Hole Mask)
      C --> D(High-Aspect-Ratio DRIE - Hole Etching)
      D --> E(Dielectric Deposition/Fill - Over holes)
      E --> F(Metallization/Interconnects)
      F --> G[Mass Produced MSPD Die]
  

Derivative 3.3.2: Customized Fabrication for Scientific Instruments (Spectrometer Arrays)

• Enabling Description: A method for fabricating custom microstructure-enhanced photodetector arrays for high-precision scientific instruments (e.g., space telescopes, laboratory spectrometers) emphasizes extreme optical performance and specialized integration. This begins with a custom SOI wafer. The active layers are grown using molecular beam epitaxy (MBE) to achieve highly controlled material compositions (e.g., superlattices for specific wavelength tunability). The microstructure holes are patterned using electron beam lithography for ultimate resolution and custom periodicity, followed by focused ion beam (FIB) milling for anisotropic etching. Each MSPD in the array can have unique hole parameters for precise spectral filtering, tailored to specific experimental requirements. Complex 3D integration techniques (e.g., wafer bonding, through-silicon vias - TSVs) are used for readout circuitry.

• flowchart TD
      A[Custom SOI Wafer] --> B(MBE Growth of Specialized Layers)
      B --> C(Electron Beam Lithography - Custom Hole Masks)
      C --> D(Focused Ion Beam Milling - Precise Hole Etching)
      D --> E(Custom Dielectric/Optical Coatings)
      E --> F(3D Integration with Readout Circuitry)
      F --> G[Specialized MSPD Array for Scientific Instrument]
  

3.4 Integration with Emerging Tech Derivatives for Method

Derivative 3.4.1: Robotic Automation and In-Situ Process Monitoring

• Enabling Description: A method of making microstructure-enhanced photodetectors is entirely performed by an autonomous robotic system within a cleanroom environment. Each fabrication step (e.g., substrate loading, epitaxial growth, lithography, etching, deposition) is executed by robotic arms and automated transfer systems. In-situ metrology tools (e.g., spectroscopic ellipsometry, atomic force microscopy, real-time optical emission spectroscopy during etching) provide continuous feedback on layer thickness, hole dimensions, and material properties. This real-time data is fed into a central control system that uses machine learning algorithms to adjust process parameters dynamically, compensating for variations and minimizing defects without human intervention, leading to higher yield and consistency.

• sequenceDiagram
      participant Robot as R
      participant System as S
      participant EpiTool as E
      participant LithoTool as L
      participant EtchTool as T
      R->S: Load Wafer
      S->E: Automated Epitaxial Growth
      E->S: In-Situ Metrology Data (Epi)
      S->L: Automated Lithography
      L->S: In-Situ Metrology Data (Litho)
      S->T: Automated Etching
      T->S: In-Situ Metrology Data (Etch)
      S->S: ML Process Optimization
      S->R: Unload Finished Wafer
  

Derivative 3.4.2: Machine Learning for Defect Detection and Process Optimization

• Enabling Description: A method of making microstructure-enhanced photodetectors utilizes machine learning (ML) for comprehensive defect detection and process optimization. After each critical fabrication step (e.g., hole etching, layer deposition), high-resolution imaging (e.g., SEM, optical profilometry) is performed across the entire wafer. The collected images are analyzed by convolutional neural networks (CNNs) trained to identify various types of defects (e.g., etch non-uniformities, missing holes, material impurities, critical dimension errors). Based on defect patterns and historical process data, the ML model identifies root causes and suggests adjustments to upstream and downstream process parameters (e.g., etch time, gas flow, growth temperature) to prevent recurrence and improve overall yield and device performance.

• flowchart TD
      A[Fabrication Step (e.g., Etch)] --> B(High-Resolution Imaging)
      B --> C(Image Data)
      C --> D{ML Model - CNN for Defect Detection}
      D -- Defect Report --> E(Process Analysis)
      E -- Optimization Recommendation --> F(Process Control System)
      F -- Adjust Parameters --> A
      D -- No Defects / Acceptable --> G[Next Fabrication Step]
  

3.5 The "Inverse" or Failure Mode Derivatives for Method

Derivative 3.5.1: Method for Selective Deactivation of Holes for Reconfigurable Performance

• Enabling Description: A method of making a microstructure-enhanced photodetector includes a post-fabrication step for selective deactivation or modification of specific hole regions to reconfigure its optical response or mitigate localized defects. After the initial formation of a dense array of microstructure holes in the intermediate layer, a localized deposition or filling technique (e.g., inkjet printing of an opaque material, localized laser-induced phase change in a transparent dielectric filling) is applied. This allows for disabling specific holes to change the effective active area, tuning the spectral response, or bypassing identified defective regions in the hole array, thereby enabling reconfigurable performance or improving yield by salvaging partially defective devices.

• flowchart TD
      A[Standard MSPD Fabrication] --> B(Form Dense Hole Array)
      B --> C(Characterize Hole Array / Detect Defects)
      C --> D{Local Modification Technique (e.g., Inkjet, Laser)}
      D -- Selective Deactivation/Modification --> E[Reconfigurable MSPD / Defect-Repaired MSPD]
  

Derivative 3.5.2: Self-Repairing Layer Formation Process

• Enabling Description: A method of making a microstructure-enhanced photodetector incorporates an in-situ self-repairing mechanism during layer formation. For instance, during the chemical vapor deposition (CVD) of the intermediate layer, a precursor material with embedded self-healing agents (e.g., microcapsules containing a polymer resin) is used. If micro-cracks or voids form in the growing layer (e.g., due to stress or particulate contamination), these agents are released and polymerize, automatically filling and repairing the defects. Similarly, during etching of the holes, an intelligent feedback system detects etch inconsistencies and momentarily pauses the etch, introducing a gas mixture that facilitates localized deposition to fill over-etched areas before resuming, thereby creating a more robust and uniform microstructure.

• sequenceDiagram
      participant GrowthTool as GT
      participant Detector as DT
      participant RepairAgent as RA
      GT->DT: Deposit Intermediate Layer (with self-healing precursors)
      DT->GT: In-situ Defect Detection
      alt Defect Detected
          DT->RA: Release Repair Agent
          RA->GT: Repair Defect in-situ
          GT->DT: Continue Deposition
      else No Defect
          GT->DT: Continue Deposition
      end
      GT->GT: Final Layer with Reduced Defects
  

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Combination Prior Art Scenarios

These scenarios combine aspects of US Patent 10,446,700 with existing open-source standards, thereby rendering further incremental improvements obvious.

1. Combination with IEEE 802.3 (Ethernet) Standards for High-Speed Optical Transceivers

• Description: The single-chip device of Claim 1, featuring a microstructure-enhanced photodetector (MSPD) monolithically integrated with an active electronic circuit (e.g., a transimpedance amplifier and limiting amplifier), is adapted for use in Ethernet optical transceivers compliant with IEEE 802.3 standards (e.g., 200GbE or 400GbE). The MSPD is specifically designed to detect optical signals at wavelengths common in fiber-optic communications (e.g., 850 nm, 1310 nm, 1550 nm) with enhanced quantum efficiency and high bandwidth (e.g., >50 Gbps per lane) due to the microstructures. The integrated electronic circuit provides the necessary signal processing to interpret the incoming data streams as per the Ethernet physical layer specifications (e.g., PAM4 modulation decoding), and outputs a processed electrical signal compatible with the Ethernet Media Access Control (MAC) layer. This integration significantly reduces the footprint, power consumption, and cost of high-speed optical modules.

• flowchart TD
      A[Optical Fiber Input (IEEE 802.3)] --> B(MSPD - Microstructure Enhanced)
      B --> C(Integrated TIA/LA)
      C --> D(Integrated DSP - PAM4 Decode, CDR)
      D --> E[Ethernet MAC Interface (IEEE 802.3)]
  

2. Combination with MIPI Alliance CSI-2 (Camera Serial Interface) Standard for Image Sensors

• Description: A microstructure-enhanced photodetector array, as described in Claim 16 (potentially with multiple MSPDs or a segmented array), is monolithically integrated with a MIPI CSI-2 compliant image signal processor (ISP) and interface circuitry on a single silicon chip. Each MSPD element in the array is optimized for light collection and conversion, and the microstructures enhance sensitivity across the visible spectrum. The integrated active electronic circuit (ISP) performs functions such as raw pixel data readout, noise reduction, color filter array demosaicing, and gamma correction, generating an image stream that adheres to the MIPI CSI-2 protocol. This enables high-performance, compact camera modules for mobile devices, automotive applications, and IoT imaging, benefiting from enhanced low-light performance due to the MSPD's high quantum efficiency.

• flowchart TD
      A[Optical Image Input] --> B(MSPD Array - Microstructure Enhanced)
      B --> C(Integrated Readout Circuitry)
      C --> D(Integrated Image Signal Processor - Demosaic, Noise Reduction)
      D --> E[MIPI CSI-2 Interface Output]
  

3. Combination with IEEE 802.11bb (Li-Fi) Standard for Optical Wireless Communication

• Description: The single-chip device of Claim 1, comprising a microstructure-enhanced photodetector (MSPD) and an active electronic circuit, is integrated into an optical wireless receiver compliant with the IEEE 802.11bb (Li-Fi) standard. The MSPD is optimized for detecting visible light (e.g., blue LED spectrum) or near-infrared signals modulated at high frequencies for Li-Fi data transmission, with its microstructures ensuring wide field-of-view and high responsivity. The integrated active electronic circuit functions as the Li-Fi physical layer (PHY), including automatic gain control (AGC), demodulation of the incoming optical signal (e.g., using orthogonal frequency-division multiplexing - OFDM), and error correction, producing a digital data stream compatible with higher network layers. This enables highly efficient and secure point-to-point or broadcast optical wireless communication links.

• flowchart TD
      A[Optical Li-Fi Signal (IEEE 802.11bb)] --> B(MSPD - Microstructure Enhanced)
      B --> C(Integrated TIA/AGC)
      C --> D(Integrated Li-Fi PHY - Demodulation, FEC)
      D --> E[Digital Data Output (Li-Fi MAC Interface)]