US 9859202

Analysis of U.S. Patent 9,859,202: Spacer Connector

Date of Analysis: April 30, 2026

This report provides a summary of United States Patent 9,859,202, including its key bibliographic data and a plain-language interpretation of its independent claims.

Bibliographic Information:

• Title: Spacer connector
• Assignee: TOPWIRE LLC
• Inventor: Dyi-chung Hu
• Filing Date: June 23, 2016
• Issue Date: January 2, 2018
• Abstract: A fabricating process for a spacer connector is disclosed. A core substrate with a plurality of through holes is prepared. A conductive carrier with a dielectric adhesive configured on a top surface is prepared. The core substrate is then pasted on a top surface of the dielectric adhesive layer. The dielectric adhesive exposed in the through hole is then etched. An electric plating process to form metal pillar in the core substrate is performed using the conductive carrier as one of the electrode.

Claim Analysis:

The patent contains one independent claim (Claim 1).

Independent Claim 1: Plain-Language Summary

Claim 1 of patent 9,859,202 describes a three-dimensional electronic package structure. This structure consists of:

• A bottom package substrate and a top package substrate stacked on top of each other.
• At least one spacer connector positioned between the two substrates. This spacer creates a defined gap or space between the top and bottom substrates.
• The spacer connector itself is made of a core substrate (like glass or silicon) with multiple metal pillars passing vertically through it.
• The top of each metal pillar on the spacer has a top metal pad.
• Crucially, the bottom end of each metal pillar extends or protrudes below the bottom surface of the spacer's core substrate.
• This entire assembly is used to house a bottom chip, which is mounted on the top surface of the bottom package substrate and sits within the space created by the spacer connectors. Specifically, the claim requires two spacer connectors placed on opposite sides of this bottom chip.
• The structure provides an electrical connection pathway from the top package substrate, through its own set of "bottom metal pillars," down to the spacer's metal pillars, and finally to the "top metal pillars" on the bottom package substrate.

In essence, the claim defines a stacked-chip package where a "spacer" with protruding-end connectors is used to create vertical space for a chip while simultaneously providing the electrical connections between the upper and lower boards.

Litigation Status:

A search of the Court of Appeals for the Federal Circuit (CAFC) dockets for the year 2026 was conducted. As of today's date, no litigation records specifically referencing US Patent 9,859,202 were found. However, this does not definitively rule out the possibility of ongoing or future litigation in other courts. The patent's public record on Google Patents indicates that its family has been involved in litigation, including a pending Inter Partes Review (IPR) proceeding (IPR2026-00303) at the Patent Trial and Appeal Board (PTAB) and cases in U.S. District Courts.