Prior art

Analysis of Prior Art for U.S. Patent 9,859,202

As a senior patent analyst, this report details the most relevant prior art cited against U.S. Patent 9,859,202, titled "Spacer connector." The analysis is based on the citations listed in the patent's file wrapper as of today's date, May 1, 2026. This examination is critical for understanding the landscape of existing technology at the time of the invention and is particularly relevant given the ongoing litigation and Inter Partes Review (IPR) proceedings involving this patent.

Under 35 U.S.C. § 102, a claim is anticipated if a single prior art reference discloses, either expressly or inherently, each and every element of that claim. The following analysis considers the potential for anticipation of the claims of the '202 patent, with a focus on independent claim 1.

Key Elements of Independent Claim 1 of US 9,859,202:

• A structure with a bottom and a top package substrate.
• At least one spacer connector creating a space between the substrates.
• The spacer connector comprises a core substrate with metal pillars passing through it.
• The bottom end of each metal pillar protrudes downwardly from the bottom surface of the core substrate.
• Top metal pads are on the top end of the spacer's pillars.
• The top and bottom substrates have their own metal pillars for connection to the spacer.
• A bottom chip is located in the space created by the spacer connectors.
• The structure includes two spacer connectors on opposite sides of the bottom chip.

---

Relevant Prior Art Citations

The following represents a selection of the most pertinent prior art cited by the examiner during the prosecution of the '202 patent.

1. U.S. Patent Application Publication No. US 2014/0167263 A1

• Full Citation: US 2014/0167263 A1, "Methods and Apparatus for Package with Interposers"
• Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
• Publication Date: June 19, 2014 (Filed: December 13, 2012)
• Brief Description: This reference describes a semiconductor package that uses an interposer to connect a top package to a bottom package. The interposer contains through-vias that provide electrical connections. The structure is designed to accommodate a die in the space between the packages, similar to the arrangement in the '202 patent. Figures 1 and 2, for instance, show a package-on-package structure with an interposer separating two substrates, with a die mounted on the lower substrate.
• Potential Anticipation: This reference is highly relevant and could be argued to anticipate the core elements of Claim 1. It discloses a stacked structure with top and bottom substrates, an interposer (spacer connector), and a chip located in the resulting cavity. The key question for a § 102 challenge would be whether the through-vias in the '263 publication are explicitly shown or described as "protruding downwardly from a bottom surface of the core substrate" of the interposer, as required by claim 1 of the '202 patent. While the electrical connection is present, the specific structural detail of the protruding pillar end is a critical limitation.

2. U.S. Patent No. US 6,366,467 B1

• Full Citation: US 6,366,467 B1, "Dual-socket interposer and method of fabrication therefor"
• Assignee: Intel Corporation
• Publication Date: April 2, 2002 (Filed: March 31, 2000)
• Brief Description: The '467 patent discloses an interposer used to connect two circuit boards. This interposer creates a space between the boards, which can house electronic components. The invention is aimed at creating a dual-socket system where the interposer provides the necessary electrical pathways and physical spacing.
• Potential Anticipation: This reference teaches the general concept of using an interposer to create space and provide electrical connections between two substrates, which relates to Claim 1. However, it is less likely to be considered a direct anticipation under § 102. The specific claimed structure in the '202 patent, including the defined arrangement of two spacer connectors on opposite sides of a bottom chip and the requirement for the metal pillars to protrude from the core substrate, may not be explicitly present in this older reference from Intel.

3. U.S. Patent Application Publication No. US 2005/0194672 A1

• Full Citation: US 2005/0194672 A1, "Stacked packages and systems incorporating the same"
• Assignee: Tessera, Inc.
• Publication Date: September 8, 2005 (Filed: November 4, 2003)
• Brief Description: This publication details various stacked semiconductor package configurations. It describes structures where one package is mounted on top of another, often with an interposer or spacer element to manage the connection and spacing. The goal is to increase component density in electronic devices.
• Potential Anticipation: The '672 publication discloses stacked package assemblies that are structurally similar to that claimed in the '202 patent. It is relevant to Claim 1 as it describes the fundamental package-on-package architecture. An argument for anticipation would depend on whether a specific embodiment within the '672 publication shows the combination of a spacer with protruding pillars, creating a cavity for a chip that is flanked by the spacer elements. This reference would likely be a significant part of any invalidity contention, either alone or in combination with other art.

4. U.S. Patent Application Publication No. US 2015/0061095 A1

• Full Citation: US 2015/0061095 A1, "Package-on-package devices, methods of fabricating the same, and semiconductor packages"
• Assignee: Mi-Na Choi
• Publication Date: March 5, 2015 (Filed: August 29, 2013)
• Brief Description: This reference, published before the priority date of the '202 patent, describes package-on-package (PoP) devices. It includes descriptions of spacer elements used to achieve the desired stacking height and to provide electrical connections between the upper and lower packages.
• Potential Anticipation: This is another strong reference against Claim 1. As a more contemporary publication, it addresses similar challenges in 3D packaging. The analysis for anticipation would hinge on the same critical detail as with other references: the explicit disclosure of a spacer connector whose metal pillars protrude downward from the bottom surface of its core substrate, in a configuration that creates a space for a chip. The proximity of its publication date to the '202 patent's priority date makes it a key piece of prior art to consider.

Disclaimer: This analysis is based on the cited references on the face of the patent and does not constitute a legal opinion on the validity of the patent's claims. A definitive conclusion on anticipation would require a detailed claim construction and a thorough comparison of the construed claims to the disclosures of the prior art references, typically performed as part of formal legal proceedings like the ongoing IPRs.