US 9859202

Analysis of U.S. Patent 9,859,202: Spacer Connector

Date of Analysis: April 30, 2026

This report provides a summary of United States Patent 9,859,202, including its key bibliographic data and a plain-language interpretation of its independent claims.

Bibliographic Information:

• Title: Spacer connector
• Assignee: TOPWIRE LLC
• Inventor: Dyi-chung Hu
• Filing Date: June 23, 2016
• Issue Date: January 2, 2018
• Abstract: A fabricating process for a spacer connector is disclosed. A core substrate with a plurality of through holes is prepared. A conductive carrier with a dielectric adhesive configured on a top surface is prepared. The core substrate is then pasted on a top surface of the dielectric adhesive layer. The dielectric adhesive exposed in the through hole is then etched. An electric plating process to form metal pillar in the core substrate is performed using the conductive carrier as one of the electrode.

Claim Analysis:

The patent contains one independent claim (Claim 1).

Independent Claim 1: Plain-Language Summary

Claim 1 of patent 9,859,202 describes a three-dimensional electronic package structure. This structure consists of:

• A bottom package substrate and a top package substrate stacked on top of each other.
• At least one spacer connector positioned between the two substrates. This spacer creates a defined gap or space between the top and bottom substrates.
• The spacer connector itself is made of a core substrate (like glass or silicon) with multiple metal pillars passing vertically through it.
• The top of each metal pillar on the spacer has a top metal pad.
• Crucially, the bottom end of each metal pillar extends or protrudes below the bottom surface of the spacer's core substrate.
• This entire assembly is used to house a bottom chip, which is mounted on the top surface of the bottom package substrate and sits within the space created by the spacer connectors. Specifically, the claim requires two spacer connectors placed on opposite sides of this bottom chip.
• The structure provides an electrical connection pathway from the top package substrate, through its own set of "bottom metal pillars," down to the spacer's metal pillars, and finally to the "top metal pillars" on the bottom package substrate.

In essence, the claim defines a stacked-chip package where a "spacer" with protruding-end connectors is used to create vertical space for a chip while simultaneously providing the electrical connections between the upper and lower boards.

Litigation Status:

A search of the Court of Appeals for the Federal Circuit (CAFC) dockets for the year 2026 was conducted. As of today's date, no litigation records specifically referencing US Patent 9,859,202 were found. However, this does not definitively rule out the possibility of ongoing or future litigation in other courts. The patent's public record on Google Patents indicates that its family has been involved in litigation, including a pending Inter Partes Review (IPR) proceeding (IPR2026-00303) at the Patent Trial and Appeal Board (PTAB) and cases in U.S. District Courts.

Litigation and Administrative Challenges Involving U.S. Patent 9,859,202

As of April 30, 2026, U.S. Patent No. 9,859,202, assigned to TOPWIRE LLC, is the subject of multiple legal and administrative challenges. The patent, which covers a "spacer connector" for semiconductor packaging, is being actively asserted by its owner, leading to litigation in federal courts and invalidity challenges at the Patent Trial and Appeal Board (PTAB).

District Court Litigation:

TOPWIRE LLC has initiated patent infringement lawsuits against major technology companies in two prominent patent litigation venues. The defendants are accused of infringing the '202 patent through the sale of smartphones featuring double-layered logic boards.

• Case 1:

  • Plaintiff: Topwire LLC
  • Defendant(s): SAMSUNG ELECTRONICS CO., LTD. and SAMSUNG ELECTRONICS AMERICA, INC.
  • Jurisdiction: U.S. District Court for the Eastern District of Texas
  • Case Number: 2:25-cv-01183
  • Filing Date: December 1, 2025
  • Status: The case is currently active. Judge Rodney Gilstrap is presiding.

• Case 2:

  • Plaintiff: Topwire LLC
  • Defendant(s): Apple, Inc.
  • Jurisdiction: U.S. District Court for the Western District of Texas
  • Case Number: 7:25-cv-00551
  • Filing Date: December 1, 2025
  • Status: This case is active and has been assigned to Judge Alan D. Albright.

Patent Trial and Appeal Board (PTAB) Proceedings:

In response to the infringement suits, both Apple and Samsung have filed petitions for Inter Partes Review (IPR) with the PTAB, seeking to invalidate the claims of the '202 patent. IPR is a trial proceeding conducted at the USPTO to review the patentability of claims of an issued patent.

• Case 1:

  • Petitioner: Apple Inc.
  • Patent Owner: Topwire LLC
  • Case Number: IPR2026-00303
  • Filing Date: March 16, 2026
  • Status: Pending

• Case 2:

  • Petitioner(s): [Samsung Electronics America Inc.](/litigations/by-plaintiff/Samsung%20Electronics%20America%20Inc.) and Samsung Electronics Co Ltd.
  • Patent Owner: Topwire LLC
  • Case Number: IPR2026-00324
  • Filing Date: March 31, 2026
  • Status: Pending

Proceedings overview

U.S. Patent 9,859,202 is currently the subject of two active Inter Partes Review (IPR) proceedings at the Patent Trial and Appeal Board (PTAB). Both IPRs are in the preliminary stages and are pending institution decisions, meaning no claims have yet been invalidated or sustained by the PTAB. This indicates an active defensive posture by asserted parties against the patent.

IPR2026-00303 — [Apple Inc.](/litigations/by-plaintiff/Apple%20Inc.) v. Topwire LLC

• Type: Inter Partes Review
• Filed: 2026-03-16
• Status: Pending. This proceeding is in the pre-institution phase, awaiting a decision from the Director of the USPTO on whether to institute a trial.
• Judge panel: Not yet assigned or publicly available, as the institution decision is now made by the Director, followed by panel assignment if instituted.
• Petition grounds: Specific claims challenged, prior art references, and statutory bases (§ 102 / § 103 / § 112) are not yet publicly detailed in the search results but would typically allege unpatentability under 35 U.S.C. §§ 102 and/or 103.
• Institution decision: Not yet issued. The deadline for the institution decision is typically six months from the petition filing date, placing it around September 16, 2026.
• Final Written Decision: Not applicable; no institution decision has been rendered.
• Settlement / termination: No information regarding settlement or termination is available.
• Appeal: Not applicable; the proceeding has not reached a Final Written Decision.
• Defensive value: The existence of this IPR signifies a direct challenge to the patent's validity by Apple Inc. The outcome of the institution decision, expected around September 2026, will be crucial in determining the near-term defensive landscape.

IPR2026-00324 — [[[Samsung Electronics Co.](/litigations/by-defendant/Samsung%20Electronics%20Co.), Ltd.](/litigations/by-plaintiff/Samsung%20Electronics%20Co.%2C%20Ltd.) et al.](/litigations/by-plaintiff/Samsung%20Electronics%20Co.%2C%20Ltd.%20et%20al.) v. Topwire LLC

• Type: Inter Partes Review
• Filed: 2026-03-31
• Status: Pending. This proceeding is also in the pre-institution phase, awaiting a decision from the Director of the USPTO on whether to institute a trial.
• Judge panel: Not yet assigned or publicly available, as the institution decision is now made by the Director, followed by panel assignment if instituted.
• Petition grounds: Specific claims challenged, prior art references, and statutory bases (§ 102 / § 103 / § 112) are not yet publicly detailed in the search results but would typically allege unpatentability under 35 U.S.C. §§ 102 and/or 103.
• Institution decision: Not yet issued. The deadline for the institution decision is typically six months from the petition filing date, placing it around September 30, 2026.
• Final Written Decision: Not applicable; no institution decision has been rendered.
• Settlement / termination: No information regarding settlement or termination is available.
• Appeal: Not applicable; the proceeding has not reached a Final Written Decision.
• Defensive value: This IPR represents a separate, independent challenge to the patent's validity by Samsung. Its pendency indicates a multi-pronged attack on the patent, and its outcome, expected around September 2026, will add to the overall picture of the patent's strength.

Strategic summary

As of May 29, 2026, all claims of US 9,859,202 are currently UNTESTED by any Final Written Decision from the PTAB. Both IPR2026-00303 and IPR2026-00324 are in their nascent stages, specifically awaiting institution decisions from the USPTO Director. Therefore, no claims have been canceled or sustained by the PTAB at this point.

The estoppel landscape under 35 U.S.C. § 315(e)(2) is not yet relevant as no Final Written Decision has been issued in either proceeding. Estoppel would only apply to a petitioner (and its privies) for grounds raised or that reasonably could have been raised in a petition that leads to a final written decision. Since both Apple and Samsung are petitioners, their ability to raise future prior art grounds will depend on the outcomes of these IPRs and the scope of any Final Written Decisions.

A clear pattern signal is that two major technology companies, Apple Inc. and Samsung Electronics Co., Ltd., have each filed their own IPR petitions against this patent. This suggests that the patent's claims are perceived as a significant threat in ongoing or anticipated litigation, likely related to the infringement suits filed against them by TOPWIRE LLC. The fact that these IPRs were filed shortly after the district court cases against Apple and Samsung (both filed in December 2025) underscores a coordinated defensive strategy.

Recommended next steps

• For IPR2026-00303, the institution decision from the USPTO Director is anticipated around September 16, 2026.
• For IPR2026-00324, the institution decision from the USPTO Director is anticipated around September 30, 2026.
• Any defendant currently being asserted against should closely monitor the official PTAB dockets for IPR2026-00303 and IPR2026-00324 for the issuance of institution decisions. These decisions will indicate whether the PTAB believes there is a reasonable likelihood that at least one claim is unpatentable, allowing the trial to proceed. The recent change in PTAB policy, effective October 2025, means that the Director of the USPTO now personally makes the institution decision for IPRs and PGRs.

Inventors

• Dyi-chung Hu: Employer not determinable from the patent text or search results.

Original assignee

The original assignee named on the issued patent is Individual. However, Google Patents lists the "Current Assignee" as TOPWIRE LLC. Given the later assignment record, it's more accurate to treat TOPWIRE LLC as the first recorded assignee of record.

TOPWIRE LLC's primary line of business and whether they ship a product embodying the claims are not explicitly stated in the patent or readily determinable from the search results. However, the ongoing litigation against Samsung and Apple suggests a focus on patent assertion rather than product manufacturing. TOPWIRE LLC is currently an operating entity, actively asserting its patents.

Assignment timeline

• 2025-03-14 (executed) / recorded 2025-04-27 — Reel 071083/0509
  • Conveyance: ASSIGNMENT OF ASSIGNORS INTEREST
  • Assignor: HU, DYI-CHUNG, DR.
  • Assignee: TOPWIRE LLC
  • Correspondent: Not specified in available data.
  • Context: Transfer-to-asserter (from inventor to LLC)

If there are more assignments, they are not publicly recorded in the USPTO Assignment Center as of today's date.

Timeline diagram

timeline
    title Ownership of US 9859202
    2016 : Filed by Dyi-chung Hu
    2018 : Issued
    2025 : Assigned to TOPWIRE LLC
         : First infringement suits filed

NPE / troll-pattern signals

1. Shell-entity transfer — Present. The patent was assigned from the individual inventor, Dyi-chung Hu, to TOPWIRE LLC. TOPWIRE LLC's name, lack of apparent product sales, and current activity primarily as a plaintiff in patent infringement lawsuits (as evidenced by the ongoing district court cases against Samsung and Apple) strongly indicate it functions as a licensing-only or assertion-focused entity.
2. Known asserter in the chain — Unclear. While TOPWIRE LLC is actively asserting this patent, it does not currently match the names of the high-frequency plaintiffs or known NPEs provided in the prompt (e.g., Acacia Research Corp, Marathon Patent Group, Intellectual Ventures, IPNav, Wi-LAN, Mosaid/Conversant, Vringo, Pendrell, Innovatio IP Ventures, MPHJ Technology, Lumen View Technology, Round Rock Research, Document Generation Corp, Erich Spangenberg entities).
3. Repeat correspondent across the chain — Not present. Only one assignment is recorded, and the correspondent information is not available in the provided data.
4. Cascading transfers — Not present. Only one assignment is recorded.
5. Pre-litigation transfer — Present. The assignment to TOPWIRE LLC was executed on March 14, 2025, and recorded on April 27, 2025 (Reel 071083/0509). The first infringement suits against Samsung and Apple were filed on December 1, 2025. This transfer occurred within six months of the initial litigation filings, indicating a likely strategic transfer to enable assertion.
6. Bankruptcy fire-sale — Not present. There is no indication of bankruptcy proceedings for the inventor or TOPWIRE LLC.
7. Privateering — Unclear. There is no publicly available information to suggest an operating company transferred the patent to TOPWIRE LLC to assert on its behalf against competitors.
8. Defensive aggregator (anti-NPE) — Not present. The patent is currently held by TOPWIRE LLC, which is actively asserting it, not a defensive aggregator.

Verdict

NPE — high confidence

This verdict is based on two strong signals: the transfer of the patent from the individual inventor to a named LLC (TOPWIRE LLC) with no apparent product sales (indicating a shell entity), and the timing of this transfer within six months prior to the filing of infringement lawsuits against major technology companies. These actions are highly indicative of a patent assertion entity's operating model.

Verification: https://assignmentcenter.uspto.gov/

Analysis of Prior Art for U.S. Patent 9,859,202

As a senior patent analyst, this report details the most relevant prior art cited against U.S. Patent 9,859,202, titled "Spacer connector." The analysis is based on the citations listed in the patent's file wrapper as of today's date, May 1, 2026. This examination is critical for understanding the landscape of existing technology at the time of the invention and is particularly relevant given the ongoing litigation and Inter Partes Review (IPR) proceedings involving this patent.

Under 35 U.S.C. § 102, a claim is anticipated if a single prior art reference discloses, either expressly or inherently, each and every element of that claim. The following analysis considers the potential for anticipation of the claims of the '202 patent, with a focus on independent claim 1.

Key Elements of Independent Claim 1 of US 9,859,202:

• A structure with a bottom and a top package substrate.
• At least one spacer connector creating a space between the substrates.
• The spacer connector comprises a core substrate with metal pillars passing through it.
• The bottom end of each metal pillar protrudes downwardly from the bottom surface of the core substrate.
• Top metal pads are on the top end of the spacer's pillars.
• The top and bottom substrates have their own metal pillars for connection to the spacer.
• A bottom chip is located in the space created by the spacer connectors.
• The structure includes two spacer connectors on opposite sides of the bottom chip.

---

Relevant Prior Art Citations

The following represents a selection of the most pertinent prior art cited by the examiner during the prosecution of the '202 patent.

1. U.S. Patent Application Publication No. US 2014/0167263 A1

• Full Citation: US 2014/0167263 A1, "Methods and Apparatus for Package with Interposers"
• Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
• Publication Date: June 19, 2014 (Filed: December 13, 2012)
• Brief Description: This reference describes a semiconductor package that uses an interposer to connect a top package to a bottom package. The interposer contains through-vias that provide electrical connections. The structure is designed to accommodate a die in the space between the packages, similar to the arrangement in the '202 patent. Figures 1 and 2, for instance, show a package-on-package structure with an interposer separating two substrates, with a die mounted on the lower substrate.
• Potential Anticipation: This reference is highly relevant and could be argued to anticipate the core elements of Claim 1. It discloses a stacked structure with top and bottom substrates, an interposer (spacer connector), and a chip located in the resulting cavity. The key question for a § 102 challenge would be whether the through-vias in the '263 publication are explicitly shown or described as "protruding downwardly from a bottom surface of the core substrate" of the interposer, as required by claim 1 of the '202 patent. While the electrical connection is present, the specific structural detail of the protruding pillar end is a critical limitation.

2. U.S. Patent No. US 6,366,467 B1

• Full Citation: US 6,366,467 B1, "Dual-socket interposer and method of fabrication therefor"
• Assignee: Intel Corporation
• Publication Date: April 2, 2002 (Filed: March 31, 2000)
• Brief Description: The '467 patent discloses an interposer used to connect two circuit boards. This interposer creates a space between the boards, which can house electronic components. The invention is aimed at creating a dual-socket system where the interposer provides the necessary electrical pathways and physical spacing.
• Potential Anticipation: This reference teaches the general concept of using an interposer to create space and provide electrical connections between two substrates, which relates to Claim 1. However, it is less likely to be considered a direct anticipation under § 102. The specific claimed structure in the '202 patent, including the defined arrangement of two spacer connectors on opposite sides of a bottom chip and the requirement for the metal pillars to protrude from the core substrate, may not be explicitly present in this older reference from Intel.

3. U.S. Patent Application Publication No. US 2005/0194672 A1

• Full Citation: US 2005/0194672 A1, "Stacked packages and systems incorporating the same"
• Assignee: Tessera, Inc.
• Publication Date: September 8, 2005 (Filed: November 4, 2003)
• Brief Description: This publication details various stacked semiconductor package configurations. It describes structures where one package is mounted on top of another, often with an interposer or spacer element to manage the connection and spacing. The goal is to increase component density in electronic devices.
• Potential Anticipation: The '672 publication discloses stacked package assemblies that are structurally similar to that claimed in the '202 patent. It is relevant to Claim 1 as it describes the fundamental package-on-package architecture. An argument for anticipation would depend on whether a specific embodiment within the '672 publication shows the combination of a spacer with protruding pillars, creating a cavity for a chip that is flanked by the spacer elements. This reference would likely be a significant part of any invalidity contention, either alone or in combination with other art.

4. U.S. Patent Application Publication No. US 2015/0061095 A1

• Full Citation: US 2015/0061095 A1, "Package-on-package devices, methods of fabricating the same, and semiconductor packages"
• Assignee: Mi-Na Choi
• Publication Date: March 5, 2015 (Filed: August 29, 2013)
• Brief Description: This reference, published before the priority date of the '202 patent, describes package-on-package (PoP) devices. It includes descriptions of spacer elements used to achieve the desired stacking height and to provide electrical connections between the upper and lower packages.
• Potential Anticipation: This is another strong reference against Claim 1. As a more contemporary publication, it addresses similar challenges in 3D packaging. The analysis for anticipation would hinge on the same critical detail as with other references: the explicit disclosure of a spacer connector whose metal pillars protrude downward from the bottom surface of its core substrate, in a configuration that creates a space for a chip. The proximity of its publication date to the '202 patent's priority date makes it a key piece of prior art to consider.

Disclaimer: This analysis is based on the cited references on the face of the patent and does not constitute a legal opinion on the validity of the patent's claims. A definitive conclusion on anticipation would require a detailed claim construction and a thorough comparison of the construed claims to the disclosures of the prior art references, typically performed as part of formal legal proceedings like the ongoing IPRs.

Obviousness Analysis of U.S. Patent 9,859,202 under 35 U.S.C. § 103

This analysis examines whether the invention described in U.S. Patent 9,859,202 ('202 patent) would have been obvious to a Person Having Ordinary Skill in the Art (PHOSITA) at the time the invention was made. The analysis is based on the prior art references cited during the patent's prosecution and is conducted under the framework of 35 U.S.C. § 103, considering the factors established in Graham v. John Deere Co.

A claim is obvious if the differences between the claimed invention and the prior art are such that the subject matter as a whole would have been obvious at the time the invention was made to a PHOSITA. A PHOSITA in the field of semiconductor packaging in June 2015 would likely have a bachelor's degree in electrical or mechanical engineering and several years of experience in designing and manufacturing integrated circuit packages, including package-on-package (PoP) and 3D stacking technologies.

Primary Obviousness Combination: US 2014/0167263 A1 ('263) in view of Known Engineering Principles

A strong argument for obviousness can be constructed by using US 2014/0167263 A1 ('263) as the primary reference, modified by well-established design principles known to a PHOSITA. The '263 publication discloses a package-on-package structure that teaches the majority of the elements of independent claim 1 of the '202 patent.

What '263 Discloses:
The '263 publication teaches a stacked semiconductor package structure comprising:

• A bottom package and a top package (Claim 1: "a bottom package substrate; a top package substrate stacked on top of the bottom package substrate").
• An interposer that separates the top and bottom packages, thereby creating a space between them (Claim 1: "at least one spacer connector interposed...to define a space").
• A die (chip) mounted on the bottom package and located within the space created by the interposer (Claim 1: "a bottom chip arranged in the space").
• The interposer contains through-vias that provide electrical connection between the packages (Claim 1: "a core substrate; a plurality of metal pillars, each passing through the core substrate").

Motivation to Modify '263:
A PHOSITA would have been motivated to modify the structure taught in '263 to arrive at the specific claimed invention of the '202 patent for at least two reasons, both of which represent predictable solutions to known problems.

1. Modifying the Interposer Vias to Protrude (Claim 1 limitation)

The critical limitation of claim 1 is that "a bottom end of each metal pillar...protrudes downwardly from a bottom surface of the core substrate." The '263 reference discloses through-vias for connection but may not explicitly show them protruding.

• Problem Known in the Art: A PHOSITA would have been well aware of the challenges in ensuring reliable solder connections between large, stacked components like interposers and substrates. Warpage of the components, manufacturing tolerances, and the need for consistent standoff height for underfill can all lead to poor or failed electrical connections.
• Obvious Solution: Modifying a connecting pillar or via to protrude slightly from its substrate surface was a known technique to address this problem. A protruding feature acts as a standoff, ensuring a more reliable and robust connection when soldering to another surface. It guarantees contact even with minor surface non-planarity and helps define a consistent bond line. Therefore, a PHOSITA seeking to improve the manufacturing yield and connection reliability of the '263 structure would have been motivated to modify the through-vias to protrude slightly. This modification is a simple application of a known technique to achieve a predictable result—a better electrical and mechanical connection.

2. Using Two Spacer Connectors Instead of a Single Interposer (Claim 1 limitation)

Claim 1 requires "two spacer connectors arranged on opposite sides of the bottom chip." The '263 publication illustrates a single interposer with a central opening for the die.

• Problem Known in the Art: Fabricating a single, large interposer from materials like silicon or glass with a large central cutout can be costly and lead to lower manufacturing yields due to the risk of breakage or defects. Furthermore, a single frame-like interposer can impede the flow of underfill or thermal interface materials around the chip it encloses.
• Obvious Solution: It would have been an obvious design choice to replace the single, frame-like interposer of '263 with two smaller, simpler spacer elements placed on opposite sides of the chip. This is a classic engineering trade-off. The motivation would be to:
  • Reduce Cost and Improve Yield: Manufacturing two smaller, rectangular spacers is typically cheaper and results in higher yields than one larger, more complex shape.
  • Improve Manufacturability: Using two separate spacers improves access to the cavity, allowing for easier and more complete flow of underfill or other encapsulants around the chip.
    This substitution of a single component for multiple, simpler components to improve cost and manufacturability is a routine practice in mechanical and package design.

Conclusion on Obviousness

The primary prior art reference, US 2014/0167263 A1, discloses the fundamental architecture of the claimed invention. A Person Having Ordinary Skill in the Art would have been motivated to modify the interposer in '263 to include the specific features recited in claim 1 of the '202 patent. Specifically, making the connecting pillars protrude to enhance connection reliability and splitting the single interposer into two spacers to reduce cost and improve manufacturability are both modifications that would have been obvious applications of known principles to achieve predictable results. Therefore, a strong case exists that the invention claimed in US 9,859,202 would have been obvious under 35 U.S.C. § 103.

Disclaimer: This analysis is based on the provided summaries of cited references and does not constitute a legal opinion on the validity of the patent's claims. A definitive conclusion on obviousness would require a more detailed claim construction and factual analysis, typically performed as part of formal legal proceedings.

Term, Adjustments, and Family Details for U.S. Patent 9,859,202

As of May 1, 2026, this analysis details the term status and related application information for U.S. Patent No. 9,859,202 ('202 patent).

Patent Term and Projected Expiration:

A standard U.S. patent has a term of 20 years from its earliest non-provisional filing date. The '202 patent was filed on June 23, 2016, as application number 15/190,695. This application claims priority from a provisional application (62/184,034) filed on June 24, 2015. However, the 20-year term is calculated from the non-provisional filing date.

• Filing Date: June 23, 2016
• Base Expiration Date (20 years from filing): June 23, 2036

Patent Term Adjustments (PTA) and Extensions (PTE):

• Patent Term Adjustment (PTA): A review of the patent's file history indicates that no Patent Term Adjustment was granted. PTA is awarded to compensate for delays caused by the U.S. Patent and Trademark Office (USPTO) during the prosecution of the patent. Since the time between the filing date (June 23, 2016) and the issue date (January 2, 2018) was less than three years and there were no other significant prosecution delays attributable to the USPTO, no PTA was accrued.
• Patent Term Extension (PTE): There is no indication of any Patent Term Extension for this patent. PTE is typically granted for patents covering products that undergo a lengthy pre-market regulatory review process, such as pharmaceuticals, and does not apply in this case.

Based on this information, the projected expiration date remains unaltered from the base date.

• Projected Expiration Date: June 23, 2036

This expiration date is contingent upon the timely payment of all required maintenance fees. These fees are due at 3.5, 7.5, and 11.5 years from the date of issuance.

Continuations and Divisional Applications:

A search of the USPTO database for applications related to the '202 patent reveals no continuation or divisional applications have been filed.

• Continuation Applications: None found. A continuation application would have allowed the applicant to pursue different claims based on the same specification while the original application was pending.
• Divisional Applications: None found. A divisional application could have been filed to pursue claims to an invention that was restricted out during the examination of the parent application.

Patent Family:

U.S. Patent 9,859,202 does not appear to have any direct foreign counterparts or other related U.S. patents that would constitute a patent "family" in the traditional sense. Its continuity data only points back to the single provisional application from which it claims priority.

• Priority Application: U.S. Provisional Application No. 62/184,034, filed June 24, 2015.
• Family Members: None found.

Defensive Disclosure of Derivative Inventions

Publication Date: May 1, 2026
Reference Patent: U.S. Patent 9,859,202 ("Spacer connector")
Field: Semiconductor Packaging, Microelectronics, System Integration.
Abstract: This document discloses a series of derivative inventions and improvements upon the core technology described in U.S. Patent 9,859,202. The purpose of this disclosure is to place these variations into the public domain, thereby establishing them as prior art to render obvious any future patent claims on these specific implementations. The disclosures herein are described in sufficient detail to enable a Person Having Ordinary Skill in the Art (PHOSITA) to practice the inventions.

---

Axis 1: Material & Component Substitution

Derivative 1.1: Flexible Spacer Connector for Conformal Electronics

• Enabling Description: The rigid core substrate (11) of the '202 patent is substituted with a flexible, high-temperature polyimide or liquid-crystal polymer (LCP) film. The metal pillars (15) are formed using a semi-additive plating process (SAP) to create meandering or serpentine copper traces through laser-drilled microvias in the polymer film. This allows the entire spacer connector to flex and conform to non-planar surfaces. The protruding bottom ends (155) are formed as compressible, C-shaped springs plated with gold over nickel, designed to make reliable contact with a corresponding pad on a flexible substrate without requiring solder, enabling repeated flexure. This structure is suitable for wearable electronics and flexible displays where components must bend.

• Mermaid Diagram:

  graph TD
      subgraph Top Flexible Substrate
          A[Bottom Pads]
      end
      subgraph Flexible Spacer Connector
          B(Flexible Core Substrate - Polyimide)
          C{Serpentine Copper Pillars}
          D(Top Metal Pads)
          E(Protruding C-Spring Contacts)
          B -- houses --> C
          C -- connects to --> D
          C -- forms --> E
      end
      subgraph Bottom Flexible Substrate
          F[Top Pads]
      end
      subgraph Mounted Component
          G[Flexible OLED/Sensor]
      end
  
      A --> D
      E --> F
      Bottom_Flexible_Substrate -- houses --> G
  

Derivative 1.2: High-Conductivity Ceramic Spacer for Thermal Management

• Enabling Description: The core substrate (11) is replaced with a high thermal-conductivity ceramic, such as Aluminum Nitride (AlN) or Beryllium Oxide (BeO), to act as a heat spreader. The metal pillars (15) are formed from a copper-molybdenum (CuMo) composite, providing a coefficient of thermal expansion (CTE) closely matched to the ceramic substrate and attached silicon dies, reducing thermally-induced stress. The pillars are fabricated by co-sintering the metal powder with the ceramic green sheet. The protruding bottom ends (155) are capped with a high-melting-point solder alloy (e.g., Gold-Tin, AuSn 80/20) for use in high-power applications like RF power amplifiers or laser diode modules, where efficient heat dissipation away from the chip is critical.

• Mermaid Diagram:

  graph LR
      subgraph RF Module
          Chip[GaN Power Amplifier]
          Spacer[Ceramic Spacer Connector]
          HeatSink[System Heat Sink]
  
          Chip -- mounted on --> Spacer
          Spacer -- conducts heat to --> HeatSink
  
          subgraph Spacer
              direction TB
              Core(AlN Ceramic Core)
              Pillars(CuMo Composite Pillars)
              Protrusions(AuSn Solder Tips)
              Core -- contains --> Pillars
              Pillars -- terminate in --> Protrusions
          end
      end
      Chip -- Electrical Path --> Pillars
      Protrusions -- Electrical/Thermal Path --> HeatSink
  

---

Axis 2: Operational Parameter Expansion

Derivative 2.1: Cryogenic Spacer Connector for Quantum Computing

• Enabling Description: This variation is designed for operation at cryogenic temperatures (< 4K). The core substrate (11) is fabricated from high-purity silicon to perfectly match the CTE of the chips and surrounding substrates, preventing mechanical failure during thermal cycling. The metal pillars (15) are made from a superconductor, such as niobium or a niobium-titanium alloy, deposited via physical vapor deposition (PVD) into etched through-silicon vias (TSVs). This eliminates resistive heating and signal loss for the sensitive quantum bits (qubits). The protruding ends (155) form direct-bond interconnects, where polished niobium surfaces are brought into contact under vacuum and pressure, forming a hermetic, superconducting electrical path without solder.

• Mermaid Diagram:

  sequenceDiagram
      participant QPU as Quantum Processing Unit
      participant Spacer as Cryogenic Spacer
      participant Control as Control Substrate
      QPU->>+Spacer: Transmit Qubit State Signal (via Niobium Pillar)
      Spacer->>+Control: Route Signal to Readout Electronics
      Control-->>-Spacer: Return Control Pulse
      Spacer-->>-QPU: Deliver Pulse to Qubit
  

Derivative 2.2: High-Frequency RF Spacer for 5G/6G Applications

• Enabling Description: To operate at frequencies above 100 GHz, the standard copper pillars are redesigned as micro-coaxial structures. The core substrate (11) is a low-loss dielectric material like fused silica or a PTFE composite. Each "pillar" is a through-via containing a central signal conductor separated from a grounded shielding wall by a dielectric (air or polymer). The protruding bottom end (155) is designed as a GSM (Ground-Signal-Ground) pad configuration for impedance-matched connection to a waveguide on the bottom substrate. This design minimizes signal crosstalk and insertion loss for millimeter-wave (mmWave) signals, essential for next-generation telecommunication modules.

• Mermaid Diagram:

  classDiagram
    class SpacerConnector {
      +coreSubstrate : FusedSilica
      +pillars : list~MicroCoaxVia~
    }
    class MicroCoaxVia {
      +centerConductor : Copper
      +dielectric : Air/PTFE
      +shielding : GroundedCopper
      +protrudingEnd : GSMPad
    }
    SpacerConnector "1" *-- "N" MicroCoaxVia : contains
  

---

Axis 3: Cross-Domain Application

Derivative 3.1: Aerospace - Vibration-Damped Avionics Stacking

• Enabling Description: In this application, the spacer connector is used to stack flight control modules. The core substrate (11) is a viscoelastic polymer composite that provides passive vibration damping. The protruding metal pillars (155) are designed as spring-loaded pogo pins that maintain positive contact force under high-G loading and mechanical shock. The entire assembly is housed in a sealed enclosure. This allows for dense, modular avionics packages where individual modules can be replaced in the field while ensuring extreme reliability in harsh environments.

• Mermaid Diagram:

  graph TD
      A[Flight Computer] -- Damped Connection --> B[Navigation Module]
      B -- Damped Connection --> C[Communications Module]
  
      subgraph Spacer Connector
          D(Viscoelastic Core)
          E{Pogo-Pin Pillars}
          F(Protruding Contact Heads)
          D -- embeds --> E
          E -- ends in --> F
      end
  
      A -- Uses Spacer --> B
      B -- Uses Spacer --> C
  

Derivative 3.2: AgTech - Modular Sensor Arrays in Vertical Farms

• Enabling Description: The spacer connector is used to build reconfigurable towers of environmental sensors for vertical farming. The core substrate (11) is a transparent polycarbonate, allowing light to pass through to lower layers. The pillars (15) carry power and data (e.g., I2C, CAN bus). The protruding ends (155) are designed as friction-fit, genderless connectors, allowing farm workers to easily stack or remove sensor modules (e.g., pH, humidity, spectral sensors) without tools. The space created by the spacer allows for airflow and prevents moisture buildup between modules.

• Mermaid Diagram:

  erDiagram
      SENSOR_MODULE ||--o{ SPACER_CONNECTOR : "connects via"
      SENSOR_MODULE {
          string ModuleID
          string SensorType "pH, Temp, Light"
      }
      SPACER_CONNECTOR {
          string CoreMaterial "Polycarbonate"
          string PillarType "Power+Data Bus"
      }
      SENSOR_TOWER ||--|{ SENSOR_MODULE : "is composed of"
      SENSOR_TOWER {
          string TowerID
          string Location
      }
  

Derivative 3.3: Automotive - Battery Management System (BMS) Interconnect

• Enabling Description: The spacer connector serves as an interconnect between layers of battery cells in an electric vehicle (EV) battery pack. The core substrate (11) is a fire-retardant ceramic composite. The pillars (15) are high-current-capacity copper busbars for power transfer and smaller, isolated signal pins for voltage and temperature monitoring of each cell. The protruding bottom ends (155) are shaped to be directly welded (e.g., ultrasonic or laser welding) to the battery cell terminals, providing a robust, low-resistance connection. The space created by the spacer acts as a channel for thermal management fluid or air.

• Mermaid Diagram:

  graph TD
      subgraph Battery Module
          Cell_Layer_1 --> Spacer_1
          Spacer_1 --> Cell_Layer_2
          Cell_Layer_2 --> Spacer_2
          Spacer_2 --> Cell_Layer_3
      end
  
      subgraph Spacer_1 [Spacer Connector]
          A(Fire-Retardant Core)
          B{High-Current Pillars}
          C{Sensor Pillars}
          D(Welded Protrusions)
          A -- holds --> B
          A -- holds --> C
          B & C --> D
      end
  

---

Axis 4: Integration with Emerging Tech

Derivative 4.1: AI-Optimized Thermal Spacer

• Enabling Description: This derivative integrates AI into the design phase. An AI model, trained on thermal simulation data (Finite Element Analysis), optimizes the placement, diameter, and material of each individual metal pillar (15) within the spacer substrate. The goal is to create a non-uniform pattern of pillars that actively channels heat from hotspots on the bottom chip to cooler regions of the top substrate or a heat sink. The protruding ends (155) may have varying heights, also determined by the AI, to fine-tune the thermal interface material (TIM) bond-line thickness for optimal thermal conductance. The output is a unique spacer design for each specific chip-pairing.

• Mermaid Diagram:

  flowchart LR
      A[Chip Layout & Power Map] --> B(AI Design Engine);
      C[Material Properties DB] --> B;
      B --> D{Generative Design Loop};
      D -- Run FEA Simulation --> E[Thermal Analysis];
      E -- Evaluate Performance --> D;
      D -- Converged Solution --> F[Optimized Pillar Layout G-Code];
      F --> G[Fabricate Custom Spacer];
  

Derivative 4.2: IoT-Enabled Predictive Maintenance Spacer

• Enabling Description: Micro-electromechanical systems (MEMS) sensors, such as strain gauges and temperature diodes, are fabricated directly onto the surface of the spacer's core substrate (11). A small microcontroller and RF transceiver are also embedded within the substrate. The metal pillars (15) provide power to this onboard circuitry. During operation, the spacer monitors the package's temperature and mechanical stress in real-time. If it detects parameters exceeding a safe threshold (indicating potential failure), it transmits a warning signal via a low-power wireless protocol (e.g., Bluetooth LE) to a central system manager. This enables predictive maintenance before a critical component fails.

• Mermaid Diagram:

  sequenceDiagram
      participant Chip as Packaged Chip
      participant Spacer as IoT Spacer
      participant Gateway as System Gateway
      loop Health Monitoring
          Spacer->>Spacer: Read embedded T°/Strain sensors
          alt Stress Threshold Exceeded
              Spacer-)+Gateway: Transmit Alert (MQTT)
              Gateway-)+Gateway: Log event & notify admin
          end
      end
  

---

Axis 5: The "Inverse" or Failure Mode

Derivative 5.1: Fusible Pillar Spacer for Over-Current Protection

• Enabling Description: The protruding bottom end (155) of each metal pillar is constructed from a precisely calibrated fusible alloy (e.g., a Bismuth-Tin alloy). This tip is engineered to have a higher electrical resistance than the main copper pillar. In the event of a downstream short circuit or a massive over-current event, the I²R heating at the protruding tip will cause it to melt and open the circuit before the protected chip or substrate is damaged. This turns the spacer into a high-density, non-resettable fuse array, providing granular protection at the package level.

• Mermaid Diagram:

  stateDiagram-v2
      [*] --> Normal_Operation
      Normal_Operation --> Fused_Open: Over-Current Event
      state Normal_Operation {
          description Current < I_max
      }
      state Fused_Open {
          description Protruding tip melts, circuit breaks
      }
      Fused_Open --> [*]
  

---

Combination Prior Art Scenarios

1. Combination with Open Compute Project (OCP) Standards: A large-scale version of the Automotive - BMS Interconnect spacer (Derivative 3.3) is designed to connect modular server blades in an OCP-compliant rack. The spacer uses a fire-retardant substrate and features blind-mate connectors on the protruding pillars that align with the OCP rack's backplane, allowing for hot-swapping of server components. The pillars carry both high-current DC power and high-speed data signals (e.g., PCIe Gen 6), conforming to the OCP electrical specifications.

2. Combination with MQTT Open Protocol: The IoT-Enabled Predictive Maintenance Spacer (Derivative 4.2) is configured to use the open-source MQTT (Message Queuing Telemetry Transport) protocol to publish its health data. The spacer's embedded microcontroller formats the sensor data (temperature, strain) into a JSON payload and publishes it to a specific MQTT topic, such as datacenter/rack04/server12/package_health. Any authorized MQTT subscriber can then monitor the real-time status of the semiconductor package, enabling integration with open-source dashboards like Grafana.

3. Combination with RISC-V ISA: A spacer connector is designed specifically for a System-in-Package (SiP) that stacks multiple RISC-V-based chiplets. The spacer's pillar layout is optimized for the AXI or TileLink bus protocols commonly used in the RISC-V ecosystem. The design itself, including the GDSII layout files for the spacer, is released as an open-source hardware project on a platform like GitHub, allowing anyone in the RISC-V community to fabricate or improve upon the spacer design for building custom multi-chiplet modules.