US 8334597

I'll verify against public sources before summarizing.

Let me check the PTAB/IPR and any CAFC activity involving this patent specifically.

US 8,334,597 B2 — Bibliographic Summary

(All values below are taken literally from the issued-patent record as presented in the Google Patents copy at https://patents.google.com/patent/US8334597/en, which is the authoritative text I was given; I did not auto-correct any identifier.)

Divisional chain (from the patent's own Cross‑Reference section): US 11/000,904 (filed 2004‑12‑02 → US 7,439,623) → US 12/241,896 (filed 2008‑09‑30 → US 7,632,751) → US 12/607,697 (filed 2009‑10‑28 → US 7,964,969) → US 13/104,484 (filed 2011‑05‑10 → US 8,334,597). Priority is claimed to Japanese Application 2003‑404437, filed 2003‑12‑03.

Recorded assignment chain (from USPTO assignment records surfaced in IPR exhibits): Panasonic Corp → Panasonic Semiconductor Solutions Co., Ltd. (recorded 2020‑05‑27) → Nuvoton Technology Corporation Japan (recorded 2024‑06‑12, change of name) → Advanced Integrated Circuit Process LLC ("AICP," Allen, TX), executed 2024‑07‑30, Reel 068118 / Frame 0314. That assignment instrument lists 25 properties including 8,334,597 (see TSMC Exhibit 1041, IPR2025‑01302, https://www.docketalarm.com/cases/PTAB/IPR2025-01302/).

Abstract (verbatim)

"A first insulating film is provided between a lower interconnect and an upper interconnect. The lower interconnect and the upper interconnect are connected to each other by way of a via formed in the first insulating film. A dummy via or an insulating slit is formed on/in the upper interconnect near the via."

Plain-language overview of the independent claims

Uncertainty notice: the copy of the patent I retrieved contained the Abstract and the full Description but not the issued "Claims" section. The following overview is therefore derived from the specification's Summary of Invention, which in this Panasonic divisional family tracks the claim language closely, but I cannot verify the issued claim numbering or which claims are independent from the material I retrieved. Verify against USPTO Patent Public Search / PatentCenter before relying on it.

The specification frames eight independent aspects — three device structures and four fabrication methods — all built on one technical idea: keep vacancies in a plated Cu interconnect from migrating into the working via (by giving them somewhere else to go, or by blocking them).

1. Structure 1 — dummy via reaching below the upper interconnect's interlayer film. A lower interconnect, an upper interconnect, a first insulating film between them, and a second insulating film beneath the first. The lower and upper interconnects are joined by a via in the first insulating film. At least one dummy via connects to the upper interconnect, the lower interconnect sits in the second insulating film, and the bottom of the dummy via is located in the second insulating film (i.e., deeper than the real via hole). The deeper hole gives a steeper stress gradient, so vacancies preferentially drain into the dummy via instead of the working via. Alternatives recited: the dummy via's bottom may land on a dummy interconnect in the second film (which doubles as an etch stop), or a third insulating film may be formed on the upper interconnect with the dummy via formed therein.

2. Structure 2 — insulating slit in the upper interconnect. Same lower/upper interconnect and first insulating film arrangement, with the via joining them, but instead of a dummy via, at least one insulating slit is formed in the upper interconnect. The slit is a non-conductive body (e.g., a left-behind piece of the interlayer dielectric) that lowers tensile stress near the via and acts as a physical barrier against atom/vacancy movement. Preferred geometry: rectangular slit, length 2–4× the via diameter (in one variant 2–10×), long side in contact with the via-connected portion; slit-to-via spacing ≤ 1 µm.

3. Structure 3 — dummy portion at the wide/narrow interconnect branch. The upper interconnect is divided into a wide first interconnect portion and a narrow second interconnect portion; the via connects to the narrow portion; at least one dummy portion is provided on the first insulating film connected to the upper interconnect; and the distance from the dummy portion to the branch point is smaller than the distance from the dummy portion to the far edge of the narrow portion. This captures vacancies before they enter the narrow, via-bearing leg. The advantage is described as especially pronounced when the narrow portion is ≤ 0.20 µm wide. The dummy portion may be connected to either interconnect portion, may mirror the via's shape or be rectangular, and may be within 1 µm of the branch point.

4. Method 1 (dual-damascene variant A). Deposit a first insulating film on a lower interconnect; form in it a via hole reaching the lower interconnect, at least one dummy hole nearby, and an upper interconnect trench connected to both; then deposit conductor to form the upper interconnect, the via, and a dummy via connected to the upper interconnect but insulated from the lower interconnect. The lower interconnect is formed in a second insulating film under the first, and the dummy hole is formed so its bottom is in the second insulating film. Via-hole-to-dummy-hole spacing preferably ≤ 1 µm.

5. Method 2 (dummy via formed after the upper interconnect). Deposit a first insulating film on a lower interconnect; form a via hole and an upper interconnect trench; deposit conductor to make the upper interconnect and via; then deposit a second insulating film on the upper interconnect, form a dummy hole in that second film reaching the upper interconnect near the via, and deposit conductor to form the dummy via.

6. Method 3 (insulating slit by masking). Deposit a first insulating film on a lower interconnect; form a via hole and an upper interconnect trench; and in that step leave part of the first insulating film in the trench near the via hole, thereby forming the insulating slit; then deposit conductor.

7. Method 4 (recess near the branch point). Deposit a first insulating film on a lower interconnect; form a via hole, an upper interconnect trench divided into a wide first trench and a narrow second trench, and a recess near the branch point between them; deposit conductor to form the upper interconnect, the via, and a dummy portion connected to the upper interconnect and insulated from the lower interconnect.

A damascene (e.g., dual-damascene) process is recited as suitable for each method.

Representative dimensions recited in the embodiments: lower interconnect width 0.2 µm; via diameter 0.20 µm; upper interconnect width 10 µm; via-to-dummy-via space 0.2 µm (preferably ≤ 1 µm, and ≤ 25 µm broadly); dummy via diameter 0.16 µm in the third embodiment; rectangular dummy trench 0.8 µm × 0.20 µm; slit 0.4 µm × 0.2 µm (sixth embodiment) and 0.8 µm × 0.2 µm (seventh embodiment). Materials: Cu conductor, PVD barrier film, SiN/SiO₂/FSG interlayer stack, plasma CVD deposition, plating fill, CMP planarization.

Litigation / docket posture — what I did and did not find

• I did not find any Federal Circuit 2026 docket, appeal, or scheduled oral argument specifically identifying US 8,334,597. I searched the CAFC scheduled-cases listing and general docket aggregation and located nothing naming this patent number. Treat that as "not found," not as proof of non-existence — CAFC dockets are keyed to appeal numbers, and a case involving this patent could exist under a number I did not surface.
• I also did not find an IPR petition specifically challenging US 8,334,597. The TSMC v. AICP petitions I located concern other patents: IPR2025‑01305 (U.S. 8,329,572 — discretionary denial, terminated 2025‑11‑20) and IPR2025‑01302 (also '572-related filings). The patents asserted by AICP against TSMC in E.D. Tex. 2:25‑cv‑00324 are 7,439,623; 7,632,751; 8,329,572; and 8,884,373 — i.e., two of this patent's direct family members ('623 and '751) but not 8,334,597 itself. See AICP's P.R. 3‑1(a) disclosures at https://ptacts.uspto.gov/ptacts/public-informations/petitions/[1558121](/patent/1558121)/ and the AICP v. TSMC complaint text (Ex. 2001 in IPR2025‑01302).
• The patent's own Google Patents record flags "Family has litigation," and the family-mate '751/'623 litigations (AICP v. TSMC, AICP v. UMC, E.D. Tex. 2:24‑cv‑00623 / 2:24‑cv‑00730 / 2:25‑cv‑00324, Judge Gilstrap) plausibly drive that flag. Whether '597 was ever separately asserted is something I could not confirm.
• Practical note consistent with the record: the patent's listed anticipated expiration is 2024‑12‑02 (20 years from the 2004‑12‑02 parent filing), and its status is "Expired – Lifetime." The AICP acquisition executed 2024‑07‑30, roughly four months before that date.

Confidence and caveats

• High confidence: title, inventor, filing/issue dates, priority, assignee history, divisional chain, abstract — all taken from the authoritative patent text supplied.
• Lower confidence: the exact issued claim set of US 8,334,597 (numbering, independence, and whether the issued claims map one-to-one onto the eight Summary-of-Invention aspects above). The claims section was absent from the material I retrieved. An earlier search result quoted claim 1 of the '751 patent (a method claim to forming a via hole, dummy hole, and interconnect trench) — that is a different patent and should not be imputed to '597.
• "Not found" rather than "does not exist": any CAFC 2026 appeal, IPR, or district-court assertion specifically naming 8,334,597.

I'll research litigation involving US patent 8334597 across patent litigation databases and court records.

Litigation Search Report — U.S. Patent No. 8,334,597

Bottom line: I found no litigation, IPR, PGR, ITC investigation, or other contested proceeding in which U.S. Patent No. 8,334,597 itself was asserted or challenged. The only appearance of the '597 patent in any litigation document I located is as one of 25 patents listed in an assignment exhibit used as evidence of ownership — not as an asserted or challenged patent. Details and the related family/portfolio proceedings are below.

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1. Ownership context (relevant to any suit)

The '597 patent is a divisional in the Harada / JP 2003-404437 family (via U.S. Pat. Nos. 7,439,623 → 7,632,751 → 7,964,969 → 8,334,597). Google Patents flags "Family has litigation" (Darts-ip family 34631679), but that flag is at the family level, and it is driven by suits asserting the sibling patents, not the '597 patent.

2. Related AICP enforcement campaign (asserted patents do not include the '597)

AICP has sued the two largest Taiwan foundries in the Eastern District of Texas. The patents I could confirm as actually asserted are:

A. AICP v. United Microelectronics Corporation, No. 2:24-cv-00730-JRG (E.D. Tex., Marshall Div.)

• Filed 09/06/2024 (CourtListener, Dkt. 1); consolidated with AICP v. TSMC, No. 2:24-cv-00623-JRG (member case).
• Seven asserted patents identified as the '227, '764, '686, '180, '076, '779 and '425 patents (collectively, per TSMC's stay briefing and the IPR exhibit lists).
• Status: active and heavily litigated as of the current date — Markman Memorandum & Opinion (Dkt. 204), extensive summary-judgment and sealing practice into 2026, mediation report and notice of compliance filed Aug./Sep. 2026.
• Docket: https://www.courtlistener.com/docket/69137887/advanced-integrated-circuit-process-llc-v-united-microelectronics/

B. AICP v. Taiwan Semiconductor Manufacturing Company Limited, No. 2:25-cv-00324-JRG (E.D. Tex., Marshall Div.)

• Filed on or about April 1, 2025; P.R. 3-1/3-2 disclosures served July 16, 2025 (Dkt. 45).
• Asserted claims are from U.S. Pat. Nos. 7,439,623, 7,632,751, 8,329,572 and 8,884,373 only.
• Complaint: https://ai-lab-cl-prod.azurewebsites.net/case/dct/txed/2:25-cv-00324/doc/analysis/99

C. PTAB proceedings (TSMC and UMC as petitioners against AICP)

• TSMC: IPR2025-00682 ('686), -00683 ('425), -00828 ('227), -00829 ('764), -00830 ('180), -00831 ('076), -00832 ('779), -01076 ('227), -01210 ('751), -01302 ('373).
• UMC: IPR2025-01092 ('180).
• IPR2025-01302 (TSMC v. AICP), filed 07/15/2025, instituted 01/09/2026, terminated 04/10/2026 due to post-institution settlement. This is the proceeding where the '597 appears — as Exhibit 1041 (the portfolio assignment), not as the challenged patent. Docket: https://www.docketalarm.com/cases/PTAB/IPR2025-01302/Taiwan_Semiconductor_Manufacturing_Company_Ltd._v._Advanced_Integrated_Circuit_Process_LLC/

None of the asserted-patent lists above include the '597 patent. Notably, two family siblings ('623 and '751) are asserted, which is a plausible reason '597 may have been held in reserve.

3. Cases involving the '597 patent

None identified. I found no complaint, counterclaim, IPR/PGR petition, ITC Section 337 investigation, or appellate proceeding naming U.S. Patent No. 8,334,597 as an asserted or challenged patent. I searched docket/brief text indexed at Docket Alarm, CourtListener, Justia, PTAB petition databases, Darts-ip/Google Patents family litigation data, and RPX litigation documents, filtering strictly on the literal number "8,334,597" / "8334597."

4. Caveats

• I am reporting only what the searched sources disclosed. District-court complaints and PTAB papers are not always text-searchable, and a newly filed or sealed case asserting the '597 patent could exist without appearing in these indexes.
• Live web results sometimes conflate the '597 patent with unrelated identifiers (e.g., the "833" design patent D851,833, or Brazilian commercial-registry entry 8334597, and Baby Jogger stroller patents). I excluded those.
• The Darts-ip "family litigation" indicator tells us only that some member of the Panasonic Harada family has been litigated worldwide; it does not establish that the '597 patent was itself asserted.

Recommended verification steps: (i) run a PACER/RECAP docket search on the exact string "8,334,597" across E.D. Tex. and other districts; (ii) check USPTO PTAB Patent Trial Appeal Board API/PATENTSVIEW for petitions naming 8,334,597; (iii) confirm with AICP's P.R. 3-1 disclosures in 2:25-cv-00324 and any amended disclosures, since AICP expressly reserved the right to supplement asserted claims.

I'll verify the structured data with web searches before drafting.

Let me pin down whether any of the AICP-related IPRs actually target 8,334,597 specifically.

Proceedings overview

Zero AIA trial proceedings are on file for US 8,334,597. The structured USPTO Open Data Portal block returns no IPR, PGR, or CBM for this patent as of the most recent ingest, and my independent web searches surfaced no petition, institution decision, FWD, or appeal naming U.S. Patent No. 8,334,597 as the challenged patent — by any petitioner, including in the 2025 TSMC/UMC campaigns against the current owner's portfolio. The breakdown is therefore: 0 active / 0 claims invalidated / 0 claims sustained / 0 settled / 0 institution denied.

Bottom line for a defendant: the patent is untested at the PTAB — not "hardened." There is no IPR estoppel, no cancelled claim to point at, and no FWD to cite. That cuts both ways: you have a clean slate to file, but you also get no free ride from someone else's work. The more important defensive facts are non-PTAB ones: (i) the patent is a 2003-priority Panasonic patent now owned by Advanced Integrated Circuit Process LLC (AICP), a Texas monetization entity, and (ii) Google Patents reports an anticipated expiration of 2024-12-02 with legal status "Expired – Lifetime." An expired patent cannot ground an injunction, and the damages window is closed (subject to the § 286 six-year lookback and any uncaptured PTA — verify against the USPTO Patent Term Adjustment record before relying on it).

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No proceedings to report

There is no ### {PROCEEDING_NUMBER} block to write, because there is no proceeding number. Per the task's own default rule, the answer is "no PTAB activity on file" for US 8,334,597.

What I verified. The '597 patent is the fourth member of a Panasonic/Winbond-Nuvoton divisional chain:

The '597 patent was not among the seven patents AICP asserted against TSMC/UMC in E.D. Tex. No. 2:24-cv-00623/-00730 ('227, '764, '686, '180, '076, '779, '425), nor among the four added in No. 2:25-cv-00324 ('623, '751, '572, '373). Because it was never asserted in those campaigns, no petition followed.

Caveat. I could not run a search of every historical PTAB docket back to 2012 within this task's tool budget. Given this is a low-volume, expired, never-asserted patent, a stale Panasonic-era IPR is unlikely — but before you certify "no IPRs" in a brief, pull the PTAB E2E docket for the patent number directly and confirm.

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Adjacent proceedings (different patents, same owner — context only)

These are not proceedings on the '597 patent. I list them because they define the litigation/estoppel weather around the owner and the family's shared specification and prior-art universe. Treat figures below as search-sourced and unverified against the ODP record.

• IPR2025-00682 / IPR2025-00683 — TSMC v. Advanced Integrated Circuit Process LLC, on U.S. Pat. No. 8,198,686 ('686). Filed 2025-03-26. On 2025-08-14 the Acting Director (Coke Morgan Stewart) denied Patent Owner's request for discretionary denial, letting TSMC proceed. (casemine)
• IPR2025-00828 / -00829 ('227) / -00830 ('180) / -00831 ('076) / -00832 ('779) — TSMC v. AICP. Director, Paper 17, 2025-09-03: institution discretionarily denied under 35 U.S.C. § 314(a), incorporating the IPR2025-00682/00683 analysis. (casemine) This is the single most important pattern signal in the portfolio: the Director used the March 26, 2025 workload-management interim process to knock out a five-petition TSMC wave.
• IPR2025-01076 ('227), IPR2025-01090 ('425, filed 2025-06-06), IPR2025-01093 ('076, filed 2025-06-05) — United Microelectronics Corp. v. AICP. IPR2025-01093 is listed as discretionary denial with an institution-decision date of 2025-10-09. (ipverse)
• IPR2025-01210 ('751), IPR2025-01211 / -01212 ('623) — TSMC v. AICP. The '751 petition asserts Watanabe and Hasunuma as anticipatory art and Watanabe+Kamoshima, +Fukazawa, +Iizuka, Hasunuma+Kurashima, Hasunuma+Watanabe, and Aoyagi (+Fukazawa) as § 103 combinations. (Docket Alarm exhibit) This art set is directly transferable work-product — the '597, '751, '623, and '969 patents share one specification.
• IPR2025-01302 ('373) — TSMC v. AICP. Filed 2025-07-15; instituted 2026-01-09; terminated-settled 2026-04-10 on a joint motion. (Docket Alarm)
• IPR2025-01305 ('572) — TSMC v. AICP, filed ~2025-07 (per TSMC's July 31, 2025 § 315(d)/§ 315(e) stipulation listing its petitions).

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Strategic summary

Claim status on 8,334,597: 100% UNTESTED. No claim of the '597 patent — independent or dependent — has been cancelled, confirmed, or even construed by the PTAB in an AIA trial. There is no surviving-claim list to give you, because there is no narrowing. If AICP's demand letter asserts the '597 patent, every claim it names is live and unadjudicated. Note the family contrast: the '623 parent and '751 grandparent are in active IPR (IPR2025-01211/-01212, IPR2025-01210), so the shared-specification claims could diverge quickly if '597 petitions follow.

Estoppel landscape. § 315(e)(2) estoppel is patent-specific and petitioner-specific. TSMC's and UMC's estoppel from the '227/'686/'425/'076/'779/'623/'751 petitions does not attach to the '597 patent, and AICP cannot use it against you. Conversely, if you file an IPR on '597 and it institutes, you will be estopped in the parallel district court case as to every ground you raised or reasonably could have raised under §§ 102/103 on patents and printed publications. Given the patent's expired status, weigh whether an IPR is worth the estoppel: your cheapest path may be a § 101/§ 112 or damages/standing defense in court rather than a PTAB validity fight over an expired asset.

Pattern signals. Three things stand out. (1) No defensive aggregator — I found no Unified Patents or RPX-filed challenge to this patent or its family; the petitioners here are commercial defendants (TSMC, UMC), not a subscription challenger. (2) The Director is the choke point, not the merits — the 2025-09-03 denial of five TSMC petitions was a § 314(a) discretionary denial, and the parallel E.D. Tex. case before Judge Gilstrap has generated competing stay motions and § 315(d) stipulations. Any new petition on '597 would face the same March 26, 2025 interim-process scrutiny, especially if the '597 patent lands in a parallel AICP suit. (3) The asset has a short runway — AICP took title on 2024-07-30 and the reported term expired four months later; the monetization play is retrospective damages, not injunctive.

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Recommended next steps

1. Confirm the negative directly. Pull the PTAB E2E / Patent Trial and Appeal Board End-to-End docket and the USPTO Assignment record for 8,334,597 before representing "no IPRs" to a court. My conclusion rests on the ODP block plus search, and I could not exhaustively sweep pre-2020 dockets.
2. Verify expiration and term adjustment. Confirm the reported 2024-12-02 expiration against the USPTO Patent Term Adjustment/terminal-disclaimer record. If it holds, move early on a no-injunction / damages-cutoff argument and check whether any asserted act falls outside the § 286 six-year window from the complaint.
3. Do not import family dispositions. The Director's 2025-09-03 discretionary denials and the IPR2025-01302 settlement are not merits rulings on '597's claims and create no estoppel or preclusion as to them. Any brief that cites them as if they adjudicated '597 is misrepresenting the record.
4. Mine the '751 petition as a template. If you do file, the Watanabe / Hasunuma / Aoyagi / Kamoshima / Fukazawa / Iizuka grounds in IPR2025-01210 attack the same specification your '597 claims descend from — start there, but re-map every limitation to '597's actual claims, which differ from '751's.
5. Expect a discretionary-denial fight. Budget for a Fintiv/§ 314(a) and General Plastic response, and consider a § 315(d)/§ 315(e) stipulation (as TSMC filed on 2025-07-31) to neutralize overlap arguments.
6. Watch for new petitions. Given AICP's pattern of serial assertion and its acquisition of 25 Nuvoton patents, a '597 petition — or a fresh AICP complaint adding '597 — is plausible. Set a docket alert on the patent number and on IPR2025-01210/-01211/-01212 for claim-construction crossover.

Uncertainty flags, stated plainly: (a) I found no evidence of any AIA proceeding on '597, but absence of search results is not proof of absence — the E2E docket is authoritative; (b) the expiration date of 2024-12-02 is Google Patents' "anticipated expiration" computation, expressly labeled an assumption by that source, and should be confirmed against PTA records; (c) the family-level proceeding details above come from secondary aggregators (Docket Alarm, ipverse, casemine) rather than the ODP record, and institutional-status labels should be re-checked before use in a filing.

I'll reconstruct the ownership chain using the patent's legal events plus targeted searches for the recorded assignments and the entities involved.

Strong data so far. Let me pin down the earlier links in the chain and the recurring correspondent.

Ownership Record — US 8,334,597 B2

Verification link: USPTO Assignment Center — search patent number 8334597. Recorded documents were confirmed via the USPTO assignment PDFs surfaced in PTAB/IPR exhibits (see reel cites below), cross-checked against Google Patents legal events, RPX Insight, and the Unified Patents litigation portal.

Important scope note: Google Patents' legal-events tab for this patent references a Darts-IP "first worldwide family litigation filed" flag. The specific chain below was reconstructed from the recorded assignments and litigation documents I could retrieve; where I could not capture a reel/frame I say so rather than guessing.

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Inventors

Pattern flags: None determinable. I found no evidence of inventor departures, and I did not locate a public record establishing Harada's post-2004 employment history. I am explicitly not inferring a departure pattern from the 2020 divestiture — the inventor record is simply low-visibility here. The relevant "people" pattern in this chain is not inventor-side; it is the single repeat attorney and the single managing-member LLC discussed below.

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Original assignee

Panasonic Corporation (as listed on the face of the granted patent; the 2004 applicant of record was Panasonic's predecessor corporate entity, Matsushita Electric Industrial Co., Ltd., which renamed to Panasonic Corporation in 2008 — I flag the name-transition as likely rather than confirmed from the assignment PDFs I retrieved).

• Line of business: Diversified electronics; the relevant unit was Panasonic Semiconductor Solutions Co., Ltd. (PSCS), a Kyoto-based developer/manufacturer of semiconductors.
• Did they ship a product embodying the claims? Yes — the patent claims a Cu multilevel interconnect with a dummy via/insulating slit to suppress voiding. This is a production-process patent for Panasonic's Cu damascene logic/interconnect manufacturing, and the specification frames the problem via electroplated-Cu vacancy migration actually observed in shipped devices ("the number of devices malfunctioning when being held at high temperature"). The claims are embodied in Panasonic's manufactured ICs rather than sold as a standalone article.
• Current status: Operating. The semiconductor business was divested — not liquidated: Panasonic announced the transfer on 2019-11-28 and completed it on 2020-09-01, selling PSCS (100% of shares) to Nuvoton Technology Corporation (TWSE: 4919; Winbond Electronics group). PSCS was renamed Nuvoton Technology Corporation Japan (NTCJ). No bankruptcy proceeding is involved anywhere in this chain.

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Assignment timeline

Entry detail

1 — Panasonic Corporation → Panasonic Semiconductor Solutions (recorded 2020-05-27)

• Conveyance: Assignment (internal restructuring)
• Correspondent: not captured; I could not retrieve the reel/frame, so I do not name a correspondent here.
• Context: Internal reorg ahead of the September 2020 sale.

2 — PSCS → Nuvoton Technology Corporation Japan (exec. 2020-09-01; rec. 2023-11-13, Reel 065552/0270)

• Conveyance: Change of Name (not an arm's-length transfer). The recorded cover sheet documents the Japanese corporate-registry renaming: Corporate Name "Panasonic Semiconductor Solutions Co., Ltd." → "Nuvoton Technology Corporation Japan," Changed R2.9.1 (September 1, 2020), Registered R2.9.2 (September 2, 2020); head office 1 Kotari-Yakemachi, Nagaokakyo City, Kyoto, Japan; Corporate Registration No. 1300-01-05277.
• Correspondent: not captured in the copy I retrieved.
• Context: Change of name only — a bookkeeping record of the 2020 rebrand.

3 — 2024-06-12 change-of-name event

• Shown in Google Patents legal events as CHANGE OF NAME (SEE DOCUMENT FOR DETAILS), assignor Panasonic Semiconductor Solutions Co., Ltd. This is most plausibly a later/companion confirmatory recording of the same 2020 renaming as entry 2. Reel/frame not captured.

4 — Nuvoton Technology Corporation Japan → Advanced Integrated Circuit Process LLC (exec. and rec. 2024-07-30, Reel 068118/0314–0317)

• Conveyance: Assignment (outright sale). Assignment ID PATI394110, attorney docket 0889-04193, submission ID 508677453. Executed by Nuvoton Technology Corporation Japan, signed "Kazehiro Koyama, President" (spelling per the recorded document's OCR).
• Assignee: Advanced Integrated Circuit Process LLC, a Texas limited liability company, address 825 Watters Creek Blvd., Suite 250, Allen, Texas 75013.
• Property list: 25 patents including US 8,334,597 (alongside 7,215,028; 7,400,045; 7,935,623; 8,329,572; 8,648,472; 7,439,623; 7,632,751; 7,964,969; 7,579,227; 7,923,764; 8,253,180; 8,587,076; 7,737,510; 8,039,968; 8,084,826; 8,198,686; 8,513,724; 8,536,704; 8,564,136; 8,729,641; 8,796,779; 8,884,373; 8,907,425; 8,969,970). RPX Insight lists 28 assets on the corresponding conveyances.
• Correspondent of record: SZYMON GURDA, 903 Commerce Dr., Suite 310, Oak Brook, IL 60523; email sgurda@cherskov.com; phone 312-621-1330; fax 312-621-0088. Repeat-player flag: this same correspondent and the identical docket number 0889-04193 appear on the AICP recording across multiple USPTO exhibits — i.e., Gurda is the recording attorney who filed the NPE-side conveyances in this family, not the litigator (litigation counsel of record for AICP are Susman Godfrey LLP and Miller Fair Henry PLLC, per Mondaq). Within this chain I can confirm only one link, so this is a partial signal.
• Context: Transfer-to-asserter. Two days later, on 2024-08-01, AICP filed its first complaint against TSMC.

If Assignment Center returns additional records

Two things I could not fully pin down and that a live Assignment Center pull would settle: (a) the reel/frame for the 2020-05-27 Panasonic Corp → PSCS assignment, and (b) the reel/frame for the 2024-06-12 change-of-name event. Neither changes the direction of the analysis.

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Timeline diagram

timeline
    title Ownership of US 8334597
    2003 : Japanese priority application filed
    2004 : US parent application filed by Panasonic
    2011 : Divisional filed by Panasonic Corp
    2012 : Patent issued as US 8334597
    2020 : IP consolidated in Panasonic Semiconductor Solutions
         : Semiconductor unit sold to Nuvoton
    2023 : Change of name recorded for Nuvoton Japan
    2024 : Assigned to Advanced Integrated Circuit Process LLC
         : TSMC suit filed two days later
         : Patent term expires

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NPE / troll-pattern signals

1. Shell-entity transfer — PRESENT.
US 8,334,597 moved out of an operating semiconductor manufacturer (Nuvoton Technology Corporation Japan, Winbond group) into Advanced Integrated Circuit Process LLC, a Texas LLC at 825 Watters Creek Blvd. Suite 250, Allen, TX 75013, per Reel 068118/0314–0317 (2024-07-30). Concrete, non-naming evidence: AICP was formed in Texas on 2024-06-12 — roughly six weeks before it took title; its sole managing member/sole owner is AMTL LLC, itself only formed in Delaware on 2024-04-01; and it shares its Allen, Texas address with a second newly formed ex-Panasonic acquirer, Advanced Memory Technologies LLC (Delaware, 2024-03-19). AICP identifies itself as NPE-classified. No products of its own are in commerce.

2. Known asserter in the chain — PRESENT.
AICP is not on the legacy lists (Acacia, Marathon, IV, Wi-LAN/Conversant, Pendrell, Round Rock, etc.), but it squarely meets the "surfaced by Unified Patents or RPX as a high-frequency plaintiff" prong: the Unified Patents litigation portal classifies the plaintiff as "NPE (Patent Assertion Entity)" in Advanced Integrated Circuit Process LLC v. TSMC, No. 2:25-cv-00324 (E.D. Tex., filed 2025-03-31). AICP is a serial filer against foundries: 2:24-cv-00623 v. TSMC (2024-08-01), 2:24-cv-00730 v. UMC (2024-09-06), 2:25-cv-00324 v. TSMC (2025-03-31/04-01) — with TSMC filing a wave of IPRs (IPR2025-00682, -00683, -00828 through -00832, -01302). Caveat: US 8,334,597 itself is not among the patents named in those complaints; the asserted set is '227, '764, '686, '180, '076, '779, '425 (first case) and '623, '751, '572, '373 (second case). '597 is in the transferred bundle and shares a specification with asserted family members '623/'751/'969, but I found no complaint asserting it.

3. Repeat correspondent across the chain — UNCLEAR (single confirmed appearance).
The only correspondent I can place on this chain is Szymon Gurda, sgurda@cherskov.com, 903 Commerce Dr. Suite 310, Oak Brook, IL 60523, on Reel 068118/0314 (docket 0889-04193). He does not appear on the Panasonic-side or Nuvoton-side links that I could retrieve. I therefore decline to call recurrence within this chain. What is notable is the role division: the entity that drafted the grant of "the exclusive right to sue for and collect past, present, and future damages" is the recording attorney (Gurda), while assertion is run by separate litigation counsel (Susman Godfrey / Miller Fair Henry) — a standard NPE split that keeps the recording agent separate from the courtroom team.

4. Cascading transfers — NOT PRESENT.
There is one LLC at the end of the chain, not a sequence of LLCs. The only rapid succession is the change-of-name event of 2024-06-12 immediately followed by the assignment of 2024-07-30 — but a name change is not a transfer, and the earlier 2020 links are corporate reorganization, not shell-to-shell hops. Two 2024 events in seven weeks is timing pressure, not a cascade of chained vehicles. (The common-principals tell does exist, but horizontally rather than vertically: AICP/AMTL share the Allen, TX address and counsel with Advanced Memory Technologies LLC.)

5. Pre-litigation transfer — PRESENT, and unusually tight.
Assignment executed and recorded 2024-07-30 (Reel 068118/0314); first infringement complaint filed 2024-08-01 — two days. The assignment expressly conveys "the exclusive right to sue for and collect past, present, and future damages… for infringement," i.e., standing was papered before filing. The suite of transferred patents maps almost one-to-one onto the patents later asserted ('227, '764, '686, '180, '076, '779, '425, '623, '751, '572, '373 all appear in the Reel 068118/0314 property list). This is a clean pre-litigation arrangement.

6. Bankruptcy fire-sale — NOT PRESENT.
Nothing in the record involves Chapter 7/11. Panasonic's exit was a negotiated business sale (announced 2019-11-28, closed 2020-09-01, all antitrust clearances obtained), and Nuvoton/Winbond is a solvent public company (TWSE: 4919). Note, however, that the economics resemble a fire-sale in a different sense: the patent was assigned ~4 months before its 2024-12-02 term expiry, i.e., AICP bought a largely burned-down asset as part of a bulk portfolio.

7. Privateering — NOT PRESENT on the evidence available.
The Reel 068118/0314 instrument is an outright sale of "entire right, title and interest… throughout the Universe" for consideration, with no license-back, no retained royalty share, and no field-of-use carve-out visible in the recorded text. That is a divestiture, not an operating company retaining an NPE as its proxy. I found no SEC disclosure, Patent Progress, or EFF coverage tying Nuvoton to direction or revenue-sharing on AICP's suits. (The letters rogatory AICP sought against Panasonic Corporation (Japan) and both Nuvoton entities in 2025 are third-party discovery against the former owners — consistent with a clean sale and an arms-length defendant, not with ally coordination.)

8. Defensive aggregator — NOT PRESENT.
The chain terminates at an asserting entity. No RPX, AST, LOT Network, Unified Patents, or OIN entity appears anywhere in the record.

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Verdict

NPE — high confidence.

Two strong signals plus one partial. First, a textbook shell-entity transfer: Reel 068118/0314–0317 (executed and recorded 2024-07-30) conveyed 25–28 ex-Panasonic assets including US 8,334,597 from operating maker Nuvoton Technology Corporation Japan to Advanced Integrated Circuit Process LLC, a Texas LLC formed 2024-06-12 whose sole owner is AMTL LLC (Delaware, formed 2024-04-01) and which shares an Allen, Texas suite with a sister acquirer. Second, a textbook pre-litigation transfer: the assignment closed 2024-07-30 and AICP's first TSMC complaint landed 2024-08-01, with the transferred list tracking the later-asserted patents almost exactly. The partial signal is the repeat correspondent (Szymon Gurda, Oak Brook, IL) — confirmed on only one link here, so I do not weight it as recurrence.

Caveats I want on the record: (i) US 8,334,597 itself is not named in the complaints I retrieved, so this is a portfolio-level NPE finding, not a patent-specific assertion finding; (ii) with a term ending 2024-12-02, any future claim would be limited to past damages inside the §286 reach-back; (iii) the 2020–2023 links are corporate reorganization and change of name, not shell activity, and I found no bankruptcy and no privateering evidence.

Verify at: USPTO Assignment Center — search 8334597.

I'll start by running targeted searches for the specific patent and its citation record.

Let me try more targeted searches for the citation record, including USPTO/Justia and the parent patent in the same family.

I found the citation record in the patent's front page. Let me verify details of each cited reference and check the current litigation/IPR context.

Retrieval note before the substance

My search tools could not reach USPTO PatentCenter/PAIR directly. I therefore grounded the citation list in US 8,334,597 B2 itself — specifically the front-page "(56) References Cited" block as it appears in the granted-patent PDF (patentimages.storage.googleapis.com/.../US8334597.pdf) — and cross-checked the family against the front pages of the sibling/ancestor patents. I did not substitute any similar patent number; the only numbers below are ones that appear literally in that record.

One discrepancy worth flagging under your "do not auto-correct" rule: the sibling US 7,632,751 front page lists its JP foreign reference as JP 2002-033384, while US 8,334,597 lists JP 2002-023384. I report the 8,334,597 list literally and do not harmonize the two.

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1. Verified bibliographic data for US 8,334,597 B2

Source: https://patents.google.com/patent/[US8334597B2](/patent/US8334597B2)/en and the granted PDF above.

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2. Complete list of references cited in US 8,334,597 B2

U.S. PATENT DOCUMENTS

FOREIGN PATENT DOCUMENTS

OTHER PUBLICATIONS (prosecution documents, not prior art): Translation of Notice of Reasons of Rejection; Chinese Office Action in CN 200410096561.2 dated Jul. 13, 2007; U.S. Notice of Allowance in 12/607,697 mailed Feb. 16, 2011; U.S. Notice of Allowance in 12/241,896 mailed Aug. 18, 2009; U.S. Notice of Allowance in 11/000,904 mailed Aug. 1, 2008.

Forward citation (not prior art): US 10,777,599 B2, Sep. 15, 2020, Kabushiki Kaisha Toshiba, "Solid state imaging device."

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3. Reference-by-reference analysis

3.1 US 6,717,267 B1 — Kunikiyo (the most relevant prior art)

• Full citation: US 6,717,267 B1, Tatsuya Kunikiyo. Title as displayed on Google Patents: "Semiconductor device having multilayer interconnection structure." A Google Patents sitemap entry for the same number renders the title as "Conductive dummy interconnections and conductive dummy plugs." I am flagging both renderings because I could not confirm which is the printed title from the document itself in this session. Assignee not verified in this session (Kunikiyo's contemporaneous filings are Mitsubishi Denki Kabushiki Kaisha).
• Date: granted Apr. 6, 2004 (front page of '597 lists "4/2004"); well before the Dec. 3, 2003 priority date.
• Brief description: Multi-level interconnect in which functional interconnections and dummy interconnections are buried in an interlayer insulating film, and functional plugs and dummy plugs (dummy vias) are formed in an overlying insulating film by dual-damascene processing, the dummy plugs connecting the upper interconnection to the dummy interconnections below. Fig. 12 shows interconnection 19C and dummy interconnection 21B in film 10; plug 29A and dummy plugs 26A/26B; interconnection 28A above. Kunikiyo uses the dummies for interconnection-density uniformity, CMP flatness, and shielding.
• Claim mapping: The '597 claim-1 elements map as: lower interconnect → interconnection 19C; upper interconnect → interconnection 28A (dual damascene with plug 29A); first insulating film → film 23; via → plug 29A; at least one dummy via connected to the upper interconnect → dummy plug 26B; second insulating film → interlayer insulating film 10; lower interconnect formed in the second insulating film → 19C in film 10; bottom of dummy via located in the second insulating film → dummy plug 26B landing on dummy interconnection 21B buried in film 10. Dependents also implicated: "bottom of the dummy via connected to a dummy interconnect formed in the second insulating film" (explicitly Fig. 12); "dummy via has a smaller diameter than the via" and "via/dummy via substantially circular" (via-to-dummy-interconnect width relationships and circular via shapes, per the petition's analysis); "dummy via substantially rectangular with its length along the same direction as the upper interconnect width" (Kunikiyo teaches varied dummy shapes).
• Practical significance: In the live PTAB proceeding, Kunikiyo (exhibit TSMC-1007) is asserted to anticipate claim 1 and to render numerous dependents obvious for the ancestor patent in this exact family. Because '597 shares that disclosure, Kunikiyo is the reference most likely to be asserted under § 102 against '597 as well.

3.2 US 6,919,637 B2 — He et al., Intel Corporation

• Full citation: US 6,919,637 B2, "Interconnect structure for an integrated circuit and method of fabrication," Intel Corporation.
• Dates: filed Sep. 30, 2002; granted Jul. 19, 2005. (Pre-dates the Dec. 3, 2003 priority date as to its filing; pre-dates it as to publication of any corresponding application.)
• Brief description: Cu/low-k interconnect structure and its fabrication method (the title is confirmed from the citation table, which shows this patent cited against the family's JP counterpart JP 4047324 B2).
• Claim mapping: I cannot responsibly map this reference to specific claims of '597 on the evidence gathered — the examiner cited it, so it bears on at least the general via/interconnect structure, but I did not retrieve its disclosure this session. Treat it as a probable § 102/§ 103 reference against the base claim(s) only, subject to verification.

3.3 US 7,439,623 B2 — Harada (asterisked, "cited by examiner")

• Full citation: US 7,439,623 B2, Takeshi Harada, "Semiconductor device having via connecting between interconnects," Panasonic Corporation, granted Oct. 21, 2008, class 257/758.
• Nature: This is the grandparent of '597 (11/000,904). It shares the same priority (JP 2003-404437) and substantially the same disclosure.
• Claim mapping: None under § 102. A reference cannot be § 102 prior art against a patent claiming the same priority date/inventor unless it qualifies under § 102(b)/§ 102(e) on an earlier date with different inventive entity — and here the '597 grant carries an express terminal disclaimer over the family. Its presence in the citation list is a related-art/self-citation, not an anticipation reference.

3.4 US 2002/0145201 A1 — Armbrust et al.

• Full citation: U.S. Patent Application Publication 2002/0145201 A1, Armbrust et al., published October 2002.
• Date: October 2002 — more than one year before Dec. 3, 2003, so it would qualify as § 102(b) art if its disclosure reads on the claims.
• Brief description / claim mapping: Unverified. I did not retrieve the disclosure in this session and will not guess at its teachings.

3.5 JP 2000-331991 (Kokai), Nov. 2000

• Full citation: Japanese Unexamined Patent Publication (Kokai) No. 2000-331991, published November 2000.
• Brief description: This is the conventional Cu dual-damascene multilevel structure that '597 expressly adopts as the background art (Figs. 18A–19C and 20A of '597 reproduce it). It shows a lower interconnect 2 in insulating film 1, SiN/SiO₂/FSG stack, via hole 6, interconnect trench 7, barrier film 8, Cu film 9, via 10, upper interconnect 11, and a SiN cap 12.
• Claim mapping: No § 102. It lacks the two features that define the invention: (i) any dummy via/slit and (ii) dummy via bottom located in the underlying insulating film. It is the natural lead reference for a § 103 combination, and a § 112 written-description/admission issue exists because '597's own Background characterizes it as the starting point.

3.6 CN 1304175, JP 2000-012688, JP 2002-023384, JP 2002-299437

• Full citations / dates: CN 1304175 (Jul. 2001); JP 2000-012688 (Jan. 2000); JP 2002-023384 (Jan. 2002 — note the sibling US 7,632,751 prints JP 2002-033384 in this slot); JP 2002-299437 (Oct. 2002).
• Brief description / claim mapping: Not verified in this session. All pre-date the Dec. 3, 2003 priority date and are therefore § 102-eligible in principle, but I cannot state which claims they would reach. I explicitly decline to guess.

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4. Other prior art relevant to '597 but not in its own citation list

'597 is the subject of an active PTAB challenge in the same family, and the petition record identifies further art beyond the '597 front page. I flag these as leads, not verified citations, because I could not resolve them to patent numbers in this session:

• "Iizuka" (petition exhibit TSMC-1008) — relied on for the teaching that "the opening of the via-hole may have any configuration, such as a square, rectangle or circle," used to render the circular-via dependents obvious in combination with Kunikiyo.
• "Aoyagi" and several further exhibits (TSMC-1005, 1013, 1014, 1016–1019, 1038) — used for dual-damascene Cu processing, circular dummy vias (TSMC-1005 ¶¶[0200], [0209], Figs. 19A, 22A), and via-shape design choices.
• Proceeding: Taiwan Semiconductor Manufacturing Company Ltd. v. Advanced Integrated Circuit Process LLC, IPR2025-01305, directed at US Patent 7,439,623 — i.e., the ancestor of '597. Grounds include anticipation of claim 1 by Kunikiyo and Kunikiyo+Iizuka obviousness for the circular-via claims.

Practical consequence: because '597, '751, '969 and '623 share one specification, Kunikiyo alone is the reference most likely to be asserted under § 102 against '597's structural claims, with Iizuka-type art supplying the shape limitations and Aoyagi-type art supplying the dual-damascene/Cu processing.

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5. Bottom line

1. The most relevant prior art for US 8,334,597 is US 6,717,267 B1 (Kunikiyo) — it discloses dummy interconnects buried in an interlayer insulating film with dummy plugs connecting to the overlying interconnection, which maps onto claim 1's "at least one dummy via connected to the upper interconnect … bottom of the dummy via located in the second insulating film," and it is already the primary § 102 reference in the live IPR against this family.
2. JP 2000-331991 is the closest background reference (it is '597's own admitted conventional structure) but cannot anticipate because it has no dummy via or insulating slit.
3. US 7,439,623 is family, not prior art (terminal disclaimer on file).
4. US 6,919,637, US 2002/0145201, CN 1304175, JP 2000-012688, JP 2002-023384 and JP 2002-299437 are § 102-eligible by date, but I could not verify their disclosures in this session, so I have not assigned them to specific claims. If you want claim-level § 102 charts for those six, the authoritative next step is to pull each document from USPTO PatentCenter / J-PlatPat / CNIPA and read them against '597's issued claims, which I also could not retrieve in full here (the claim set was truncated in my source text; my mapping above is keyed to the claim families recited in the '597 SUMMARY — first interconnection structure, second interconnection structure, third interconnection structure, and the first–fourth methods).

I'll first try to locate the prior-art references for this patent and its family, since the "Prior Art section" wasn't included in the material passed to me.

Let me pull details on the key family-IPR references and check for art specifically addressing dummy vias that extend deeper than the functional via.

Let me confirm the exact structure disclosed in Watanabe and try to retrieve the issued claim text of the '597 patent.

Obviousness Analysis — U.S. Patent No. 8,334,597 B2 under 35 U.S.C. § 103

0. Scope, inputs, and a threshold caveat

Two inputs the task assumes are missing from the record I was given.

1. No "Prior Art section" was supplied in this thread. The material passed to me contained the patent's specification/abstract and the previously generated bibliographic and litigation sections — not a prior-art (IDS/face-of-patent/PTAB-ground) listing. I therefore reconstructed the prior-art universe from (a) the reference list appearing on the face of the family's own printing (US 7,632,751 — the same specification, same inventor, same family: CN 1304175; JP 2000‑012688; JP 2000‑331991; JP 2002‑033384; JP 2002‑299437), and (b) the references actually applied by TSMC against the sibling patents 7,439,623 / 7,632,751 in the PTAB petitions (IPR2025‑01302 exhibit list, petition papers at PTACTS). Where I rely on those, I say so.

2. The issued claims of '597 are still not in my record. This was flagged in the previously generated summary and remains true. The analysis below is therefore claim‑aspect based, keyed to the eight independent aspects recited in the '597 Summary of Invention (three structures, four methods, plus the shared technical idea). Verify the issued claim text (USPTO Patent Public Search / PatentCenter) before using any of this.

I am a technical analyst, not counsel. This is a technical obviousness assessment, not a validity opinion.

Governing law. The '597 application (13/104,484) was filed 2011‑05‑10 and claims priority to JP 2003‑404437 (2003‑12‑03); the pre‑AIA version of §103 applies. Control: Graham v. John Deere, KSR Int'l v. Teleflex, 550 U.S. 398 (2007), and the Federal Circuit's articulation that any rationale grounded in the record — including "design incentives," "market forces," "obvious to try," and the predictable use of prior-art elements according to their established functions — suffices. Prior-art status is assessed under pre-AIA §§102(a)/(b)/(e). Two of my strongest references qualify only under §102(e) (via their U.S. filing dates) — flagged below.

Secondary-relevant fact from the family record. In this family's IPRs, TSMC's declarant (Dr. Reinhold Dauskardt) framed the state of the art as: stress migration/electromigration move metal atoms and vacancies; vacancies aggregate in/under vias forming voids and opens; "dummy vias have been added near active vias to arrest stress-induced vacancy migration and void formation" — well before the '751 patent (petition paper). That framing is the single most damaging piece of record-based evidence for '597's inventive concept, and it is directly transferable to '597, which shares the specification.

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1. Person of ordinary skill in the art (POSITA)

A POSITA at the 2003‑12‑03 priority date would have: a B.S. in EE, Materials Science, or Applied Physics (or equivalent), plus 2–4 years of hands‑on semiconductor back‑end‑of‑line (BEOL) integration experience (Cu dual‑damascene, PVD barrier, electroplated Cu, CMP), or an M.S. with equivalent coursework and 1–2 years; and would be familiar with the stress-migration literature, including E. T. Ogawa et al., "Stress-Induced Voiding Under Vias Connected To Wide Cu Metal Leads," IEEE 40th Annual IRPS (2002), pp. 312–321 — cited in Kamoshima ¶[0004] and squarely on point for '597's FIG. 19B/19C problem (wide Cu lead, narrow via, void under the via).

This definition matters because the '597 specification concedes the entire conventional baseline (FIG. 19B/C) as prior art, including the Cu/FSG dual‑damascene stack, the 0.2 µm lower interconnect, the 0.20 µm via, and the 10 µm upper interconnect. Those values are therefore admitted art and cannot carry novelty.

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2. Prior-art universe and §102 status

Note on the two §102(e) references (Kamoshima, Kurashima, Hasunuma). Their publication dates postdate the '597 priority date; they are available only because their U.S. filing dates precede 2003‑12‑03 (Kamoshima 2003‑09‑09; Kurashima 2003‑08‑14; Hasunuma 2003‑09‑03). This is exactly how TSMC applied Kamoshima against '751 — an established, sourced use. Any post-2013 revival of this family under the AIA would change the calculus (AIA §102(a)(2) "effectively filed" still captures Kamoshima), so the ground is robust either way.

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3. Ground-by-ground obviousness analysis

GROUND 1 — Structure 1 ("dummy via with bottom in the second insulating film")

Primary: Watanabe. Secondary: JP 2000‑331991 (Cu dual damascene + term mapping); Ogawa IRPS 2002 (mechanism/motivation).

Element mapping (using '597's vocabulary):

Motivation to combine (record-grounded):

• Same field, same problem, same solution. Watanabe's stated object is improving stress-migration resistance in a damascene Cu structure — the identical problem '597 "solves." TSMC's own record asserts Watanabe "identified the same problem of stress-related via failures in dual-damascene interconnects … and proposed the same solution later claimed," specifically "citing stress migration leading to via lift-off or connection failure" and "incorporating non-functional dummy vias formed concurrently with the functional structures using the dual damascene process" (petition exhibit).
• Ogawa IRPS 2002 supplies the mechanism ('597's own theory: voids under vias connected to wide Cu leads) as of 2002 — before the priority date. Kamoshima's background cites it.
• The "deeper hole" is not an inventive increment. Where there is no lower interconnect, no etch stop exists; a dummy hole etched concurrently with the via hole necessarily penetrates further, into the film containing the lower interconnect. That is an inherent geometric consequence of the Watanabe structure, not a separate design step. In re … inherency principle; and KSR (predictable result of known elements used per their established function).
• Even if one credited the deeper bottom as a distinct design choice, "deeper hole ⇒ steeper stress gradient ⇒ preferential vacancy drain" is a known technique applied to a known structure ready for improvement (KSR rationale D) — and the '597's own FIG. 3 shows a smooth monotonic malfunction-vs-spacing trend, which is evidence of predictability, not surprise (In re Aller-type optimization; the absence of a sharp, unexpected inflection undercuts any "criticality" argument).

Anticipated rebuttal and answer. Patentee will argue Watanabe's stated rationale is wiring-length reduction and mechanical support, not vacancy capture. Answer: (i) obviousness does not require the reference to articulate the inventor's mechanism — it is enough that the structure is disclosed and its use for the same purpose (stress-migration resistance) is disclosed; (ii) "discovery of the cause of a known defect" is not the patentable contribution; (iii) Kamoshima supplies the vacancy-dispersion rationale for the identical geometry.

Conclusion. Structure 1, and dependent features such as the ≤1 µm spacing and the dummy-interconnect bottom alternative, are obvious over Watanabe (with JP 2000‑331991 for the environment and Ogawa for mechanism), and additionally obvious over Watanabe + Kamoshima.

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GROUND 2 — Structure 2 ("insulating slit in the upper interconnect")

Primary: Kamoshima. Secondary: JP 2000‑331991 (masking/dry-etch sequence); Iizuka (geometry).

Kamoshima alone discloses the heart of the claim:

• Emb. 3 (¶[0082]): "slit 41 is formed so as to interpose the portion connected to via 4a" — i.e., a dielectric slit in the upper interconnect that is in contact with the via-connected portion; this is '597's express Structure‑2 option and the sixth embodiment's "longer side in contact with the portion connected to the via."
• The slit is part of interlayer insulating layer 4 — i.e., a material different from the Cu conductive film, matching '597's "slit is a part of the first insulating film" and its stated barrier function.
• Emb. 6/Fig. 25 places the slit near the branch point of the wide/narrow portions — '597's seventh embodiment.
• Rectangular slit, longer side running along the interconnect length direction (per the family record: "Kamoshima similarly uses a rectangular structure (e.g., insulating slit 41) positioned in such a manner (a longer side extending in a same direction as a longer side of the wider interconnect portion) to suppress migration of vacancies to via 4a").

Motivation. Kamoshima's own object is suppressing microvoid concentration under the via due to stress migration (¶¶[0002], [0088], [0097]–[0098]). A dielectric slit near the via (i) lowers local tensile stress in the Cu near the via and (ii) acts as a diffusion barrier to vacancy flux. JP 2000‑331991 supplies the enabling process ('597 Method 3) — "lithography and dry etching performed twice" to form via hole + trench; leaving part of the FSG in the trench is a mere matter of mask layout, which Kamoshima's process already does.

Numeric-range limitations ('597: slit length ≥2× and ≤4× via diameter; 0.4 µm × 0.2 µm; or ≥2× and ≤10×; 0.8 µm × 0.2 µm; spacing ≤1 µm): pure optimization of a known geometry for its known purpose. KSR ("when a work is available in one field … design incentives … can prompt variations"); In re Aller/In re Boesch (optimizing a result-effective variable). The '597 range ends fall exactly at 2× and 4×, i.e., whole-number multiples of the via diameter with no disclosed criticality or data showing an unexpected boundary.

Conclusion. The insulating-slit structure and its dependent geometry are obvious over Kamoshima alone, and certainly over Kamoshima + JP 2000‑331991 (process) + Iizuka (shape).

Mandatory caution: US 2006/0180934 A1 is nearly a verbatim textual match to this claim aspect ("dummy dielectric layer … adjacent to the vertical connection to prevent mobile metal atoms and/or defects generated through stress migration from moving into the vertical connection"). It publishes in 2006 and is not §102 prior art to a 2003‑12‑03 priority date. Do not plead it as prior art. It is useful only to show that the concept was a mainstream, predictable engineering approach — which is corroborative of obviousness but not itself a ground.

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GROUND 3 — Structure 3 ("dummy portion at the wide/narrow branch point")

Primary: Kamoshima (Emb. 5/6). Secondary: Watanabe (dual-damascene formation, ≤1 µm spacing).

Kamoshima ¶[0095]: interconnection layer 3 has a large line width portion 3a and a small line width portion 3b; via 4a is connected to the narrow portion 3b; dummy via 4c is positioned on the narrow portion 3b between connection portion R and via 4a; and Fig. 24 places 4c on the wide portion 3a adjacent to R. ¶[0098]: "A large number of microvoids in interconnection layer with a large line width 3a tend to concentrate in the area under dummy via 4c before reaching the area under via 4a" — the identical rationale '597 recites ("vacancies which are to enter the narrow interconnect from the wide interconnect … are effectively captured in the dummy portions").

This maps 1:1 onto:

• "upper interconnect divided into a relatively wide first portion and a relatively narrow second portion" → 3a/3b;
• "via connected to the second interconnect portion" → 4a on 3b;
• "at least one dummy portion connected to the upper interconnect" → 4c;
• "distance between dummy portion and branch point smaller than distance between dummy portion and the far edge of the narrow portion" → 4c between R and 4a (so necessarily closer to R than to the far end of 3b);
• "second interconnect portion ≤0.20 µm" → the reference's narrow-portion/design-rule geometry, and the '597's own admitted 0.2 µm value;
• "distance ≤1 µm" → Watanabe's <1 µm teaching.

Motivation. The wide lead is the vacancy reservoir; the narrow leg feeding the functional via is the failure point. Kamoshima explicitly states the "bottleneck/capture" mechanism. Watanabe supplies the reason to place the dummy structure by dual damascene concurrently and to keep it <1 µm from the working via. Both are analogous art (same field: interconnect structures; reasonably pertinent to interconnect reliability). KSR rationales A/C/D all apply; the combination is a predictable use of known elements.

Conclusion. Structure 3 (including its dependent shapes and the ≤1 µm and ≤0.20 µm values) is obvious over Kamoshima, and further over Kamoshima + Watanabe.

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GROUND 4 — Shape/size/material-dependent features (across all three structures)

• Rectangular dummy via / different planar shape from the circular via: Iizuka (via openings "square, rectangle or circle") + Fukazawa (column-shaped dummy contact) + Kamoshima's rectangular slit 41 geometry. Changing a via's plan-view shape is a known design alternative with predictable results (later: US 2005/0142840 notes a non‑connecting dummy via's opening can even be shrunk below the design rule).
• Dummy via diameter smaller than the via's: geometrically dictated once the dummy via must fit beside the working via within the ≤1 µm spacing; and Kamoshima/Watanabe both scale dummy features by layout. Result-effective variable, routine optimization.
• Dummy interconnect narrower than the upper interconnect: Hasunuma (US 2004/0113238, §102(e)) + Kurashima (functional and dummy wires, same width/layer) — expressly applied in the '751 IPV ground 7.
• "Longer side of the rectangular dummy portion parallel to the interconnect width": disclosed/rendered obvious by Kamoshima's slit-41 orientation teaching (per the family record's §398 analysis).
• Materials (barrier film, Cu, SiN/SiO₂/FSG): admitted in JP 2000‑331991 and the '597 specification itself; not inventive.

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GROUND 5 — The four method aspects (Methods 1–4)

Each method is the fabrication counterpart of a structure, and each maps onto a known dual-damascene sequence:

Motivation (methods). All four methods are the same dual-damascene toolset (deposit ILD → pattern via hole and trench → deposit barrier/Cu → CMP) already disclosed by JP 2000‑331991 and Watanabe, with the dummy feature added by simply editing the mask layout. This is the paradigm KSR case: "a known technique … used to improve a similar device in the same way," with a reasonable expectation of success and no teaching away. Nothing in the methods requires a new material, a new tool, or an unpredictable process window.

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4. Cross-cutting motivation-to-combine, stated in the form the Board expects

For each ground above, at least three of the following rationales are supported by record evidence:

• (A) Combining known prior-art elements to yield predictable results. Watanabe's and Kamoshima's dummy features are structurally identical to '597's; the result (fewer voids at the working via) is predictable and corroborated by the '597's own smooth FIG. 3 and FIG. 5 curves.
• (B) Simple substitution of one known element for another. Dummy via ↔ insulating slit (both disclosed in Kamoshima); dummy-hole bottom on a lower interconnect ↔ on the underlying insulating film (both disclosed in Watanabe).
• (C) Use of a known technique to improve a similar device in the same way. Dual-damascene dummy-via insertion, already used to improve stress-migration resistance, applied to the wide-lead/narrow-via geometry the art (Ogawa 2002; Kamoshima ¶[0007]) identified as failure-prone.
• (D) Applying a known technique to a known device ready for improvement. The wide-lead-under-via structure is expressly identified in the literature as ripe for dummy-feature placement.
• (E) "Obvious to try." A finite, small number of identified, predictable solutions (place a dummy via, or a slit, at the via-connected portion or at the branch point), with a reasonable expectation of success — KSR.

Analogy and reasonable expectation of success. All references are in the same field (Cu damascene interconnect structures for semiconductor devices) and are reasonably pertinent to the very problem '597 states (interconnect reliability / stress-migration voiding). The mechanisms are physically compatible; no reference teaches away from dummy features; Watanabe affirmatively teaches their benefit.

Secondary considerations (Graham factor 4). No evidence of nexus, unexpected results, licensing‑because‑of‑the‑claimed‑feature, or commercial success attributable to the claimed features appears in the record I hold. The family's litigation posture is consistent with portfolio enforcement against sibling patents rather than reliance on '597 (per the previously generated litigation section: the asserted patents are 7,439,623, 7,632,751, 8,329,572, 8,884,373 — not 8,334,597). The '597 expired (anticipated 2024‑12‑02), which limits both the practical exposure and any objective-evidence story.

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5. Where the analysis is weakest / most contestable

1. The "bottom of the dummy via is located in the second insulating film" limitation (Structure 1 / Method 1). This is the one limitation Kamoshima does not disclose (its dummy vias sit above the interconnect). It depends entirely on Watanabe's "non‑forming region" disclosure plus the inherency/over‑etch argument. Expect a claim-construction fight over whether Watanabe's dummy hole bottom is literally "in" the film containing the first wiring, or merely at its top surface. Mitigation: plead Watanabe's dummy-wiring alternative (dummy connection hole "formed so as to reach the dummy wiring") as an express, non-inherent disclosure of the bottom-in-the-second-film variant.
2. Kamoshima's §102(e) status (filing 2003‑09‑09 vs. priority 2003‑12‑03) must be proved with the U.S. filing receipt/continuity, since its publication is after the critical date. Same for Kurashima and Hasunuma.
3. Mechanism mismatch (Watanabe: wiring-length/mechanical; '597: vacancy capture). Rebutted above, but an examiner or PTAB panel could weight it.
4. Claim text unknown. If the issued '597 claims include a limitation not present in my reconstruct (e.g., a specific relationship between dummy-hole depth and via-hole depth, or a specific plan-view symmetry), a supplemental ground may be needed.

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6. Bottom line

Under pre-AIA §103, all eight aspects — Structures 1–3 and Methods 1–4 — are, on the record I can assemble, obvious, on these primary combinations:

This is consistent with — and largely mirrors — the grounds TSMC assembled against the sibling patents '623 and '751 (Watanabe as primary; Kamoshima, Iizuka, Fukazawa, Kurashima, Hasunuma as secondaries). If '597 were ever asserted, the same reference set would be the natural starting point, with the added task of mapping the "bottom-of-dummy-via-in-the-second-insulating-film" limitation onto Watanabe's non‑forming-region dummy connection hole.

Verification steps before relying on this: (i) pull the issued claims of 8,334,597 from PatentCenter/Patent Public Search and re-map; (ii) confirm §102(e) filing dates for Kamoshima, Kurashima, Hasunuma from their file wrappers; (iii) obtain the full text/figures of Watanabe US 2003/0116852 (esp. Figs. 12A–12N and the ¶[0171]–[0181] generic embodiment) and Kamoshima US 2004/0173905 ¶¶[0080]–[0105], Figs. 15–27, to lock the element-by-element citations; (iv) treat US 2006/0180934 and DE 103 42 996 as background only (post‑priority publications).