US 7632751

Here is a concise summary of US Patent 7632751:

• Title: Semiconductor device having via connecting between interconnects
• Current Assignee: Advanced Integrated Circuit Process LLC
• Inventor: Takeshi Harada
• Filing Date: September 30, 2008
• Issue Date: December 15, 2009
• Abstract: A first insulating film is provided between a lower interconnect and an upper interconnect. The lower interconnect and the upper interconnect are connected to each other by way of a via formed in the first insulating film. A dummy via or an insulating slit is formed on/in the upper interconnect near the via.

Plain-Language Overview of Independent Claims (based on the "Definitions" section of the patent):

1. First Interconnection Structure: This claim describes a semiconductor device with a lower interconnect and an upper interconnect, connected by a via through a first insulating film. The lower interconnect is in a second insulating film beneath the first. A key feature is the inclusion of at least one "dummy via" connected to the upper interconnect, where the bottom of this dummy via is situated within the second insulating film. This dummy via does not form part of a closed circuit during actual device use.
2. Second Interconnection Structure: This claim focuses on an interconnection structure that includes a lower interconnect, an upper interconnect, and a first insulating film between them, with a via connecting the two interconnects. The distinguishing feature here is the presence of at least one "insulating slit" formed within the upper interconnect.
3. Third Interconnection Structure: This claim describes a structure where the upper interconnect is split into a wider first portion and a narrower second portion, with the via connecting to the narrower second portion. The invention includes at least one "dummy portion" connected to the upper interconnect, strategically placed such that its distance to the branching point of the wide and narrow interconnects is less than its distance to the opposite edge of the narrow interconnect portion.
4. First Method for Forming an Interconnection Structure: This method involves depositing a first insulating film over a lower interconnect (which is itself in a second insulating film). It includes forming a via hole to the lower interconnect, at least one dummy hole nearby, and an upper interconnect trench connecting to both holes. A conductive material is then deposited to form the upper interconnect, the functional via, and a dummy via connected to the upper interconnect but insulated from the lower one, with the dummy hole's bottom in the second insulating film.
5. Second Method for Forming an Interconnection Structure: This method includes depositing a first insulating film over a lower interconnect, then forming a via hole and an upper interconnect trench. A conductive material fills these to create the upper interconnect and the functional via. Subsequently, a second insulating film is deposited over the upper interconnect, and a dummy hole is formed in this second film, reaching the upper interconnect near the functional via. A conductive material then fills this dummy hole to form a dummy via.
6. Third Method for Forming an Interconnection Structure: This method describes depositing a first insulating film on a lower interconnect, then forming a via hole and an upper interconnect trench. A conductive material fills these to form the upper interconnect and functional via. A distinct aspect of this method is that during the formation of the via hole and upper interconnect trench, a portion of the first insulating film is intentionally left within the upper interconnect trench near the via hole, thereby creating an insulating slit.
7. Fourth Method for Forming an Interconnection Structure: This method involves depositing a first insulating film on a lower interconnect, followed by forming a via hole, an upper interconnect trench (divided into wide and narrow sections), and a recess near the branch point of these sections. A conductive material is then deposited to fill these structures, creating the upper interconnect (with its wide and narrow portions), the functional via, and a dummy portion connected to the upper interconnect but insulated from the lower one.

CAFC 2026 Dockets:
As of April 26, 2026, a search of CAFC 2026 dockets for US7632751 did not return any cases directly involving this specific patent number.