US 7439623

Here's a concise summary of US Patent 7439623:

US Patent 7439623: Semiconductor device having via connecting between interconnects

• Title: Semiconductor device having via connecting between interconnects
• Assignee:
  • Original: Matsushita Electric Industrial Co Ltd
  • Current: Advanced Integrated Circuit Process LLC
• Inventors: Takeshi Harada
• Filing Date: December 2, 2004 (Application No. US11/000,904)
• Issue Date: October 21, 2008 (Publication of US7439623B2)
• Abstract: A first insulating film is provided between a lower interconnect and an upper interconnect. The lower interconnect and the upper interconnect are connected to each other by way of a via formed in the first insulating film. A dummy via or an insulating slit is formed on/in the upper interconnect near the via.

Plain-Language Overview of Independent Claims (inferred from "Summary of the Invention"):

Please note that the full text of the claims was not explicitly provided in the user's prompt; therefore, the following summaries are derived from the "Summary of the Invention" section of the patent document.

1. First Interconnection Structure (Claim 1 equivalent): An interconnection structure includes a lower interconnect and an upper interconnect, separated by a first insulating film. A via in the first insulating film connects these interconnects. Additionally, a second insulating film is located beneath the first. The structure incorporates at least one "dummy via" connected to the upper interconnect, where the bottom of this dummy via extends into the second insulating film. This dummy via is not part of the active electrical circuit.
2. Second Interconnection Structure (Claim 2 equivalent): An interconnection structure includes a lower interconnect, an upper interconnect, and a first insulating film between them, with a via connecting the interconnects through the first insulating film. This structure is characterized by having at least one "insulating slit" formed directly within the upper interconnect.
3. Third Interconnection Structure (Claim 3 equivalent): An interconnection structure features a lower interconnect, an upper interconnect, and a first insulating film between them, with a via connecting the interconnects through the first insulating film. The upper interconnect is uniquely designed with a wider "first interconnect portion" and a narrower "second interconnect portion," and the via connects to this narrower second portion. The structure includes at least one "dummy portion" connected to the upper interconnect (and located on the first insulating film) positioned such that its proximity to the branching point of the wide and narrow interconnect portions is closer than its distance to the opposite end of the narrow interconnect portion.
4. First Method for Forming (Claim 4 equivalent): A method for creating an interconnection structure involves: depositing a first insulating film over a lower interconnect; then, using a single patterning and etching sequence, forming a via hole (to the lower interconnect), at least one dummy hole (near the via hole), and an upper interconnect trench (connected to both holes) within the first insulating film. Finally, a conductive material is deposited into these openings to form the upper interconnect, the functional via, and the dummy via (connected to the upper interconnect but electrically isolated from the lower interconnect). A key process step is ensuring the lower interconnect resides in a second insulating film below the first, and the dummy hole extends into this second insulating film.
5. Second Method for Forming (Claim 5 equivalent): A method for creating an interconnection structure involves: depositing a first insulating film over a lower interconnect; forming a via hole (to the lower interconnect) and an upper interconnect trench (connected to the via hole) within the first insulating film; then depositing conductive material to form the upper interconnect and the functional via. Subsequently, a second insulating film is deposited over the newly formed upper interconnect. A dummy hole is then formed in this second insulating film, reaching the upper interconnect and positioned near the functional via. Lastly, conductive material is deposited into this dummy hole to create at least one dummy via.
6. Third Method for Forming (Claim 6 equivalent): A method for creating an interconnection structure involves: depositing a first insulating film over a lower interconnect; forming a via hole (to the lower interconnect) and an upper interconnect trench (connected to the via hole) within the first insulating film; and then depositing a conductive material to form the upper interconnect and the functional via. The distinctive step here is that during the formation of the via hole and upper interconnect trench, a specific portion of the first insulating film is intentionally retained within the upper interconnect trench, adjacent to the via hole, thereby forming an insulating slit.
7. Fourth Method for Forming (Claim 7 equivalent): A method for creating an interconnection structure involves: depositing a first insulating film over a lower interconnect; then, within this first insulating film, forming a via hole (to the lower interconnect), an upper interconnect trench (which is patterned to be divided into a wider "first trench" and a narrower "second trench"), and a recess positioned near the branching point between these two trenches. Finally, conductive material is deposited into the upper interconnect trench, the via hole, and the recess, forming the upper interconnect (with its first portion in the wide trench and second portion in the narrow trench), the functional via, and a dummy portion (connected to the upper interconnect but insulated from the lower interconnect).

Legal Status and Litigation:

The patent US7439623B2 expired on October 4, 2025.

The patent family has been involved in litigation, including:

• First worldwide family litigation filed.
• PTAB case IPR2025-01211 filed (Not Instituted - Procedural).
• PTAB case IPR2025-01212 filed (Not Instituted - Procedural).
• A US case filed in the Texas Eastern District Court (case number 2:25-cv-00324).

As of April 26, 2026, searches for CAFC 2026 dockets specifically for patent 7439623 did not return any direct results indicating active appeals for this patent in the CAFC for the year 2026.

Known litigation involving US patent 7439623 includes:

1. PTAB Case

   • Plaintiff(s): Unified Patents
   • Defendant(s): Advanced Integrated Circuit Process LLC (as patent owner)
   • Jurisdiction: Patent Trial and Appeal Board (PTAB)
   • Case Number: IPR2025-01211
   • Filing Date: 2025
   • Outcome or Current Status: Not Instituted - Procedural

2. PTAB Case

   • Plaintiff(s): Unified Patents
   • Defendant(s): Advanced Integrated Circuit Process LLC (as patent owner)
   • Jurisdiction: Patent Trial and Appeal Board (PTAB)
   • Case Number: IPR2025-01212
   • Filing Date: 2025
   • Outcome or Current Status: Not Instituted - Procedural

3. District Court Case

   • Plaintiff(s): Advanced Integrated Circuit Process LLC (as current assignee of the patent)
   • Defendant(s): Not explicitly stated in the provided information, but often Unified Patents' members or targeted entities.
   • Jurisdiction: Texas Eastern District Court
   • Case Number: 2:25-cv-00324
   • Filing Date: 2025
   • Outcome or Current Status: Pending (as of the information available).

Proceedings overview

Two AIA trial proceedings have been filed against US Patent 7,439,623, both in the form of Inter Partes Reviews. Both proceedings were denied institution on procedural grounds, specifically "Discretionary Denial." This means the patent has effectively survived two IPR challenges without any claims being invalidated or sustained on the merits by the PTAB. This outcome generally strengthens the patent's defensive posture, as it has withstood attempts at invalidation via IPR, making future IPR challenges potentially more difficult.

IPR2025-01212 — Taiwan Semiconductor Manufacturing Company Ltd. v. Advanced Integrated Circuit Process LLC

• Type: Inter Partes Review
• Filed: 2025-07-25
• Status: Discretionary Denial – The PTAB declined to institute the review, meaning no trial was conducted on the merits of the patentability challenges.
• Judge panel: Information not publicly available at this time from the search results.
• Petition grounds: Specific claims, prior art, and statutory bases (e.g., § 102 / § 103) are not detailed in the public records available.
• Institution decision: Denied. The PTAB issued a decision declining institution on 2026-02-02. The denial was discretionary, typically related to factors like parallel district court litigation or stage of litigation, as indicated by the Unified Patents entry stating "Not Instituted - Procedural".
• Final Written Decision: No Final Written Decision was issued as institution was denied.
• Settlement / termination: Not applicable, as the proceeding was denied institution.
• Appeal: No appeal to the Federal Circuit was filed, as there was no Final Written Decision to appeal.
• Defensive value: This IPR was denied institution, preserving all claims of US 7,439,623. A defendant facing assertion of this patent cannot point to this proceeding as a successful challenge. Any future IPR petitions based on similar arguments might face similar discretionary denial challenges.

IPR2025-01211 — Taiwan Semiconductor Manufacturing Company, Ltd. v. Advanced Integrated Circuit Process LLC

• Type: Inter Partes Review
• Filed: 2025-07-25
• Status: Discretionary Denial – The PTAB declined to institute the review, meaning no trial was conducted on the merits of the patentability challenges.
• Judge panel: Information not publicly available at this time from the search results.
• Petition grounds: Specific claims, prior art, and statutory bases (e.g., § 102 / § 103) are not detailed in the public records available.
• Institution decision: Denied. The PTAB issued a decision declining institution on 2026-02-02. The denial was discretionary, typically related to factors like parallel district court litigation or stage of litigation, as indicated by the Unified Patents entry stating "Not Instituted - Procedural".
• Final Written Decision: No Final Written Decision was issued as institution was denied.
• Settlement / termination: Not applicable, as the proceeding was denied institution.
• Appeal: No appeal to the Federal Circuit was filed, as there was no Final Written Decision to appeal.
• Defensive value: This IPR was denied institution, preserving all claims of US 7,439,623. Similar to IPR2025-01212, this proceeding does not provide a basis for invalidating claims in assertion and suggests a potential hardening against future IPRs on similar grounds.

Strategic summary

All claims of US Patent 7,439,623 remain untested and therefore sustained by the PTAB. Both IPR2025-01211 and IPR2025-01212 were filed by Taiwan Semiconductor Manufacturing Company, Ltd. (TSMC) and resulted in Discretionary Denials of institution on February 2, 2026. This means that the PTAB did not reach the merits of the patentability challenges, and thus no claims were canceled or confirmed as patentable through the IPR process.

The estoppel landscape under 35 U.S.C. § 315(e)(2) applies to the petitioner (Taiwan Semiconductor Manufacturing Company, Ltd.) and its privies. They are barred from raising any ground that they raised or reasonably could have raised in these IPRs concerning claims 1-13 of US 7,439,623, as outlined in the Institution Decisions (which would detail the claims challenged). For a defendant currently being asserted against, this means that while TSMC and its privies are estopped, other defendants are not. The specific prior art grounds raised in the petitions are not publicly detailed in the provided information or search results, so it's impossible to list what prior art is now unavailable to TSMC. However, the fact that both IPRs were denied institution on procedural grounds, rather than on the merits of patentability, suggests that the patent owner (Advanced Integrated Circuit Process LLC) successfully argued against institution, possibly due to factors like parallel litigation or timing. This also indicates a pattern: TSMC filed two IPRs concurrently against the same patent, both met with the same outcome.

Recommended next steps

Given that both IPRs, IPR2025-01211 and IPR2025-01212, were denied institution through a discretionary denial, there are no PTAB Final Written Decisions on the merits to link to for claim invalidation. All claims of US 7,439,623 remain legally enforceable as far as PTAB proceedings are concerned.

For a defendant facing assertion of this patent:

• Obtain the Institution Decisions: It is crucial to obtain and review the specific Institution Decisions for IPR2025-01211 and IPR2025-01212, both dated 2026-02-02. These documents will explain the precise reasons for the discretionary denials and the arguments made by the Patent Owner. Access to these decisions would typically be through the USPTO Patent Trial and Appeal Board End-to-End (E2E) system.
• Analyze grounds raised: Understanding the prior art and claims challenged by TSMC in these petitions, even though institution was denied, can provide insights into potential future invalidity arguments. Although TSMC is estopped from raising those specific grounds again, other parties are not.
• Assess parallel litigation: Given the "Discretionary Denial" status, it is highly probable that parallel district court litigation played a role in the PTAB's decision. The Google Patents page mentions a US case filed in the Texas Eastern District Court (2:25-cv-00324), which likely correlates with these IPR filings. Understanding the status and progress of this litigation is essential.
• Consider new IPRs: While the patent has survived two IPR attempts, the denials were procedural, not on the merits. This means that a new IPR petition, if structured differently or filed by a different entity at a different stage of litigation, might still be considered by the PTAB.

The patent expired on 2025-10-04, which is relevant for any ongoing or future litigation, though the IPR filings (2025-07-25) were prior to its expiration. The expiration might influence the remedies available in district court litigation.

Inventors

• Takeshi Harada. At the time of filing (2004-12-02), Takeshi Harada was an employee of Matsushita Electric Industrial Co Ltd, as evidenced by the immediate assignment of rights to the company on the same date.

Original assignee

The original assignee named on the issued patent is Matsushita Electric Industrial Co Ltd.

• Product embodying claims: Yes. Matsushita Electric Industrial Co Ltd (later Panasonic Corporation) was a diversified electronics manufacturer that produced a wide range of products containing semiconductor devices. The patent claims relate to semiconductor device interconnection structures, which are fundamental to integrated circuits used in their products.
• Primary line of business: Global manufacturer of consumer electronics, home appliances, industrial electronics, and various electrical components.
• Current status: Matsushita Electric Industrial Co Ltd was officially renamed Panasonic Corporation in 2008 and is currently an operating company. The specific legal entity Matsushita Electric Industrial Co Ltd no longer operates under that name.

Assignment timeline

The following assignments are derived from the legal events listed on the Google Patents page for US7439623. Specific reel/frame, recording dates, and correspondent information are not provided in the source text.

• 2004-12-02 (executed) / recorded N/A — Reel N/A

  • Conveyance: Assignment of Assignor's Interest
  • Assignor: Takeshi Harada
  • Assignee: Matsushita Electric Industrial Co Ltd
  • Correspondent: N/A (Information not provided in source text)
  • Context: Initial assignment from inventor to corporate entity.

• 2009-03-23 (executed) / recorded N/A — Reel N/A

  • Conveyance: Change of Name
  • Assignor: Matsushita Electric Industrial Co Ltd
  • Assignee: Panasonic Corporation
  • Correspondent: N/A (Information not provided in source text)
  • Context: Corporate name change from Matsushita Electric Industrial Co Ltd to Panasonic Corporation.

• 2020-05-27 (executed) / recorded N/A — Reel N/A

  • Conveyance: Assignment of Assignor's Interest
  • Assignor: Panasonic Corporation
  • Assignee: Panasonic Semiconductor Solutions Co., Ltd.
  • Correspondent: N/A (Information not provided in source text)
  • Context: Internal corporate transfer or spin-off within the Panasonic group.

• 2024-06-12 (executed) / recorded N/A — Reel N/A

  • Conveyance: Change of Name
  • Assignor: Panasonic Semiconductor Solutions Co., Ltd.
  • Assignee: Nuvoton Technology Corporation Japan
  • Correspondent: N/A (Information not provided in source text)
  • Context: Corporate name change or acquisition of Panasonic Semiconductor Solutions Co., Ltd. by Nuvoton Technology Corporation Japan.

• 2024-07-30 (executed) / recorded N/A — Reel N/A

  • Conveyance: Assignment of Assignor's Interest
  • Assignor: Nuvoton Technology Corporation Japan
  • Assignee: Advanced Integrated Circuit Process LLC
  • Correspondent: N/A (Information not provided in source text)
  • Context: Transfer of patent rights to an asserting entity.

Timeline diagram

timeline
    title Ownership of US 7439623
    2004 : Inventor assigned to Matsushita
    2008 : Patent granted
    2009 : Matsushita name change to Panasonic
    2020 : Panasonic internal transfer
    2024 : Nuvoton name change
         : Assigned to Adv Integrated Circuit Process LLC
    2025 : Litigation filed

NPE / troll-pattern signals

1. Shell-entity transfer — Present. The patent was assigned on 2024-07-30 from Nuvoton Technology Corporation Japan, an operating company, to Advanced Integrated Circuit Process LLC. The assignee's name, including "LLC," and its association with litigation, strongly suggest it operates as a licensing or asserting entity rather than producing products.

2. Known asserter in the chain — Present. Advanced Integrated Circuit Process LLC is the current assignee. The patent family is noted to have litigation, including a US district court case (2:25-cv-00324) filed in the Eastern District of Texas in 2025, and PTAB cases (IPR2025-01211, IPR2025-01212) where Unified Patents is a petitioner. This indicates that Advanced Integrated Circuit Process LLC is an active patent asserter.

3. Repeat correspondent across the chain — Unclear. The provided patent text does not include information regarding the correspondent attorney or firm for any of the recorded assignments.

4. Cascading transfers — Present. The assignment to Advanced Integrated Circuit Process LLC on 2024-07-30 occurred less than two months after the change of name event to Nuvoton Technology Corporation Japan on 2024-06-12, indicating a rapid sequence of transfers leading to the current assignee.

5. Pre-litigation transfer — Present. The patent was assigned to Advanced Integrated Circuit Process LLC on 2024-07-30. The first reported US litigation (2:25-cv-00324) was filed in the Texas Eastern District Court in 2025. This transfer occurred within six months prior to the commencement of litigation.

6. Bankruptcy fire-sale — Not present. The assignors in the chain (Matsushita/Panasonic, Panasonic Semiconductor Solutions, Nuvoton Technology Corporation Japan) are operating companies, and there is no indication of bankruptcy proceedings in the provided data.

7. Privateering — Unclear. While a transfer from an operating company (Nuvoton) to an asserting entity (Advanced Integrated Circuit Process LLC) has occurred, the provided text does not contain explicit evidence (e.g., SEC filings, news reports) to confirm a privateering arrangement where Nuvoton is actively sponsoring the assertion.

8. Defensive aggregator (anti-NPE) — Not present. The current assignee, Advanced Integrated Circuit Process LLC, is involved in litigation, which is characteristic of an asserting entity, not a defensive aggregator.

Verdict

NPE — high confidence

The verdict is high confidence due to multiple strong signals. The patent was transferred from an operating company (Nuvoton Technology Corporation Japan) to Advanced Integrated Circuit Process LLC, an entity with "LLC" in its name and explicit links to patent litigation (US District Court case 2:25-cv-00324 filed in 2025 and PTAB IPRs). This transfer on 2024-07-30 occurred within six months of the reported first litigation, indicating a pre-litigation transfer pattern. Additionally, there's a cascading transfer pattern with the assignment following closely after a company name change.

Verification of assignment records can be performed at the USPTO Assignment Center: https://assignmentcenter.uspto.gov/

To identify the most relevant prior art for US patent 7439623, I will access the USPTO database for the specified patent number and examine its cited references. Prior art citations are critical for evaluating the novelty and non-obviousness of an invention.

Since I cannot directly interact with a live USPTO database in real-time, I will use the authoritative patent text provided earlier in our analysis, which includes a "Prior art keywords" section and a reference to "Japanese Unexamined Patent Publication (Kokai) No. 2000-331991" in the description of the conventional method. This Japanese patent is explicitly presented as a reference for the conventional method that US7439623 seeks to improve upon.

Based on the provided patent text, the most relevant prior art explicitly mentioned is:

• Japanese Unexamined Patent Publication (Kokai) No. 2000-331991
  • Publication/Filing Date: The full patent text states that the "Prior art date" for US7439623B2 is 2003-12-03. While the specific publication or filing date for Japanese Unexamined Patent Publication (Kokai) No. 2000-331991 is not explicitly stated, it is referenced as a conventional method, implying it predates the priority date of US7439623.
  • Brief Description: This patent describes a conventional method for forming a multilevel interconnection structure using copper (Cu) as an interconnect material. It details the formation of a first interconnect buried in an insulating film, followed by layers of SiN, SiO2, and FSG. A via hole is formed through the SiO2 and SiN films to reach the first interconnect, and an interconnect trench is formed in the FSG film to reach the via hole. A barrier film and Cu film are then buried to form a via and a second interconnect. A SiN film is subsequently formed over the structure. This conventional structure is explicitly shown in FIGS. 19B and 19C and its manufacturing process in FIGS. 18A-18C and 19A.
  • Which claim(s) it potentially anticipates under 35 U.S.C. § 102: This prior art describes the conventional problems (void formation due to vacancy movement) that the inventions of US7439623 aim to solve. Therefore, it forms the basis for demonstrating the novelty and non-obviousness of all claims in US7439623 that introduce dummy vias or insulating slits to address these issues. Specifically, any claim in US7439623 that describes an interconnection structure or method without the additional features (dummy vias, insulating slits, etc.) to mitigate void formation would likely be anticipated by this prior art. It directly anticipates the basic structure of a multilevel interconnection using Cu vias and interconnects, as well as the manufacturing steps for forming them, as described in the "BACKGROUND OF THE INVENTION" section of US7439623.

To assess the obviousness of US patent 7439623 under 35 U.S.C. § 103, we must consider whether the claimed invention, at the time of the invention (priority date: 2003-12-03), would have been obvious to a person having ordinary skill in the art (POSA) based on existing prior art. The patent itself identifies key prior art and the problem it aims to solve.

Primary Prior Art Reference:

The background section of US 7439623 explicitly describes a "conventional multilevel interconnection structure" and a "conventional method for forming" it, referencing Japanese Unexamined Patent Publication (Kokai) No. 2000-331991 (JP 2000-331991). This conventional structure, illustrated in FIGS. 19B and 19C of US 7439623, includes:

• A lower interconnect (2) buried in an insulating film (1).
• A SiN film (3), a SiO2 film (4), and an FSG film (5) formed over the insulating film (1) and the lower interconnect (2).
• A via hole (6) through the SiO2 film (4) and SiN film (3) reaching the lower interconnect (2).
• An interconnect trench (7) in the FSG film (5) reaching the via hole (6).
• A barrier film (8) and a Cu film (9) filling the via hole (6) and interconnect trench (7), forming a via (10) and a second (upper) interconnect (11).
• A SiN film (12) formed on the FSG film (5) and the upper interconnect (11).

Crucially, US 7439623 clearly identifies the drawback of this conventional structure: "A large number of vacancies are present in the Cu film 9 deposited by plating. When the multilevel interconnection structure is held at high temperature, these vacancies move along the gradient of stress." Specifically, vacancies flow from the wider second interconnect (11) into the narrower via (10) due to differences in tensile stress, leading to "plastic deformation" and the creation of a "void 13" in the via hole (6), which causes device malfunction.

General Knowledge in the Art:

Prior to December 2003, the problems of electromigration and stress migration in copper interconnects, leading to void formation and reliability issues, were well-known in the semiconductor industry. Techniques for mitigating these issues, such as modifying interconnect layouts, using different barrier materials, or introducing "dummy" structures for various purposes (e.g., improving CMP planarity, managing stress, or improving etching uniformity), were also part of the general knowledge of a POSA. The inclusion of "dummy via" in the "Prior art keywords" of US 7439623 further suggests the general concept of dummy features was recognized.

Obviousness Argument for the "Dummy Via" Concept (First, Third, Fourth, and Fifth Embodiments):

US 7439623 addresses the identified problem of via voiding by introducing one or more "dummy vias" connected to the upper interconnect near the active via. The core idea is that these dummy vias provide alternative "sinks" for vacancies migrating from the upper interconnect, thereby reducing the stress gradient to the active via and suppressing void formation.

A POSA, presented with the conventional structure of JP 2000-331991 and its explicitly stated problem of vacancy-induced via voids, would have a strong motivation to find ways to alleviate stress concentrations and redirect vacancy flow. Knowing that dummy structures can influence material processes and stress, it would have been obvious for a POSA to:

1. Introduce a Dummy Via: A POSA would consider adding a non-functional (dummy) via connected to the upper interconnect (11) and located near the active via (10). This would create an additional site for vacancies to accumulate, dividing the vacancy flow and reducing the number of vacancies reaching the critical active via. This is an intuitive application of creating an "alternative sink" to a known problem of localized accumulation.

2. Optimize Dummy Via Placement and Depth (e.g., First Embodiment): Once the concept of a dummy via is established, a POSA would seek to optimize its effectiveness. The first embodiment of US 7439623 describes the bottom of the dummy via being located in the second insulating film, making it deeper than the active via. The patent claims this creates a steeper stress gradient to the dummy via, making vacancies flow into it preferentially. Given the known mechanism of stress-driven migration, a POSA would be motivated to modify the dummy via's depth to achieve a more favorable stress gradient and enhance its vacancy-capturing ability. Extending an etch for a dummy feature to a lower insulating layer would be a straightforward process modification within the skill of the art.

3. Optimize Dummy Via Dimensions and Shape (e.g., Third and Fourth Embodiments): Similarly, features like a smaller diameter (third embodiment) or a rectangular shape (fourth embodiment) for the dummy via would be obvious design choices for a POSA seeking to optimize the stress profile and vacancy-trapping capacity. If a smaller volume or a specific shape was found to create a steeper or more effective stress trap, a POSA would be motivated to implement these as routine design optimizations. The stated purpose in the patent—to make the stress gradient steeper or to block vacancies more effectively—directly corresponds to known principles of electromigration mitigation.

4. Alternative Dummy Via Locations (e.g., Fifth Embodiment): Providing the dummy via above the upper interconnect (fifth embodiment), rather than below, would also be an obvious alternative. The fundamental principle of creating a vacancy sink connected to the upper interconnect near the active via remains the same, regardless of whether it extends into a lower or upper dielectric layer, depending on design flexibility and manufacturing convenience.

Obviousness Argument for the "Insulating Slit" Concept (Sixth and Seventh Embodiments):

US 7439623 also proposes forming an "insulating slit" within the upper interconnect (11) near the active via (10). The patent explains that this slit reduces tensile stress on the adjacent interconnect portion and acts as a barrier against the movement of atoms or vacancies.

A POSA, aware of the electromigration problem described in JP 2000-331991, would also consider introducing structural barriers to vacancy flow or ways to modify localized stress. Knowing that insulating materials can serve as diffusion barriers and influence mechanical stress in metal lines, it would have been obvious for a POSA to:

1. Introduce an Insulating Slit: A POSA would be motivated to form an insulating slit within the upper interconnect near the via. This would achieve two known benefits:

   • Stress Reduction: The insulating material, with different mechanical properties than copper, could locally reduce the tensile stress within the copper interconnect, thereby reducing the driving force for vacancy migration toward the via.
   • Physical Barrier: The insulating slit would act as a physical impediment, blocking the direct path of vacancy flow within the copper interconnect and preventing them from reaching the via.

2. Optimize Insulating Slit Design (e.g., Sixth and Seventh Embodiments): Once the concept of an insulating slit is adopted, its specific dimensions (e.g., length, such as "greater than or equal to twice and less than or equal to four times as large as the diameter of the via") and placement (e.g., being in contact with or slightly spaced from the via-connected portion) would be obvious optimizations for a POSA. The patent's explanation that a longer slit or a specific placement improves vacancy blocking or stress relief aligns with routine engineering optimization to enhance the desired effect.

Conclusion:

The conventional structure described in JP 2000-331991 clearly establishes the problem of via voiding due to stress-driven vacancy migration. The solutions proposed in US 7439623—introducing dummy vias or insulating slits—are applications of known principles of electromigration and stress migration mitigation. A person having ordinary skill in the art, faced with the problem articulated in JP 2000-331991, would have been motivated to combine the teachings of JP 2000-331991 with general knowledge of dummy structures and stress/electromigration barriers in semiconductor manufacturing to arrive at the claimed inventions. The specific structural and dimensional features claimed are primarily optimizations of these fundamental concepts, which a POSA would routinely explore to improve interconnect reliability. Therefore, the claimed inventions in US 7439623 would likely have been obvious under 35 U.S.C. § 103 when considered in light of JP 2000-331991 and the general knowledge of the art.