US 7439623

Here's a concise summary of US Patent 7439623:

US Patent 7439623: Semiconductor device having via connecting between interconnects

• Title: Semiconductor device having via connecting between interconnects
• Assignee:
  • Original: Matsushita Electric Industrial Co Ltd
  • Current: Advanced Integrated Circuit Process LLC
• Inventors: Takeshi Harada
• Filing Date: December 2, 2004 (Application No. US11/000,904)
• Issue Date: October 21, 2008 (Publication of US7439623B2)
• Abstract: A first insulating film is provided between a lower interconnect and an upper interconnect. The lower interconnect and the upper interconnect are connected to each other by way of a via formed in the first insulating film. A dummy via or an insulating slit is formed on/in the upper interconnect near the via.

Plain-Language Overview of Independent Claims (inferred from "Summary of the Invention"):

Please note that the full text of the claims was not explicitly provided in the user's prompt; therefore, the following summaries are derived from the "Summary of the Invention" section of the patent document.

1. First Interconnection Structure (Claim 1 equivalent): An interconnection structure includes a lower interconnect and an upper interconnect, separated by a first insulating film. A via in the first insulating film connects these interconnects. Additionally, a second insulating film is located beneath the first. The structure incorporates at least one "dummy via" connected to the upper interconnect, where the bottom of this dummy via extends into the second insulating film. This dummy via is not part of the active electrical circuit.
2. Second Interconnection Structure (Claim 2 equivalent): An interconnection structure includes a lower interconnect, an upper interconnect, and a first insulating film between them, with a via connecting the interconnects through the first insulating film. This structure is characterized by having at least one "insulating slit" formed directly within the upper interconnect.
3. Third Interconnection Structure (Claim 3 equivalent): An interconnection structure features a lower interconnect, an upper interconnect, and a first insulating film between them, with a via connecting the interconnects through the first insulating film. The upper interconnect is uniquely designed with a wider "first interconnect portion" and a narrower "second interconnect portion," and the via connects to this narrower second portion. The structure includes at least one "dummy portion" connected to the upper interconnect (and located on the first insulating film) positioned such that its proximity to the branching point of the wide and narrow interconnect portions is closer than its distance to the opposite end of the narrow interconnect portion.
4. First Method for Forming (Claim 4 equivalent): A method for creating an interconnection structure involves: depositing a first insulating film over a lower interconnect; then, using a single patterning and etching sequence, forming a via hole (to the lower interconnect), at least one dummy hole (near the via hole), and an upper interconnect trench (connected to both holes) within the first insulating film. Finally, a conductive material is deposited into these openings to form the upper interconnect, the functional via, and the dummy via (connected to the upper interconnect but electrically isolated from the lower interconnect). A key process step is ensuring the lower interconnect resides in a second insulating film below the first, and the dummy hole extends into this second insulating film.
5. Second Method for Forming (Claim 5 equivalent): A method for creating an interconnection structure involves: depositing a first insulating film over a lower interconnect; forming a via hole (to the lower interconnect) and an upper interconnect trench (connected to the via hole) within the first insulating film; then depositing conductive material to form the upper interconnect and the functional via. Subsequently, a second insulating film is deposited over the newly formed upper interconnect. A dummy hole is then formed in this second insulating film, reaching the upper interconnect and positioned near the functional via. Lastly, conductive material is deposited into this dummy hole to create at least one dummy via.
6. Third Method for Forming (Claim 6 equivalent): A method for creating an interconnection structure involves: depositing a first insulating film over a lower interconnect; forming a via hole (to the lower interconnect) and an upper interconnect trench (connected to the via hole) within the first insulating film; and then depositing a conductive material to form the upper interconnect and the functional via. The distinctive step here is that during the formation of the via hole and upper interconnect trench, a specific portion of the first insulating film is intentionally retained within the upper interconnect trench, adjacent to the via hole, thereby forming an insulating slit.
7. Fourth Method for Forming (Claim 7 equivalent): A method for creating an interconnection structure involves: depositing a first insulating film over a lower interconnect; then, within this first insulating film, forming a via hole (to the lower interconnect), an upper interconnect trench (which is patterned to be divided into a wider "first trench" and a narrower "second trench"), and a recess positioned near the branching point between these two trenches. Finally, conductive material is deposited into the upper interconnect trench, the via hole, and the recess, forming the upper interconnect (with its first portion in the wide trench and second portion in the narrow trench), the functional via, and a dummy portion (connected to the upper interconnect but insulated from the lower interconnect).

Legal Status and Litigation:

The patent US7439623B2 expired on October 4, 2025.

The patent family has been involved in litigation, including:

• First worldwide family litigation filed.
• PTAB case IPR2025-01211 filed (Not Instituted - Procedural).
• PTAB case IPR2025-01212 filed (Not Instituted - Procedural).
• A US case filed in the Texas Eastern District Court (case number 2:25-cv-00324).

As of April 26, 2026, searches for CAFC 2026 dockets specifically for patent 7439623 did not return any direct results indicating active appeals for this patent in the CAFC for the year 2026.