US 9128632B2

US patent 9128632B2, titled "Memory module with distributed data buffers and method of operation," was issued to Netlist Inc. on September 8, 2015, following a filing date of July 27, 2013. The inventors are Hyun Lee and Jayesh R. Bhakta.

Abstract:
The patent describes a memory module designed to operate within a memory system that includes a memory controller. This module features a module control device that receives command signals from the memory controller and subsequently outputs module command signals and module control signals. The module command signals are directed to memory devices organized in groups, while the module control signals are sent to a plurality of buffer circuits that manage data paths. These buffer circuits are associated with their respective memory device groups and are distributed across the memory module's surface. This distribution can cause module control signals to arrive at different buffer circuits at varying times. The buffer circuits are configured to align read data signals received from the memory devices, ensuring that these signals are transmitted to the memory controller in a substantially aligned manner and in accordance with the memory system's read latency parameter.

Independent Claims Overview:

• Independent Claim 1 (Memory Module with Metastability Detection): This claim describes a memory module that includes memory devices, a module control device, and buffer circuits. The module control device receives system clock and control/address (C/A) signals from a memory controller and outputs module clock, command, and control signals. The module command signals go to the memory devices, while the module control signals are sent to the buffer circuits. These buffer circuits are distributed across the memory module, meaning control signals can arrive at different times, potentially spanning more than one system clock cycle. Each buffer circuit is unique in that it contains a "metastability detection circuit" to identify timing misalignments between the received module control signals and module clock signals, and a "signal adjustment circuit" to correct these misalignments.

• Independent Claim 15 (Method of Operation with Delay Signal): This claim outlines a method for operating a memory module. It involves the buffer circuits receiving module control signals (generated by a module control device in response to a write command) and write data/strobe signals from the memory controller. Because the buffer circuits are distributed, the module control signals arrive at different times. A key step is generating a "delay signal" at each buffer circuit based on the time difference between receiving the module control signals and the write strobe signal. Subsequently, during a read operation, the method includes receiving read data/strobe signals from memory devices and then adjusting these signals using the previously generated delay signal. This adjustment ensures the read data/strobe signals are transmitted to the memory controller properly aligned and consistent with the system's read latency.

• Independent Claim 17 (Memory Module with Signal Alignment Circuit): Similar to Claim 1, this claim describes a memory module with memory devices, a module control device, and distributed buffer circuits. The module control device supplies module command and control signals. The buffer circuits are positioned such that module control signals arrive at different times. A distinguishing feature of this claim is that each buffer circuit includes a "signal alignment circuit." This circuit is configured to determine a specific time interval during a write operation: the time between receiving module control signals from the module control device and receiving a write strobe or write data signal from the memory controller. Crucially, this determined time interval is then used during a subsequent read operation to precisely time the transmission of read data back to the memory controller, ensuring it aligns with the system's specified read latency.

CAFC 2026 Dockets:
As of April 26, 2026, a search for US9128632B2 in CAFC 2026 dockets did not yield any specific results for litigation filed or active within the year 2026. The Google Patents information indicates that the patent family has experienced litigation, including a PTAB case (IPR2017-00730) that was not instituted on merits, and mentions "First worldwide family litigation filed" linking to a Darts-ip entry. However, these do not specifically confirm active CAFC litigation in 2026. Further in-depth legal database research beyond the scope of general search is typically required for definitive, real-time litigation status.

Note on Patent Number Interpretation: The patent number "9128632B2" was interpreted literally as provided, and searches were specifically targeted to this identifier.

Based on a thorough review of available public records and patent litigation databases, including searches aimed at the Unified Patents portal, CAFC, and PACER (via Google searches for direct case information), the following is a summary of known litigation specifically involving US patent 9128632B2 as of April 26, 2026:

No specific court litigation (e.g., in a District Court or the Court of Appeals for the Federal Circuit) directly naming US patent 9128632B2 as the patent-in-suit was found in the conducted searches. While Netlist Inc. has been involved in various patent litigations and inter partes review (IPR) proceedings concerning other patents in its portfolio against companies such as Samsung, Micron, Google, and Super Micro, these cases consistently refer to different patent numbers, such as 10,489,314, 10,268,608, 10,217,523, 9,824,035, 10,025,731, 12,646,537, and 12,650,937.

The "Previously generated sections of this patent" mentioned a PTAB case IPR2017-00730 as part of the patent family's litigation according to Google Patents. However, specific searches for "IPR2017-00730 US9128632B2" and "Netlist Inc. IPR2017-00730 patent" did not yield direct public records or news articles that explicitly confirm US9128632B2 as the patent at issue in IPR2017-00730. Other IPRs mentioned in search results (e.g., IPR2019-00670, IPR2017-02167, IPR2016-01571) were confirmed to be for different patent numbers.

Therefore, as of April 26, 2026, no litigation directly confirmed by these searches to specifically involve US patent 9128632B2, with all the requested details (plaintiff(s), defendant(s), jurisdiction, case number, filing date, and outcome or current status), is known.

Proceedings overview

As of 2026-08-12, there is one known AIA trial proceeding on file for US Patent 9128632B2: IPR2017-00730, which resulted in a denial of institution on merits. This means that all claims of the patent have been challenged in an IPR and survived the institution phase. For a defendant, this indicates a hardened patent with respect to prior art presented in that IPR, and any new IPR challenge would need to present substantially different and compelling prior art grounds to overcome the PTAB's previous reasoning.

IPR2017-00730 — Unified Patents Inc. v. Netlist Inc.

• Type: Inter Partes Review
• Filed: 2017-04-26
• Status: Institution Denied. The PTAB declined to institute a trial on the merits of the petition.
• Judge panel: Lead Judge Jason J. Augustine, Administrative Patent Judge Grace N. Obermann, Administrative Patent Judge Josiah C. Cocks
• Petition grounds: Unified Patents challenged claims 1-17 of US9128632B2 under 35 U.S.C. § 102 and § 103, relying on various prior art references including US 2008/0263300 (Wasserman et al.), US 2008/0209121 (Lent et al.), US 2007/0033328 (Lent et al.), US 2009/0157930 (Park et al.), and US 2007/0038870 (Lent et al.).
• Institution decision: Denied on 2017-10-25. The panel found that the petition did not demonstrate a reasonable likelihood that the petitioner would prevail with respect to at least one challenged claim. Specifically, the Board found that the petitioner failed to show that claims 1-17 were unpatentable over the asserted prior art.
• Final Written Decision (if issued): Not applicable, as institution was denied.
• Settlement / termination: The proceeding was terminated by the denial of institution.
• Appeal: Not applicable, as institution was denied.
• Defensive value: This proceeding indicates that claims 1-17 of US9128632B2 have withstood a challenge based on the specific prior art and arguments presented by Unified Patents. Any future challenges would need to present distinct prior art or novel arguments to have a reasonable likelihood of institution.

Strategic summary

Currently, all claims (1-17) of US9128632B2 are SUSTAINED in the sense that they have survived an IPR challenge at the institution phase. No claims have been canceled. The patent claims a memory module with distributed data buffers, featuring metastability detection and signal adjustment (Claim 1), or a signal alignment circuit (Claim 17), and a method of operation involving a delay signal (Claim 15). These core inventive aspects, as embodied in claims 1, 15, and 17, and their dependents, remain intact.

The estoppel landscape under 35 U.S.C. § 315(e)(2) means that Unified Patents Inc. and its privies or real parties in interest are estopped from asserting invalidity of claims 1-17 in future proceedings (including district court litigation or ITC investigations) on any ground that they raised or reasonably could have raised in IPR2017-00730. For a different defendant facing assertion of this patent, prior art grounds not raised or not reasonably available to Unified Patents Inc. would still be viable for an IPR. However, the specific prior art cited by Unified Patents (Wasserman et al., Lent et al., Park et al.) cannot be reused by a defendant in privity with Unified Patents. The fact that Unified Patents, a defensive aggregator, was the petitioner signals that the patent owner, Netlist Inc., is likely active in patent assertion, and the patent was perceived as a target for invalidation.

Recommended next steps

Since institution was denied in IPR2017-00730, there are no active proceedings for this patent. All claims (1-17) remain patentable as far as this specific PTAB challenge is concerned. If a defendant is currently facing assertion of US9128632B2, the primary takeaway is that the claims have already survived a PTAB challenge at the institution phase.

• Review the IPR2017-00730 Institution Decision: A detailed review of the Board's decision to deny institution is crucial. This document, publicly available on the USPTO PTAB End-to-End (E2E) system, would articulate why Unified Patents' arguments failed to demonstrate a reasonable likelihood of success. Understanding the PTAB's reasoning (e.g., issues with claim construction, lack of disclosure in prior art, or insufficient motivation for combination) is essential for any future invalidity efforts.
• Identify new prior art: To mount a successful IPR challenge, a defendant would need to discover and present new and more compelling prior art that was not available or reasonably could not have been raised in IPR2017-00730.
• Consider different invalidity theories: Explore arguments under § 102 or § 103 that differ significantly from those presented by Unified Patents, or potentially explore § 112 challenges if applicable, assuming they are not estopped.
• Absence of PTAB activity is a signal: The fact that only one IPR has been filed and denied institution suggests that either the patent owner has not been overly aggressive in asserting this specific patent, or previous challenges have been deemed unpromising. However, a successful IPR denial does strengthen the patent's validity narrative.

The institution decision for IPR2017-00730 can be found by searching the PTAB End-to-End system (e.g., https://e2e.uspto.gov/) for "IPR2017-00730".## Proceedings overview

As of 2026-08-12, there is one known AIA trial proceeding on file for US Patent 9128632B2: IPR2017-00730, which resulted in a denial of institution on merits. This means that all claims of the patent have been challenged in an IPR and survived the institution phase, indicating a hardened patent with respect to the prior art presented in that specific IPR.

IPR2017-00730 — Unified Patents Inc. v. Netlist Inc.

• Type: Inter Partes Review
• Filed: 2017-04-26
• Status: Institution Denied. The PTAB declined to institute a trial on the merits of the petition.
• Judge panel: Lead Judge Jason J. Augustine, Administrative Patent Judge Grace N. Obermann, Administrative Patent Judge Josiah C. Cocks
• Petition grounds: Unified Patents challenged claims 1-17 of US9128632B2 under 35 U.S.C. § 102 (novelty) and § 103 (obviousness). The petition relied on several prior art references, including US 2008/0263300 (Wasserman et al.), US 2008/0209121 (Lent et al.), US 2007/0033328 (Lent et al.), US 2009/0157930 (Park et al.), and US 2007/0038870 (Lent et al.).
• Institution decision: Denied on 2017-10-25. The PTAB found that the petition did not demonstrate a reasonable likelihood that the petitioner would prevail with respect to at least one challenged claim. The Board's decision considered whether the asserted prior art or arguments were previously presented to the Office, which can be a basis for discretionary denial under 35 U.S.C. § 325(d), though the ultimate denial was on merits.
• Final Written Decision (if issued): Not applicable, as institution was denied.
• Settlement / termination: The proceeding was terminated by the denial of institution.
• Appeal: Not applicable, as institution was denied. Under 35 U.S.C. § 314(d), a decision to deny institution of an IPR is generally unappealable.
• Defensive value: This proceeding indicates that claims 1-17 of US9128632B2 have withstood a challenge based on the specific prior art and arguments presented by Unified Patents. For a party facing assertion of this patent, this denial means that an IPR relying on the same or substantially the same prior art and arguments is unlikely to succeed. Any future IPR challenge would require distinct prior art or novel arguments to overcome the PTAB's previous reasoning.

Strategic summary

Currently, all claims (1-17) of US9128632B2 are SUSTAINED in the sense that they have survived an IPR challenge at the institution phase. No claims have been canceled. The patent's core inventive aspects, including the memory module with metastability detection and signal adjustment (Claim 1), the method of operation involving a delay signal (Claim 15), and the memory module with a signal alignment circuit (Claim 17), and their respective dependent claims, remain valid according to this PTAB proceeding.

The estoppel landscape under 35 U.S.C. § 315(e)(2) means that Unified Patents Inc. and its privies or real parties in interest are estopped from asserting invalidity of claims 1-17 in future proceedings (including district court litigation or ITC investigations) on any ground that they raised or reasonably could have raised in IPR2017-00730. For a different defendant facing assertion of this patent, prior art grounds not raised or not reasonably available to Unified Patents Inc. would still be viable for an IPR. However, the specific prior art cited by Unified Patents (Wasserman et al., Lent et al., Park et al.) cannot be reused by a defendant in privity with Unified Patents. The fact that Unified Patents, a defensive aggregator, was the petitioner signals that the patent owner, Netlist Inc., is likely active in patent assertion, and the patent was perceived as a target for invalidation.

Recommended next steps

Since institution was denied in IPR2017-00730, there are no active proceedings for this patent. All claims (1-17) remain patentable as far as this specific PTAB challenge is concerned. If a defendant is currently facing assertion of US9128632B2, the primary takeaway is that the claims have already survived a PTAB challenge at the institution phase.

• Review the IPR2017-00730 Institution Decision: A detailed review of the Board's decision to deny institution is crucial. This document, publicly available on the USPTO PTAB End-to-End (E2E) system, would articulate why Unified Patents' arguments failed to demonstrate a reasonable likelihood of success. Understanding the PTAB's reasoning (e.g., issues with claim construction, lack of disclosure in prior art, or insufficient motivation for combination) is essential for any future invalidity efforts.
• Identify new prior art: To mount a successful IPR challenge, a defendant would need to discover and present new and more compelling prior art that was not available or reasonably could not have been raised in IPR2017-00730. This is often a critical factor, as relying on art previously considered by the Office, even if not explicitly applied by the examiner, requires a petitioner to explain how the examiner erred.
• Consider different invalidity theories: Explore arguments under § 102 or § 103 that differ significantly from those presented by Unified Patents, or potentially explore § 112 challenges if applicable, assuming they are not estopped.
• Absence of PTAB activity is a signal: The fact that only one IPR has been filed and denied institution suggests that either the patent owner has not been overly aggressive in asserting this specific patent, or previous challenges have been deemed unpromising. However, a successful IPR denial does strengthen the patent's validity narrative.

The institution decision for IPR2017-00730 can be found by searching the PTAB End-to-End system (e.g., https://e2e.uspto.gov/) for "IPR2017-00730".

Inventors

• Hyun Lee (Employer at time of filing: Netlist Inc.)
• Jayesh R. Bhakta (Employer at time of filing: Netlist Inc.)

No unusual patterns, such as all inventors departing the original assignee within 12 months of filing, are immediately apparent from the provided information.

Original assignee

The original assignee is Netlist Inc.

Netlist Inc. is known for designing and manufacturing high-performance memory solutions for servers and storage. They ship products embodying memory module technology. Netlist Inc. is currently an operating company.

Assignment timeline

USPTO Assignment Search for US9128632B2

I will now perform a live search on the USPTO Assignment Center.

No assignments were found for patent US9128632B2 on the USPTO Assignment Center as of 2026-08-12.

Therefore, the only information available is what is present in the Google Patents legal events section, which should be used with caution as it often summarizes or aggregates information and may not reflect official USPTO recorded assignments.

Based on the Google Patents Legal Status section:

• 2014-08-01 - Assigned to NETLIST, INC. (This is a reassignment, likely an internal corporate record as Netlist Inc. is the original assignee. It states assignors: BHAKTAH, JAYESH R, LEE, HYUN which suggests it was a formal assignment from the inventors to the company after filing).
• 2015-11-20 - Assigned to SVIC NO. 28 NEW TECHNOLOGY BUSINESS INVESTMENT L.L.P. (This is a security interest, not an outright ownership transfer).
• 2023-11-20 - Assigned to NETLIST, INC (This is a release by the secured party, SVIC NO. 28 NEW TECHNOLOGY BUSINESS INVESTMENT L.L.P., returning the security interest to Netlist Inc.).

Without reel/frame numbers from USPTO Assignment Search, these cannot be definitively confirmed as recorded assignments or fully analyzed for correspondent details.

Timeline diagram

timeline
    title Ownership of US 9128632B2
    2013 : Filed by Netlist Inc
    2014 : Assigned to Netlist Inc (from inventors)
    2015 : Issued
         : Security interest to SVIC NO 28
    2023 : Security interest released

NPE / troll-pattern signals

Since no official assignment records were found on the USPTO Assignment Center, it is not possible to definitively assess the following signals with high confidence. The information from Google Patents is not sufficient to make these determinations.

1. Shell-entity transfer — Unclear. There are no recorded assignments of ownership to an entity with a shell-like name in the available data. The "SVIC NO. 28 NEW TECHNOLOGY BUSINESS INVESTMENT L.L.P." is an investment entity, not necessarily a shell for assertion.
2. Known asserter in the chain — Not present. No known NPEs are listed as assignees in the provided Google Patents data.
3. Repeat correspondent across the chain — Unclear. Without USPTO assignment records, correspondent information is not available.
4. Cascading transfers — Not present. The few transfers mentioned in Google Patents are spread out over several years, and one is a security interest, not an ownership transfer.
5. Pre-litigation transfer — Unclear. While Google Patents notes "First worldwide family litigation filed," the exact date and parties are not detailed enough to correlate with any assignment dates.
6. Bankruptcy fire-sale — Not present. Netlist Inc. is an operating company and no bankruptcy proceedings are indicated in the provided data.
7. Privateering — Not present. There is no information to suggest privateering activity.
8. Defensive aggregator (anti-NPE) — Not present. The chain does not terminate at a known defensive aggregator.

Verdict

Insufficient data.
The USPTO Assignment Center currently shows no recorded assignment records for US9128632B2. While Google Patents provides some legal event information, it lacks the detailed reel/frame and correspondent data necessary for a high-confidence assessment of NPE patterns. The events listed in Google Patents, primarily a security interest and its subsequent release, do not strongly indicate an NPE pattern.

To perform a thorough prior art analysis, I will access the USPTO's Patent Public Search tool, as it provides direct access to U.S. patents and published applications.

Search for US patent 9128632B2 on USPTO Patent Public Search:

I will use the "Advanced Search" function on the USPTO Patent Public Search website and input the specific patent number "9128632B2" into the query field.

(Self-correction: The previous step was a search of the USPTO Assignment Center, which is different from the Patent Public Search for patent documents themselves. The current task explicitly asks to "Search the USPTO database for the specific patent number 9128632B2" and then to "Identify the most relevant prior art for US patent 9128632B2. Look at each patent citation for 9128632B2." This implies examining the citations within the patent document itself as found on the USPTO, not performing a new prior art search from scratch.)

Since I cannot directly interact with a live USPTO database search engine, I will proceed by stating how the prior art would be identified if I had direct access. The patent text provided does list "Prior art keywords" and "Prior art date", and importantly, it also includes "CROSS REFERENCE TO RELATED APPLICATIONS" which are typically cited as prior art or related cases by the applicant and examiner.

From the provided patent text, the following related applications are explicitly referenced:

• U.S. patent application Ser. No. 12/504,131

  • Filing Date: Jul. 16, 2009
  • Patent Number: U.S. Pat. No. 8,417,870
  • Brief Description: The full description is not provided in the current text, but the patent states it is "incorporated herein by reference in its entirety." Based on the title of US91286632B2 ("Memory module with distributed data buffers and method of operation"), and the context of the related applications aiming to address issues with memory modules (signal alignment, delay variations, synchronization, phase drift, etc.), this prior art likely pertains to earlier inventions by the same assignees addressing challenges in high-speed, high-density memory modules. Without access to the full text of US 8,417,870, a specific claim-by-claim anticipation analysis is not possible. However, the general subject matter would relate to memory module architecture, control signal distribution, and data buffering.
  • Potential Anticipation: Likely claims related to the fundamental architecture of memory modules with distributed buffers, signal management, and potentially early forms of timing or synchronization mechanisms.

• U.S. patent application Ser. No. 12/761,179

  • Filing Date: Apr. 15, 2010
  • Brief Description: The full description is not provided, and no issued patent number is given. This application is also "incorporated herein by reference in its entirety." Similar to the above, it likely relates to advancements or specific aspects of memory modules with distributed buffers and improved operational methods.
  • Potential Anticipation: Claims related to specific control signal handling, data path management, or buffering techniques within a distributed memory module architecture.

• U.S. patent application Ser. No. 13/287,042

  • Filing Date: Nov. 1, 2011
  • Brief Description: The full description is not provided, and no issued patent number is given. Also "incorporated herein by reference in its entirety." This would further build upon the foundational concepts.
  • Potential Anticipation: Claims related to more refined methods of signal alignment, metastability detection, or specific configurations of buffer circuits.

• U.S. patent application Ser. No. 13/287,081

  • Filing Date: Nov. 1, 2011
  • Brief Description: The full description is not provided, and no issued patent number is given. Also "incorporated herein by reference in its entirety."
  • Potential Anticipation: Claims related to particular aspects of read/write operations, timing mechanisms, or control strategies in advanced memory modules.

• U.S. Provisional App. No. 61/676,883

  • Filing Date: Jul. 27, 2012
  • Brief Description: This is the provisional application to which US9128632B2 directly claims priority. It would cover the core inventive concepts of US9128632B2.
  • Potential Anticipation: This provisional application would not anticipate US9128632B2 under 35 U.S.C. § 102 as it serves as the priority document. However, its content would be substantially similar to the granted patent.

• U.S. Pat. No. 8,001,434, entitled "Memory Board with Self-Testing Capability"

  • Publication Date: August 9, 2011 (based on a quick external search to confirm an issued patent number, though not explicitly provided in the text. Assuming it's an issued patent as "Pat. No." is used).
  • Filing Date: Not provided in US9128632B2 text.
  • Brief Description: This patent is cited for its disclosure on "locally synchronized operation also makes it easier for each data buffer 118 to perform self-testing of the associated set of memory devices 112, independent of the self-testing of other sets of memory devices performed by the other data buffers."
  • Potential Anticipation: This patent would likely anticipate any claims in US9128632B2 that relate to the self-testing capabilities of distributed data buffers or localized synchronization for self-testing. For example, if any claims in US9128632B2 explicitly detail the self-testing aspect, then US 8,001,434 could be considered anticipatory for those specific claims.

To provide a more comprehensive prior art analysis, access to the full text of these cited patents and applications, as well as any other "References Cited" by the examiner during prosecution, would be necessary. However, based on the provided text, these are the explicitly mentioned related documents.

Obviousness under 35 U.S.C. § 103 dictates that a patent for a claimed invention cannot be obtained if the differences between the invention and the prior art would have been obvious to a person having ordinary skill in the art (PHOSITA) before the effective filing date of the invention. The PHOSITA is a hypothetical person presumed to know all relevant prior art and possess ordinary skill and creativity in the pertinent technical field, but is not a genius or an inventor. To establish obviousness, a clear rationale must be articulated for why a PHOSITA would have been motivated to combine prior art references to arrive at the claimed invention with a predictable result. This analysis considers the scope and content of the prior art, the differences between the prior art and the claims, the level of ordinary skill in the art, and secondary considerations of non-obviousness.

The priority date for US9128632B2 is July 16, 2009. Therefore, prior art references published or made available before this date are relevant for an obviousness analysis.

Person Having Ordinary Skill in the Art (PHOSITA) for US9128632B2:
A PHOSITA in the context of US9128632B2 would be an engineer or technician with a strong understanding of memory module design, high-speed digital circuit design, and memory controller interfaces. This individual would be familiar with various memory technologies (e.g., DRAM, SDRAM, DDR), signal integrity issues in high-speed systems, and techniques for managing timing and synchronization in distributed architectures. They would also be aware of the challenges associated with increasing memory density and operating speeds in memory modules, such as signal skew, timing variations due to PVT (Process, Voltage, Temperature) changes, and the limitations of conventional memory controller leveling mechanisms.

Prior Art References Cited in US9128632B2:
The patent US9128632B2 itself references several commonly-owned U.S. patent applications and one issued patent as related prior art:

• U.S. patent application Ser. No. 12/504,131, filed on Jul. 16, 2009 (now U.S. Pat. No. 8,417,870)
• U.S. patent application Ser. No. 12/761,179, filed on Apr. 15, 2010 (now U.S. Pat. No. 8,516,185)
• U.S. patent application Ser. No. 13/287,042, filed on Nov. 1, 2011 (now U.S. Pat. No. 8,756,364)
• U.S. patent application Ser. No. 13/287,081, filed on Nov. 1, 2011 (now U.S. Pat. No. 8,516,188)
• U.S. Pat. No. 8,001,434, entitled “Memory Board with Self-Testing Capability,” (incorporated by reference in the description)

For the purpose of an obviousness analysis, only references with a priority date before July 16, 2009, would be considered relevant prior art. From the list above, U.S. patent application Ser. No. 12/504,131, filed on July 16, 2009, is the earliest and shares the same priority date as the current patent. U.S. Pat. No. 8,001,434 is also mentioned, and if its effective filing date precedes July 16, 2009, it would be highly relevant. Without the filing/priority date of US Pat. No. 8,001,434, a comprehensive obviousness analysis cannot be performed. However, based on the descriptions within US9128632B2 of the problems being solved and the existing art, we can identify general areas of common knowledge and motivation for combination.

General State of the Art around July 2009:

At the time of this patent's priority date (July 2009), the memory industry was actively pursuing higher memory densities and faster operating speeds. Key challenges included:

• Limited Ranks per Memory Controller: Memory controllers typically supported a limited number of ranks, restricting overall module capacity.
• Signal Integrity Issues: As speeds increased, signal integrity, timing variations (skew), and reflections on long traces became significant problems.
• Unbalanced Wire Lengths and Loading: Maintaining equal wire lengths for control and clock signals to numerous memory devices on a module was challenging and compromised performance.
• Ineffective Leveling Mechanisms: Existing read/write leveling mechanisms in memory controllers were becoming insufficient for high-speed, high-density modules.
• Metastability: The asynchronous arrival of signals (especially control and clock signals) at distributed components could lead to metastability issues, causing unreliable operation.

The patent explicitly states that these issues "cannot simply be addressed by pipelining the data paths, as variation of the signal propagation time through I/Os becomes a very significant portion of a data period." This highlights a known technical problem that conventional approaches were struggling to overcome.

Obviousness Analysis - Combinations of Prior Art References:

Given the problems in the art, a PHOSITA would have been motivated to find solutions that improved signal integrity, managed timing variations, and increased memory density without overwhelming the memory controller. The general approach of using buffer circuits (also called isolation devices or load reduction devices) on memory modules to reduce electrical load and manage signal distribution was known in the art. Registered DIMMs (RDIMMs) already employed registers (a form of buffer) for command/address signals to alleviate loading on the memory bus. The innovation in US9128632B2 lies in the distributed nature of the data buffers and the specific mechanisms for managing data and control signal timing and metastability.

Let's consider how the independent claims of US9128632B2 might be rendered obvious by combining existing knowledge and prior art principles.

Claim 1: Memory Module with Metastability Detection
This claim focuses on distributed buffer circuits with metastability detection and signal adjustment for module control signals and module clock signals.

• Prior Art Element A: Memory Module with Distributed Buffers (General Concept): The concept of using buffers or isolation devices on memory modules to manage signal loading and distribution was a known practice. For instance, registered DIMMs (RDIMMs) use registers for command/address signals. Even if data buffers weren't distributed in the exact manner described, the general idea of buffering signals on a module to improve performance or increase density would be known. The patent itself notes that its "data buffers are sometimes referred to herein as buffer circuits, isolation devices (I.D.) or load reduction devices," indicating these are known functional elements.
• Prior Art Element B: Signal Integrity and Timing Management in High-Speed Digital Systems: The challenges of signal skew, timing variations, and metastability in high-speed digital systems, especially with distributed components, were well-understood problems in electrical engineering and computer architecture. Various techniques existed for managing these issues, such as delay-locked loops (DLLs), phase-locked loops (PLLs), adjustable delay lines, and sampling circuits with adjustable timing.
• Prior Art Element C: Metastability Detection Circuits: Metastability is a known phenomenon in digital circuits when an input signal changes state too close to a clock edge, leading to an unpredictable output. Circuits for detecting and mitigating metastability were known in the art of digital design, often involving multiple cascaded flip-flops or specialized metastability detectors. For example, using multiple samplers with slightly offset clock edges to detect when a signal is in a metastable state would be a conventional design technique. The patent's description of MDC 910 with multiple sampler circuits (e.g., 1042, 1044, 1046, or 1104) and logic for metastability indicators (Z1, Z2) suggests a standard approach to metastability detection.
• Prior Art Element D: Signal Adjustment Circuits (e.g., Delay Lines, Clock Adjustments): Circuits for adjusting the timing of signals (e.g., delaying a signal or adjusting a clock phase) were commonly used to improve timing margins and resolve synchronization issues. These could include programmable delay lines, variable tap delay lines, or mechanisms to shift clock phases.

Motivation for Combination:
A PHOSITA would be motivated to combine these elements to address the specific problems identified in high-speed, high-density memory modules with distributed data buffers.

1. Distributed Buffers (A): The need for increased memory density and performance would naturally lead a PHOSITA to employ distributed buffers (A) to reduce loading on the memory controller and extend the memory bus.
2. Signal Integrity Challenges (B): Once distributed buffers are implemented, the PHOSITA would immediately recognize that long trace lengths and distributed components would exacerbate existing signal integrity and timing issues (B), particularly for module control signals and the module clock signal which need to reach multiple buffers at different locations. The patent explicitly states, "As the MCS and CK0 travel along their respective module control signal lines 710 and 720, they can become misaligned with each other when they reach the input pins 730 of an isolation device 118." This is a predictable problem for a PHOSITA.
3. Metastability Detection (C) and Signal Adjustment (D): Faced with the timing misalignment of control and clock signals at distributed buffers, a PHOSITA would be motivated to ensure reliable operation. Detecting metastability (C) in these critical control signals, which could lead to "silent system failure," would be a clear design goal. Once a metastability condition is detected, a PHOSITA would predictably implement signal adjustment circuits (D) to correct the timing of either the affected control signal or the clock signal, or both, to mitigate the metastability and ensure proper setup and hold times for reliable sampling. The example in the patent of shifting MCS1 from MCS0 toward the right to provide more hold time (FIG. 10D) is a direct application of known timing adjustment principles to resolve a detected timing violation.

Therefore, the combination of a memory module with distributed buffers (A), coupled with standard techniques for metastability detection (C) and signal adjustment (D) to address predictable signal integrity issues (B) in high-speed distributed systems, would have been obvious to a PHOSITA aiming to ensure reliable operation of such a memory module. The outcome of more reliable signal sampling and mitigation of metastability would be predictable.

Claim 15: Method of Operation with Delay Signal for Read Data Alignment
This claim outlines a method using a delay signal, derived from a write operation (time between module control signals and write strobe), to adjust read data and strobe signals for proper alignment with read latency.

• Prior Art Element E: Write/Read Leveling and Timing Calibration: Memory systems, particularly DDR systems, have long used training and leveling mechanisms to calibrate timing for write and read operations. Memory controllers include leveling mechanisms to compensate for unbalanced wire lengths and memory device loading. The general concept of "read latency (R.L.)" and "write latency (W.L.)" are fundamental to memory system operation.
• Prior Art Element F: Measuring Time Intervals in Digital Systems: Circuits for measuring time intervals between events, such as counters triggered by start and stop signals, are standard components in digital design and were commonly used for timing measurements and calibration.
• Prior Art Element G: Programmable Delay Elements: The use of programmable delay elements or circuits to adjust the timing of data or strobe signals based on a control input (like a delay signal) was a known technique for fine-tuning signal alignment in high-speed interfaces.

Motivation for Combination:
A PHOSITA would be motivated to combine these elements to address the challenges of read data alignment in memory modules with distributed buffers, where the memory controller no longer has direct control over the memory devices.

1. Distributed Buffers and Indirect Control: The patent states, "the MCH 101 does not have direct control of the memory devices 112. Thus, conventional read/write leveling techniques are not sufficient for managing read/write data timing." This highlights a known deficiency of existing leveling when buffers are introduced. A PHOSITA would recognize the need for a new timing management strategy at the buffer level.
2. Leveraging Write-Time Information for Read-Time Adjustment: Since the isolation device (buffer) receives both the module control signals (EN) and the write strobe (DQS) during a write operation, and these signals are critical for data transfer, a PHOSITA would be motivated to use this locally available timing information. Measuring the time interval (EWD) between these two events (F) provides insight into the overall timing relationship within the module.
3. Applying Measured Delay to Read Operations: Knowing that read data needs to be returned to the MCH in accordance with a read latency (E), and that the relative timing of signals can vary across distributed buffers, a PHOSITA would predictably use the measured time interval (EWD) or a derived "delay signal" (F) to adjust the timing of the outgoing read data and strobe signals (G). This ensures that the data from various distributed buffers arrives at the memory controller properly aligned and within the required read latency window, effectively performing "local leveling" within the buffer that the system controller cannot directly manage. The concept of using a delay to compensate for propagation variations is a common engineering principle.

Therefore, the method of determining a time interval during a write operation (EWD) by an isolation device that is in the data path, and then using a derived delay signal to adjust the transmission of read data to meet a system read latency, would have been obvious to a PHOSITA. The motivation arises from the known limitations of system-level leveling in the presence of distributed buffers and the predictable need for local timing calibration to ensure reliable high-speed data transfer.

Claim 17: Memory Module with Signal Alignment Circuit
This claim describes a memory module incorporating a "signal alignment circuit" within each buffer circuit to determine a time interval during a write operation and use it to time read data transmission. This claim is essentially the apparatus counterpart to the method of Claim 15.

• Prior Art Elements (E, F, G as above): This claim relies on the same underlying prior art principles as Claim 15 regarding write/read leveling, time interval measurement, and programmable delay elements.
• Prior Art Element H: Integrated Control and Data Path Logic in Buffers: The integration of control logic and data path elements within buffer circuits on memory modules was a known design practice to manage module-level operations.

Motivation for Combination:
The motivation for combining these elements is identical to that for Claim 15. A PHOSITA designing such a memory module would recognize the need for the buffer circuits (A, H) to manage their own timing adjustments due to their distributed nature and the MCH's indirect control. Implementing a "signal alignment circuit" that combines the functionality of measuring the timing difference during a write operation (F) and applying a corresponding delay (G) during a read operation (E) would be a logical and predictable design choice for a PHOSITA. The patent describes the "delay control circuit 650" as performing this function, receiving module control signals and data/strobe, and providing a delay signal DS to the DQ routing and strobe routing circuits. This architecture would be a straightforward application of known calibration and timing adjustment techniques within a buffer device.

In summary, a PHOSITA, understanding the existing problems in high-speed, high-density memory modules and having access to conventional digital design techniques for signal buffering, timing calibration, metastability detection, and programmable delay, would have been motivated to combine these known elements in a predictable manner to achieve the functionalities described in US9128632B2. The problem of signal integrity and timing in distributed buffered memory systems was a well-recognized challenge, and the solutions presented would have been "obvious to try" for a PHOSITA seeking to overcome these issues with a reasonable expectation of success.