US 6681358

I'll run a few targeted searches for this specific patent number before summarizing.

Search results (as of April 26, 2026)

USPTO / patent databases — found. US 6,681,358 B1 is confirmed in USPTO/Google Patents/Justia records. No reissue, reexamination, IPR/PGR, or certificate-of-correction proceeding for this number surfaced in the searches.

CAFC 2026 dockets — no match found. I searched for "6681358" together with CAFC/Federal Circuit docket terms and found nothing tying this patent number to any 2026 (or earlier) Federal Circuit appeal. The 2026 CAFC results that came back (e.g., Ironburg v. Valve, No. 24-2088; Regenxbio v. Sarepta; mCom IP v. City National Bank; Ollnova v. ecobee) involve unrelated patents. I cannot confirm any CAFC litigation involving US 6,681,358, and I would treat the absence as "no evidence found," not as proof none exists. A "bond number 6681358" appearing in a Moses Lake, WA municipal document is an unrelated coincidence and is not this patent.

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Bibliographic summary of US 6,681,358 B1

Source: https://patents.google.com/patent/US6681358/en

Abstract (verbatim)

"A multiport BIST method and apparatus therefor are disclosed. The multiport BIST is advantageously based on adapting a single port BIST method by dividing the memory into sections based on the number of ports and applying the single port BIST simultaneously through all ports simultaneously (inverting where appropriate), so as to test the sections in parallel. In one embodiment of the invention, an integrated circuit device comprises a multiport memory and a built-in self-test (BIST) unit that applies a first test pattern of read and write operations to a first port of the memory and applies a second test pattern of read and write operations to a second port of the memory. The addresses in the first test pattern are offset from addresses in the second test pattern by a fixed amount. The ports preferably have adjacent bit lines, and the data values conveyed by the first and second test patterns are preferably complementary. Also, the fixed amount is preferably selected so that the read and write operations of the first and second port are concurrently directed to memory words that share common bit lines."

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Plain-language overview of the six independent claims

Claim 1 (device). An IC containing a multiport digital memory (which has address rows and address columns) plus a BIST unit. The BIST runs one pattern of reads/writes on port 1 and at the same time a second pattern on port 2, where the addresses used by the second pattern are displaced from those of the first by a fixed offset. Notably, the claim recites that the offset is determined by a ratio of the number of ports to the number of address rows or address columns of the memory (i.e., the memory is effectively carved into per‑port sections of size N/P).

Claim 6 (device). Same concurrent, fixed‑offset two‑port testing idea, but reciting that the memory is divided into segments, one assigned per port. The address generator walks through every location of port 1's own segment, and — the distinguishing limitation — walks that same assigned segment a second time before port 1 is allowed to address anything outside its assigned segment. (This maps to the "each‑port‑does‑one‑segment‑at‑a‑time" embodiment, i.e., repeating the March passes segment by segment.)

Claim 8 (method). The method counterpart: divide the memory into sections based on the number of ports, then apply a first test pattern to port 1 while concurrently applying a second test pattern to port 2, with the addresses in the two patterns separated by a fixed offset.

Claim 13 (method). Concurrent two‑port, fixed‑offset method as in claim 8, plus the segmented variant: each port has an assigned segment, and the method consecutively addresses all locations in port 1's assigned segment and then addresses that same segment again before touching any location outside it.

Claim 15 (device). Multiport memory where separate segments are associated with separate ports, and a BIST that concurrently runs offset (fixed amount) patterns on two ports — but here the offset is defined by its effect on word lines: the concurrent operations of the two ports must land on memory words sharing neighboring word lines. This is the "all ports accessing different words in the same row" / multiple‑word‑line‑assertion variant (FIG. 7 quadrant arrangement), aimed at weak‑grounding and word‑line coupling faults.

Claim 20 (device). Multiport memory divided into column groups (one or more columns each), one group assigned per port. The address generator consecutively addresses every location in port 1's assigned column group, and repeats that same column group before addressing outside it (the column‑group analogue of claims 6 and 13).

Dependent claims (briefly)

• Claims 2–5 (dep. from 1): offset chosen so concurrent access hits words sharing neighboring bit lines; data values on the two patterns are complementary; the two ports' bit lines are adjacent; address generator consecutively addresses the whole memory through port 1.
• Claim 7 (dep. from 1), 14, 19: a comparator checks data concurrently read from both ports against expected values.
• Claims 9–12 (dep. from 8): mirror claims 2–5 in method form.
• Claims 16–18 (dep. from 15): complementary data; adjacent word lines; consecutive addressing of the whole memory via port 1.

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Context and caveats

• Technical purpose: The patent addresses interport faults in multiport memories (bit‑line/word‑line shorts and coupling between ports). It adapts a single‑port BIST — the description uses the March C algorithm, with its six passes — by splitting the memory into as many sections as there are ports, running the algorithm through all ports simultaneously, inverting the data pattern on odd‑numbered ports, and starting each port in a different section. The stated benefit is that test time stays the same as the single‑port BIST and is independent of the number of ports, while interport fault coverage is added. Prior approaches criticized in the specification: the "Single Port BIST" method, the "Shadow Read" method, and the "Dual Port" method (low‑address‑up / high‑address‑down).
• Cited prior art (only two references, both LSI): US 5,822,228 and US 5,909,404. Seven non‑patent citations, including Hnatek, "4‑Kilobit Memories Present a Challenge to Testing," Computer Design, May 1975.
• Noticeable sequel art: US 6,550,032 B1 ("Detecting interport faults in multiport static memories") appears in the "similar documents" list and uses very similar fixed‑offset concurrent‑operation language; and US 8,201,032 B2 / US 2008/0016418 A1 ("Generalized BIST for multiport memories," Agere Systems) cites this patent. I have not verified a formal family relationship, so treat that as an observation, not a confirmed link.
• Internal inconsistency in the source text (flagged, not corrected): the specification states the incorporated‑by‑reference application "Ser. No. 09/363,697, filed Jul. 28, 1991." A 09/xxx,xxx series number is inconsistent with a 1991 filing date; I am reporting it exactly as it appears in the patent.
• Claim‑language note: Claim 1's "offset is determined by a ratio of a number of ports to a number of address rows or address columns" is broader/differently worded than the Abstract and claim 2, which describe the offset by its effect (sharing neighboring/common bit lines).

If you want, I can attempt a deeper litigation‑history pull (e.g., Docket Navigator / CourtListener / PACER‑derived sources) or check whether the 2015–2016 Avago/LSI assignments involved this patent in any district court case — but on the current evidence I have no confirmed CAFC or district court docket for US 6,681,358, and I will not speculate that one exists.

I'll search for litigation involving US patent 6681358 across patent litigation databases.

Let me search litigation-specific databases more directly.

Let me try a few more targeted litigation searches.

Litigation Search Results: US Patent No. 6,681,358

Bottom Line

No litigation involving U.S. Patent No. 6,681,358 was found. Searches of patent litigation resources (Unified Patents litigation portal results, Google Patents legal-events/citations data, and general web searches for the patent number in litigation contexts) returned no district court complaints, ITC Section 337 investigations, PTAB proceedings, or Federal Circuit appeals in which US 6,681,358 was asserted or challenged.

Because I could not locate any case, I cannot provide plaintiff(s), defendant(s), jurisdiction, case number, filing date, or outcome — fabricating those would be improper.

What the Searches Actually Returned

The patent number appears in the record only in non-litigation contexts:

Note: Searchers also returned a Russian telephone number "6681358" (InterTulMash, Ltd.), a municipal bond number 6681358, and JP6681358B2 — a different patent (a Japanese notification/medical-care system), which is unrelated and should not be conflated with US 6,681,358.

Contextual Notes on Why Litigation Is Unlikely / Absent

While these are observations rather than litigation records, they bear on the absence of suits:

• Subject matter: The patent covers a built-in self-test (BIST) technique for testing multiport memories at the design/manufacturing-test level (claims 1–20). Such internal test circuitry is typically not asserted offensively against end products, which reduces litigation exposure.
• Ownership chain: Original assignee LSI Logic Corp.; later LSI Corporation; then assigned to Avago Technologies General IP (Singapore) Pte. Ltd. (2015). The Google Patents page lists the current assignee as Avago Technologies International Sales Pte Ltd. No NPE or assertion entity appears in the record.
• Status: Per the Google Patents legal-status data, the patent is "Expired – Fee Related," with a lapse for failure to pay maintenance fees and a maintenance-fee reminder dated 2015-08-28, lapsing effective 2016-01-20, and a "patent discontinuation" event (expired under 37 CFR 1.362) on 2016-02-15. The anticipated expiration was 2020-02-22. A patent that lapsed in 2016 and is expired is not a likely candidate for active assertion.

Caveats and Verification Steps

• This conclusion is based on the sources returned by my searches. Unified Patents' litigation caselist and PACER/CAFC dockets were not returned directly in my result set, so I could not exhaustively query every federal docket by patent number.
• Court dockets before ~2005 are not always digitized or indexed by patent number, so it remains possible (though no evidence suggests) that an early, unreported dispute existed.
• For definitive confirmation, I recommend querying: (1) Unified Patents litigation portal (portal.unifiedpatents.com/litigation) — filter by patent number; (2) PACER / CourtListener RECAP — full-text search "6,681,358"; (3) Docket Navigator or Lex Machina; and (4) USPTO PTAB (PTAB Trials / P-TACTS) for any IPR/PGR/CBM involving the patent. To date, none of the evidence surfaced through my searches indicates any such filing.

Proceedings overview

Total AIA trial proceedings on US 6,681,358: zero (0). There is nothing to break down by status — no active trials, no claims invalidated, no claims sustained, no settlements, no institution denials. The USPTO Open Data Portal (ODP) AIA-trial feed returns no proceedings for this patent, and independent web searches for the patent number in an IPR/PGR/CBM context returned only prior-art citations (EPO search reports, RU 2408093 C2, CN 101303898 B, WO 2013/102230 A1, US 9,287,006 B2) — never a Board docket entry. Do not let anyone tell you a panel has ruled on this patent; no panel ever has.

Defensive posture bottom line: this is not a "hardened by surviving IPRs" patent, and it is also not a "claims already canceled" patent. It is an untested, un-narrowed claim set (claims 1–20) that expired on 2016-01-20 for failure to pay maintenance fees and whose status is "Expired – Fee Related." The practical consequence is that IPR estoppel, claim-cancellation leverage, and Board precedent are all irrelevant — the expiration date does the defensive work instead. (Compare the prior litigation section: no district court assertion of this patent was found either.)

No proceeding entries to enumerate

Because the canonical structured list is empty and no supplementary record surfaced, I am not creating placeholder ### IPRxxxx-xxxxx headers. Manufacturing a docket number would be the single most damaging thing I could do for a defendant relying on this memo. If a demand letter or complaint cites a PTAB outcome for US 6,681,358, ask for the proceeding number and pull it on PTAB E2E (https://ptacts.uspto.gov/ptacts/) — you will not find one.

Related-but-different proceedings (checked and excluded — do not conflate)

These are the Avago/patent-owner AIA matters that dominate search results when you query the assignee. None involves US 6,681,358. I list them so the record is not mistaken for this patent in a later search:

Note the assignee appears in these as Avago Technologies General IP (Singapore) Pte. Ltd. and Avago Technologies International Sales Pte. Ltd. — both Avago-side names. Avago is a patent owner in that chain, not a defensive aggregator; there is no Unified Patents or similar intermediary anywhere in this patent's file history per the Google Patents assignment record.

Strategic summary

Claim status across the patent: all 20 claims are UNTESTED, none CANCELED, none SUSTAINED in any AIA proceeding. Claims 1–20 (five independents — 1, 6, 8, 13, 15, 20 — with dependents) have never been construed by the Board, never been the subject of a final written decision, and never been amended. The line "the patent has survived two IPRs and is hardened" is false here; so is "claim 1 is dead." Neither narrative is available because no IPR was ever filed.

Estoppel landscape: empty. Section 315(e)(2) estoppel runs only against petitioners and privies in an instituted IPR. With no petitioner, there is no estoppel, no § 315(b) one-year bar running against any defendant from any prior service, and no § 325(d)/§ 314(a) discretionary-denial history to work around. That sounds like it would be helpful, and it would be — except for the timing problem below. Note also that the two statutory alternatives are foreclosed for this patent: PGR is unavailable because its effective filing date (2000-02-22) predates the AIA's 2013-03-16 PGR threshold, and CBM review is ineligible on the merits — the patent is directed to built-in self-test circuitry for multiport memory, not to a covered business method for a financial product or service, and the CBM program has itself sunset.

Pattern signals: none, and structural reasons why. No repeat petitioner, no patent-owner appeal activity, no aggregator chain. Two structural facts explain the absence better than any inference about the merits: (1) AIA trials did not exist until 2012-09-16, and this patent lapsed for non-payment of maintenance fees effective 2016-01-20, leaving only a ~3.4-year window in which Board review was even available against a live patent; and (2) this is design/manufacturing-test circuitry — as the litigation section observed, BIST internal-test subject matter is rarely asserted offensively against end products. Portions of the same technology family did attract IPRs (see the Avago rows above), but this particular patent never became a target.

Recommended next steps

• Lead with expiration, not with IPR history. The patent expired 2016-01-20 for failure to pay maintenance fees under 37 CFR 1.362 (maintenance-fee reminder mailed 2015-08-28; lapse for failure to pay; "patent discontinuation" event 2016-02-15); Google Patents lists it as "Expired – Fee Related," with an anticipated expiration of 2020-02-22. Any infringement theory is therefore limited to acts occurring before 2016-01-20, further capped by the 35 U.S.C. § 286 six-year damages lookback. No injunctive relief is available on an expired patent.
• If you are a defendant, demand the proceeding number. There is no FWD to link to, so I cannot quote a disposition (and will not fabricate one). If opposing counsel cites any IPR result for this patent, verify at PTAB E2E (https://ptacts.uspto.gov/ptacts/) and CourtListener (https://www.courtlistener.com/). Nothing will appear for US 6,681,358.
• Do not budget for a PTAB defense. A petition would be filed against expired claims, with all of the Board's current discretionary-denial pressures (settled expectations under § 314(a), as reflected in the Director's Dabico v. AXA Power line of decisions) cutting against institution. Validity is far more cheaply contested as a § 102/§ 103 defense in court, where the two prosecution-cited references of record — US 5,822,228 and US 5,909,204, both LSI Logic — plus the seven non-patent citations (including Hnatek 1975; Alves et al. 1993; Amin et al. 1997; Matsumura 1995; Wu et al. 1997; Yokoyama et al. 1994) are available without any § 315(e)(2) estoppel constraint.
• Flag the one live coherence issue for the litigation section: the earlier "no litigation found" conclusion and this "no PTAB activity" conclusion are consistent and mutually reinforcing — a patent that was never asserted was never IPR'd, and a patent that lapsed in 2016 had little to assert. No contradiction between the sections; the two absences corroborate each other.

I'll verify the assignment record and attempt to surface correspondents of record through targeted searches.

I have the reel/frame chain from the patent record but not correspondents. Let me make targeted attempts at correspondent data and inventor/assignee context.

Assignment Reconstruction — US Patent No. 6,681,358

Scope note / source limitation: The reel/frame chain below is taken from the USPTO assignment-recording data as reproduced in the Google Patents legal-events record for US 6,681,358. Google Patents reproduces reel/frame, conveyance type, assignor, assignee, and execution/recording dates — but not the correspondent-of-record field. My attempts to pull the correspondent (the filing attorney/agent) for these specific reel/frame entries from the USPTO Assignment Center and from secondary mirrors (PlainSite, Tianyancha) did not return that field. I therefore cannot report correspondents for any link in this chain, and I will not guess them. If the correspondent is material to the analysis (it normally is the strongest NPE tell), it must be pulled directly from the Assignment Center record per reel/frame.

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Inventors

Filing/assignment timing: Application 09/510,009 was filed 2000-02-22. The inventors' assignment was executed between 2000-02-10 and 2000-02-16 and recorded 2000-02-22 — i.e., signed within roughly one week before filing, which is the ordinary employment/obligation-assignment pattern, not a distress signal.

Departure pattern: Unclear. I found no reliable record of when (or whether) Karimi, Crosby, or Irrinki left LSI Logic after filing. There is no evidence of a coordinated inventor exodus within 12 months of filing, and no evidence against one. This signal cannot be scored either way from available data.

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Original assignee

LSI Logic Corporation, Milpitas, California (corporate address appearing on contemporaneous LSI Logic assignments: 1551 McCarthy Blvd., Milpitas, CA 95035).

• Primary business: Fabless/ASIC and standard-product semiconductors — ASSP/ASIC design services, storage controllers, RAID, Fibre Channel/SerialLink cores, set-top and consumer SoC, and embedded memory and test (BIST) IP. This patent (multiport-memory BIST) sits squarely in LSI's chip-design/test-IP activity, so the claimed subject matter is consistent with LSI's line of business rather than an acquired-IP orphan.
• Did they ship a product embodying the claims? Unclear but plausible. The disclosure is directed at on-die BIST circuitry for multiport embedded memories — a design/EDA-IP feature rather than a catalog part. LSI was a major supplier of embedded-memory and BIST IP and SoCs, so the technique was almost certainly deployed inside LSI ASIC/SoC designs, but I could not tie the specific claimed BIST unit to a named commercial product.
• Current status: No longer an independent entity. LSI Logic changed its name to LSI Corporation (corporate name change effective 2007-04-06). LSI Corporation was acquired by Avago Technologies (deal closed 2014; the patent assignment to the Avago IP entity is effective 2014-08-14). Avago subsequently acquired Broadcom Corp. and renamed the combined company Broadcom Inc. The LSI business is now part of the Broadcom group. LSI did not go through bankruptcy in this chain.

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Assignment timeline

Every entry below is a recorded USPTO assignment or security instrument. Convener types and dates are as recorded; correspondents are unavailable (see scope note).

• 2000-02-10 → 2000-02-16 (executed; individual signing dates) / recorded 2000-02-22 — Reel 010636/0643

  • Conveyance: Assignment of Assignors' Interest
  • Assignor: Karimi, Farzin; Crosby, Thompson W.; Irrinki, V. Swamy
  • Assignee: LSI Logic Corporation (Milpitas, CA)
  • Correspondent: Not available in the retrieved record. A same-reel-frame correspondent for this recording could not be pulled; cannot assess recurrence.
  • Context: Original inventor-to-employer assignment at filing.

• 2007-04-06 (effective) / recorded 2014-06-06 — Reel 033102/0270

  • Conveyance: Change of Name
  • Assignor: LSI Logic Corporation
  • Assignee: LSI Corporation
  • Correspondent: Not available in the retrieved record.
  • Context: Internal reorganization — change of name only, no change in beneficial ownership. The 7-year gap between the effective date (2007) and the recording date (2014) is itself notable: it indicates the name change was papered/recorded as part of the housekeeping leading into the Avago acquisition, not contemporaneously.

• 2014-05-06 (effective) / recorded 2014-05-08 — Reel 032856/0031

  • Conveyance: Patent Security Agreement (grant of security interest)
  • Assignor: LSI Corporation; Agere Systems LLC
  • Assignee: Deutsche Bank AG New York Branch, as Collateral Agent
  • Correspondent: Not available in the retrieved record.
  • Context: Securitization/collateral — a lien on the patent estate to secure debt. Not a title transfer; the patent remained owned by LSI/Agere pending release.

• 2014-08-14 (effective) / recorded 2015-04-03 — Reel 035390/0388

  • Conveyance: Assignment of Interest
  • Assignor: LSI Corporation
  • Assignee: Avago Technologies General IP (Singapore) Pte. Ltd.
  • Correspondent: Not available in the retrieved record. This reel/frame (035390/0388) is the same reel/frame used across the broader LSI→Avago portfolio transfer, so it is a bulk-portfolio recording, not a patent-specific deal — relevant context: this patent moved as one of many, not individually.
  • Context: Acquisition — transfer of the LSI patent portfolio to Avago's captive IP-holding entity following Avago's acquisition of LSI.

• 2016-02-01 (effective) / recorded 2016-02-02 — Reel 037684/0039

  • Conveyance: Termination and Release of Security Interest (releases Reel 032856/0031)
  • Assignor: Deutsche Bank AG New York Branch, as Collateral Agent
  • Assignee: LSI Corporation; Agere Systems LLC
  • Correspondent: Not available in the retrieved record.
  • Context: Release of the 2014 collateral lien — closing out the securitization, not a title change.

Post-record events (from USPTO legal-status data, not assignments):

• 2015-08-28 — maintenance-fee reminder mailed (4-year/8-year window).
• 2016-01-20 — lapse for failure to pay maintenance fees (effective date).
• 2016-02-15 — patent expired due to nonpayment of maintenance fees under 37 CFR 1.362; status "Expired – Fee Related."
• 2020-02-22 — anticipated statutory expiration date (never reached as an enforceable patent).

Discrepancy to flag: Google Patents labels the current assignee as "Avago Technologies International Sales Pte Ltd." The last recorded title assignment (Reel 035390/0388) runs to Avago Technologies General IP (Singapore) Pte. Ltd. — a different Avago legal entity. The "International Sales" designation is consistent with a later intra-group reorganization/renaming that does not appear as a separate reel/frame in the events retrieved, or with a Google assignee-labeling artifact. This is a genuine inconsistency in the record and should be reconciled against the Assignment Center and SEC filings before being relied on.

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Timeline diagram

timeline
    title Ownership of US 6681358
    2000 : Filed by LSI Logic Corp
         : Inventors assign to LSI Logic
    2004 : Patent issued
    2014 : Name change to LSI Corporation
         : Security deal with Deutsche Bank
    2015 : Assigned to Avago General IP
    2016 : Security interest released
         : Lapsed for nonpayment

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NPE / troll-pattern signals

1. Shell-entity transfer — Not present. Every link runs between operating-company entities: LSI Logic → LSI Corporation (name change) → Avago Technologies General IP (Singapore) Pte. Ltd. (Reel 035390/0388). Avago General IP is an IP-holding entity, but it is a captive subsidiary of the Avago/Broadcom operating group, not a licensing-only shell — it holds the group's own operating patents. There is no Delaware/Texas single-member LLC, no registered-agent address, and no licensing-only entity anywhere in the chain.

2. Known asserter in the chain — Not present. No assignee matches the listed NPE directories (Acacia, Marathon, IV, IPNav, Wi-LAN, Converso/Mosaid, Vringo, Pendrell, Round Rock, etc.). Context worth recording without over-scoring: the ultimate owner group (Avago/Broadcom) is a high-volume patent litigant — e.g., Avago/Broadcom-related actions against Tesla and the Avago/Realtek license disputes in Germany and the UPC. Those are operating-company assertions by the group's own IP arm, not NPE assertions, and none of them name US 6,681,358. So this signal stays "not present" as to NPE lists, with the operating-company litigation activity noted separately.

3. Repeat correspondent across the chain — Unclear. The correspondent-of-record field was not retrievable for any of the five reel/frame entries, so recurrence cannot be measured. Reel 035390/0388 is a shared bulk-portfolio recording (the same reel/frame is cited across many LSI→Avago assignments), which is consistent with a single portfolio-transaction correspondent, but I have no name and will not infer one.

4. Cascading transfers — Not present. Over the patent's 16-year life there is exactly one beneficial title transfer (Reel 035390/0388, 2014), plus a name change (033102/0270), one collateral grant (032856/0031) and its release (037684/0039). No chained LLC-to-LLC sequence, and no sub-24-month cascade.

5. Pre-litigation transfer — Not present. No infringement suit, ITC §337 action, or PTAB proceeding naming US 6,681,358 was found (consistent with the separate litigation analysis). With no suit, there is no transfer to time against.

6. Bankruptcy fire-sale — Not present. LSI Logic/LSI Corporation was acquired in a solvent transaction by Avago; there is no Chapter 7/11 proceeding and no bankruptcy-court sale in this chain. The 2014 security agreement (Reel 032856/0031) is ordinary secured financing, not a distressed sale.

7. Privateering — Not present. The 2014 transfer moved the patent to a wholly-owned captive IP entity inside the acquiring operating group (LSI acquired by Avago; patents parked in Avago General IP). That is standard post-merger IP consolidation, not the transfer of an operating company's patents to an independent NPE to assert on its behalf.

8. Defensive aggregator (anti-NPE) — Not present. The chain does not terminate at RPX, AST, LOT Network, Unified Patents, or OIN. It terminates inside the Avago/Broadcom group — but the patent was then allowed to lapse for nonpayment (2016-01-20) and expire (37 CFR 1.362, 2016-02-15), i.e., it was neutralized by abandonment rather than by defensive aggregation.

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Verdict

Defensive / non-asserting — by the "non-asserting" limb, with an explicit caveat.

The chain is a clean, single operating-company lineage with exactly one beneficial title transfer — Reel 035390/0388 (effective 2014-08-14), LSI Corporation → Avago Technologies General IP (Singapore) Pte. Ltd. — preceded by a pure name change (Reel 033102/0270) and one collateral grant/release pair (Reels 032856/0031 and 037684/0039). Zero of the eight NPE signals score "present," and there is no litigation involving this patent. The asset was then abandoned: maintenance-fee lapse effective 2016-01-20 and expiry under 37 CFR 1.362 on 2016-02-15.

Caveat on schema fit: the option's parenthetical defines "Defensive / non-asserting" as a chain that terminates at a defensive aggregator. This chain does not — it terminates at an operating company and then died by nonpayment. If that parenthetical is applied strictly, the technically correct score is Insufficient data for NPE purposes (no NPE-relevant records, and the correspondent field — the key NPE tell — could not be retrieved). On substance, however, there is no NPE risk: the patent was never transferred to an assertion entity and has been unenforceable since early 2016.

Verification: USPTO Patent Assignment Search — https://assignmentcenter.uspto.gov/ (search patent number 6,681,358) and https://assignment.uspto.gov/patent/index.html. Search the individual reel/frame entries above and capture the correspondent field, which this analysis could not retrieve.

I'll verify the patent record and each cited reference before analyzing.

Now let me verify the non-patent literature cited, which is where the closest prior art likely sits.

Prior-Art Analysis — US 6,681,358 B1 ("Parallel testing of a multiport memory")

Verification of the target number: US 6,681,358 B1 is confirmed on Google Patents/USPTO (https://patents.google.com/patent/US6681358/en), application US 09/510,009, filed and priority 2000‑02‑22, granted 2004‑01‑20, LSI Logic Corp. This analysis is confined to that number. Unrelated hits for the same digit string (e.g., JP 6681358 B2 — a Japanese medical-care/notification patent; a municipal bond number; a Russian telephone number) have been excluded, per the literal-identifier rule.

Legal framework: Filed 2000‑02‑22, so pre-AIA 35 U.S.C. § 102 governs (§ 102(a), (b), (e) as they existed before 2013‑03‑16). Anticipation under § 102 requires every limitation of a claim in a single reference, arranged as claimed.

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1. The complete citation set (this is a small one)

The face of the patent lists only two patent citations and seven non-patent citations. That matters: there is no large family of cited art to sift.

Every one of these dates is more than one year before the 2000‑02‑22 filing date, so each is § 102(b)-class art (printed publication / patent more than one year prior) as well as § 102(a) art if the invention date is not earlier.

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2. The two patent citations — P1 and P2

P1 — US 5,822,228 A

Full citation: Method for using built in self test to characterize input-to-output delay time of embedded cores and other integrated circuits, US 5,822,228 A, LSI Logic Corporation. App. filed 1997‑05‑27; granted 1998‑10‑13.
Description (verified): Uses a BIST generator and BIST compactor together with an external ATE clock to characterize propagation delay. The generator applies test inputs on one clock edge; the compactor latches outputs on the opposite edge, converting outputs to a signature; the delay is bracketed by shrinking the interval until an invalid signature appears. It is a delay-measurement/timing invention over embedded cores generally (including memory cores), not a memory-array fault-test invention.
§ 102 relevance: None anticipatory. It discloses no multiport memory, no concurrent multi-port operation, no address offset between ports, and no per-port segment division. It cannot meet the "offset … determined by a ratio of a number of ports to a number of address rows or address columns" limitation of claim 1, nor any of claims 2–20. At most it is § 102(a)/(b) art for the generic proposition that BIST generators and compactors exist — a background citation, likely surfaced because of shared LSI/BIST vocabulary.

P2 — US 5,909,404 A

Full citation: Refresh sampling built-in self test and repair circuit, US 5,909,404 A (inventor Schwarz per FPO), LSI Logic Corporation. App. filed 1998‑03‑27; granted 1999‑06‑01.
Description (verified): On-chip test/repair method that statistically characterizes the failure time of a sampled subset of cells, computes a statistic (mean, standard deviation, AVG−k·STDEV), derives a refresh pause time, and then runs a data-retention test; faults are mapped to redundant rows/columns (BISR). Claim 1 is a method claim to that sampling/statistics/retention sequence; claims 26–29 are directed to weak-write circuitry in a memory device.
§ 102 relevance: None anticipatory. It is a single-port data-retention/BISR invention. It does not disclose two ports tested concurrently, an inter-port address offset, complementary concurrent patterns, or segmentation by port count. No claim of US 6,681,358 is anticipated.

Intermediate conclusion on the patent citations: Both P1 and P2 are formal/background citations tied to BIST for memories. Neither is a § 102 reference against any of claims 1–20. The anticipation case, if any, lives in the NPL.

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3. The non-patent citations — where the real prior art is

N1 — Hnatek (May 1975)

Full citation: E. R. Hnatek, "4‑Kilobit Memories Present a Challenge to Testing," Computer Design, May 1975, pp. 117–125.
Description: The specification uses Hnatek for the general taxonomy of fault-detection methods and the trade-off between fault coverage and test length, and notes that the "most popular class" is March C and its variants. It is a single-port-era survey of test-pattern methodologies.
§ 102 relevance: No claim anticipated. It is cited as incorporated background, not as anticipating art; it teaches no multiport concurrency, no port-to-port offset, no per-port segmentation.

N2 — de Jonge et al., "Moving Inversions…"

Full citation: J. H. de Jonge et al., "Moving Inversions Test Pattern Is Thorough, Yet Speedy," Philips Data Systems, Apeldorn, The Netherlands (5 pp.).
Description: The classic source for moving-inversion test patterns — the read/verify/invert/write-back sequence that underlies March C, which the '358 specification describes across its six passes.
§ 102 relevance: No claim anticipated. It describes a single-port pattern-generation regimen. It supplies, at most, motivation/obviousness context for the "read, verify, invert, write back" passes recited by the '358 specification — but the claims are directed to multi-port offset/concurrency, not to moving inversions itself.

N3 — Alves et al. (1993)

Full citation: Alves et al., "A New Class of Fault Models and Test Algorithms for Dual‑Port Dynamic RAM Testing," 1993, IEEE, pp. 68–71.
Description: Proposes new fault models and test algorithms specifically for dual-port DRAMs — i.e., it recognizes that dual-port devices need fault models beyond the single-port set. (I could not retrieve the full text; this description is at the level supported by the title and by the patent's own citation, and I flag it as unverified in detail.)
§ 102 relevance: Potential § 102 candidate for the multi-port concurrency concept, but not charted. It predates the '358 filing by seven years and is dual-port-specific, so it is squarely § 102(a)/(b) art. However, on the record available I cannot confirm it discloses (i) a fixed address offset between the two ports, (ii) that offset being determined by the port-to-row/column ratio (claim 1), or (iii) the "repeat the assigned segment before leaving it" limitations (claims 6/13/20). Requires full-text review before any § 102 assertion.

N4 — Amin et al. (Sep. 1997) — the most substantive verified NPL reference

Full citation: A. A. Amin, M. Y. Osman, R. E. Abdel‑Aal, H. Al‑Muhtaseb, "New fault models and efficient BIST algorithms for dual-port memories," IEEE Trans. on CAD of Integrated Circuits and Systems, vol. 16, no. 9, pp. 987–1000, Sep. 1997. DOI 10.1109/43.658567.
Description (verified via abstract): Defines a functional model for dual-port memories; proposes architectural modifications to enhance testability, expressly to "allow multiple access of memory cells for increased test speed with minimal overhead on both silicon area and device performance"; proposes new fault models accounting for the simultaneous dual-access property; gives O(√n) test algorithms for the array and the address decoders; and covers "duplex dynamic neighborhood pattern-sensitive faults (DDNPSF)."
§ 102 relevance: This is the closest verified anticipatory candidate on the multi-port side, and it is important that it differs in mechanism:

• It achieves concurrency through word-line/column multi-access architectural modification and an O(√n) algorithm (rows/columns addressed jointly), not by dividing the memory into port-count segments and offsetting port addresses by N/P.
• Indeed, the '358 specification criticizes approaches that "require one or more modifications of the memory array circuitry" — exactly Amin's route.
• Claims 1 and 8: Amin discloses concurrent multi-port BIST access of dual-port memory (element-by-element overlap with the "concurrently apply a second test pattern" limitation), but the record does not show a fixed offset between the two ports' addresses determined by a port/row/column ratio. Likely not § 102; strong § 103 "suggested by the art" candidate if combined with an offset/segment teaching (e.g., N2/N1 or P-art).
• Claims 15/16 (word-line-based offset, adjacent word lines): Amin's multiple-access-of-cells scheme is the nearest thing to "concurrent accesses to words sharing neighboring word lines," but again the fixed offset framing is absent.

N5 — Matsumura (1995)

Full citation: T. Matsumura, "An Efficient Test Method for Embedded Multi‑Port RAM with BIST Circuitry," 1995, IEEE, pp. 62–67.
Description/source check: I could not retrieve the body text in this session; I therefore will not characterize its disclosure beyond its title and the fact that the examiner cited it. From the title it is directed to an efficient BIST test method for embedded multi-port RAM — i.e., the same problem space as the '358 patent, five years earlier.
§ 102 relevance: High-priority § 102 candidate, unverified. It is exactly the right subject matter (multi-port RAM + BIST) and predates the filing by five years, so it is § 102(a)/(b) art. Whether it discloses concurrent per-port patterns with a port-count-derived fixed offset (claim 1) or per-port segment repetition (claims 6/13/20) cannot be stated without the full paper. This is the single item I would obtain first.

N6 — Wu et al. (1997)

Full citation: Wu et al., "Built‑in Self Test for Multi‑Port RAMs," 1997, IEEE, pp. 398–403.
Description/source check: Body text not retrieved; no venue confirmed from the record returned (I will not guess the conference). Subject matter per title: BIST for multi-port RAMs.
§ 102 relevance: § 102 candidate, unverified. Same reasoning as N5: correct subject matter, dated 1997 (three years before filing). Cannot be charted on current evidence.

N7 — Yokoyama et al. (1994)

Full citation: Yokoyama et al., "Built‑in Random Testing for dual‑port RAM's," 1994, IEEE, pp. 2–6.
Description/source check: Body text not retrieved.
§ 102 relevance: Weaker § 102 candidate. "Random" testing is a different pattern regime from the deterministic offset/complementary-pattern scheme claimed; § 102 anticipation of the '358 claims is unlikely absent a showing that the random test is nonetheless applied at a port-to-port fixed offset. Keep as § 103 context only, pending review.

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4. Non-cited prior art worth adding to the record

Two references fall outside the front page but are materially closer than anything cited, and I flag them explicitly as not part of the patent's citation set:

(a) US 6,550,032 B1 — Detecting interport faults in multiport static memories (Zhao, Puri, Irrinki; LSI Logic). Filed 1999‑07‑28; granted 2003‑04‑15. Verified via Google Patents, IEEE Xplore and the patent PDF.

• Its claim 1 recites: "…concurrently with the first memory operation, performing a second memory operation through a second port, wherein the second memory operation occurs at a fixed number of cells away from the address of the first memory operation."
• That is the fixed-offset concurrent two-port operation concept, disclosed in an application filed before 2000‑02‑22 → § 102(e) (pre-AIA) prior art as of 1999‑07‑28, notwithstanding its 2003 grant date. Different inventive entity from the '358 patent (common inventor V. S. Irrinki), so the "same inventive entity" exclusion does not apply on its face.
• It does not appear to recite a port-to-row/column ratio offset (claim 1 of '358) or dividing the memory into per-port segments (claims 6, 8, 13, 20). So it is a strong § 103 reference and a partial § 102 reference, but likely not a full anticipant of any single '358 claim.
• Flag / probable cross-reference: the '358 specification states it incorporates by reference "co-pending U.S. patent application Ser. No. 09/363,697, filed Jul. 28, 1991." The 09/xxx,xxx series is inconsistent with a 1991 date, and US 6,550,032 was filed July 28, 1999 with the same assignee and a shared inventor. I infer — but cannot confirm from the record retrieved — that Ser. No. 09/363,697 is the application that issued as US 6,550,032, and that "1991" in the printed patent is an error. I am reporting this as an inference, not correcting the printed text.
• Because it appears to be both commonly owned and incorporated by reference, any § 102(e)/§ 103(c) treatment (common-ownership disqualification from obviousness combinations) deserves separate analysis; I am not asserting a conclusion on that point.

(b) US 5,796,745 A — Memory array built-in self test circuit for testing multi-port memory arrays (granted 1998‑08‑18). Listed in the "similar documents" set, not among the '358 citations. A BIST circuit expressly for multi-port memory arrays, granted ~18 months before the '358 filing → § 102(b) art. Its actual disclosure was not verified here; recommendation: obtain and chart it.

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5. Ranking and bottom line

Conclusion: of the seven references actually cited on the face of US 6,681,358, none is a clear § 102 anticipant, and the two patent citations (US 5,822,228; US 5,909,404) are pure background — neither discloses multiport concurrent testing with an inter-port address offset. The only cited references with genuine § 102 potential are the multi-port BIST NPL items (Matsumura 1995, Wu 1997, Amin 1997, Alves 1993), and of those only Amin could be substantively characterized here; it reads more like § 103 material than § 102 because its concurrency comes from memory-array architectural modification and an O(√n) multi-access algorithm rather than the claimed segmentation-plus-fixed-offset scheme. Finally, the most dangerous reference overall is almost certainly US 6,550,032 B1, which is not cited on the face of the patent yet appears to be § 102(e) art as of 1999‑07‑28 and recites, in terms, a concurrent second-port operation "at a fixed number of cells away."

Caveats I want stated plainly: (i) For N3, N5, N6, N7 and for US 5,796,745 I could not retrieve full text, so no § 102 assertion is made for them — the entries above are priority flags, not findings; (ii) the identification of Ser. No. 09/363,697 with US 6,550,032 is my inference from the filing date, series, assignee and shared inventor, not a confirmed fact; (iii) all statements about what a reference "discloses" are limited to the text I actually retrieved, and are quoted or paraphrased from that text only.

I'll ground the obviousness analysis in the actual prior-art references listed on this patent's page. Let me verify details on the key ones.

Excellent — these searches surfaced the exact prior art I need. Let me pin down two more references.

Obviousness Analysis — U.S. Patent No. 6,681,358 B1

Under 35 U.S.C. § 103 (pre‑AIA), as applied to a Feb. 22, 2000 filing

Analysis uses the Prior Art section of the US6681358 Google Patents page (Citations, Non‑Patent Citations, Similar Documents) as the primary record, supplemented where noted. All dates below are verified as indicated.

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0. Bottom line up front

Every independent claim of US 6,681,358 is vulnerable to a § 103 rejection, and several are close to § 102 anticipation by a single reference. The core idea — running a conventional single‑port March BIST through two (or more) ports simultaneously, with the second port's addresses displaced by a fixed, hardware‑trivial offset (an inverted address bit) and its data inverted, so that adjacent word lines/bit lines are exercised concurrently with no added test time — was squarely in the art by 1997–1999. The most damaging references are:

The strongest claim for the patentee is claim 6 (and its twins, claims 13 and 20): the requirement that the address generator walk the same assigned segment twice before leaving it is a sequencing detail that the page's prior art does not squarely show. I flag that honestly below, along with the § 103(c) problem that may disqualify the one reference that matches it best.

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1. Legal framework and the hypothetical person of ordinary skill

Governing law. The application was filed 2000‑02‑22, so pre‑AIA §§ 102/103 govern (AIA first‑inventor‑to‑file provisions took effect 2013‑03‑16). Obviousness is measured from the effective filing date (2000‑02‑22) using the Graham v. John Deere, 383 U.S. 1 (1966) factors: scope/content of the prior art, differences between the art and the claims, the level of ordinary skill, and objective indicia. Under KSR Int'l v. Teleflex, 550 U.S. 398 (2007), a combination of known elements is obvious where there was an apparent reason to combine, and where the art identifies a "finite number of identified, predictable solutions." MPEP § 2143 lists the acceptable rationales: combining prior art elements according to known methods to yield predictable results; simple substitution of one known element for another; use of a known technique to improve a similar device in the same way; and "obvious to try."

The person of ordinary skill ("POSITA"). A hypothetical POSITA here holds a B.S. (or M.S.) in electrical/computer engineering with roughly 2–5 years of experience in embedded‑memory design and manufacturing test. Such a person would:

• be familiar with March algorithms and their variants (March C, March C−, Smarch, March LR), as compiled in van de Goor, Testing Semiconductor Memories: Theory and Practice (1991) — cited inside US 6,070,256 and effectively the field's standard text;
• understand the multiport‑memory fault model, including inter‑port bit‑line and word‑line shorts ("WSA"/"WSD" shorts), and know that such shorts are most probable within the same or adjacent row/column (stated verbatim in US 6,070,256's Background, quoting its own fault‑model analysis);
• know that test time dominates memory manufacturing cost, so any modification that adds coupling coverage without adding test cycles is per se desirable.

That last point matters: the patent's own stated advantage (spec: "test time … is the same as that required by the original BIST") is exactly the design objective headline in Wu & Gupta ("does not impose any extra test time") and in Matsumura ("about the same pattern length as the standard functional test patterns for single‑port RAMs"). The claimed benefit was not merely predictable — it was the articulated goal of the field.

Reference dates (pre‑AIA § 102).

Observation on the record. The examiner cited only two U.S. patents — both LSI's own, neither about multiport inter‑port testing. Meanwhile US 5,796,745, the Wu & Gupta paper, US 6,070,256, and Matsumura all sat in the same classification space (G11C29/xx, G01R31/318x) and none appears on the "Citations" list. That is a prosecution‑record gap, not a validity shield — § 282 does not privilege thin examination.

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2. Key claim terms — construction that drives the analysis

Note the internal tension already flagged in the summary section: claim 1's "ratio" language is not described anywhere in the specification, which instead describes segments of size N/P and offsets "correspond[ing] to the location of the memory segments that the ports are assigned." That is a potential § 112(a) written‑description/support issue for claim 1, and it is also evidence that the "ratio" phrase was added without a corresponding inventive concept.

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3. Combination A — Claims 1–5, 7–12, 14 (the "offset + complementary data + comparator" claims)

Primary: US 5,796,745 in view of Wu & Gupta (ATS '97) / US 6,070,256, further in view of Matsumura.

A1. What US 5,796,745 alone teaches. Claim 1 of US 5,796,745 recites an on‑chip BIST for a memory array "having multiple ports," comprising a data generator, R/W controller, address counter, and frequency controller, "wherein each of said multiple ports simultaneously receive one said unique data, one said unique read/write control and one said address." Claims 3 and 11 recite that "said addresses … are for adjacent memory addresses to test cell‑to‑cell, bitline and wordline coupling sensitivities." The specification adds that the address counter's "programmable latches … can be set … to invert various port (P1 to PN) address bits. For example, the least significant bit of the word line address on Port 1 can be inverted … Thus, wordline‑to‑wordline sensitivities may be tested. If the latches are programmed in this manner, then Port 1 can output a different address than Ports 2 through N." Compare circuitry generates PASS/FAIL#.

That single reference discloses nearly all of independent claims 1 and 8 except the "ratio" phrasing and the segmentation/sequencing detail: multiport memory, BIST unit, concurrent per‑port patterns, per‑port fixed address offsets, address offsets chosen to hit adjacent/coupled rows and columns.

A2. What Wu & Gupta / US 6,070,256 add — and why the combination is compelling. The Wu & Gupta paper performs "a conventional single‑port test such as MARCH or SMARCH on one port … and simultaneously performs an inter‑port test on all other ports," with "no extra test time" and "only a few gates" added. The implementation detail is the crux:

"For the port under the inter‑port test, its (LSB+1) bit of the row address, A_row[1], is inverted, which is equivalent to performing [row + (−1)^⌊row/2⌋·2]. … This implementation requires the addition of only 2 XOR gates, 2 AND gates and 2 inverters to a conventional MARCH BIST controller … In general, the costs include only 1 XOR gate, 1 AND gate and 1 inverter per port."

US 6,070,256 (Nortel, filed 1998‑02‑19) is the patent counterpart: claim 1 recites "inverting the second least significant bit of the row address signal of the address signal provided to the selected ports," and claims 2–3 recite address‑modifier means doing the same. Its stated purposes are detection of "bit line and word line shorts across ports" that are "most likely [in] the same and adjacent columns" / "the same row and between adjacent rows."

Thus Wu/‌US 6,070,256 supply precisely what claim 1 calls the offset "causing read and write operations of the first port and second port to concurrently be directed to memory words that share neighboring bit lines" (claim 2/9) and what claim 15 calls "sharing neighboring word lines." A single inverter (or XOR) on one address bit is a fixed amount, and it is hard‑wired — the definition of an offset "determined by" memory geometry rather than computed per address.

A3. Where the claim‑1 "ratio" hook is met. For claim 1's specific limitation that the offset be "determined by a ratio of a number of ports to a number of address rows or address columns," the cleanest disclosure is US 6,510,530 (Nortel, filed 1999‑09‑23): the CsRAM is "virtually partitioned into k sections, the sections being tested simultaneously from different ports with identical and complementary test data," and claim 12 recites that "the most significant bit of the row address is used as a memory section select signal" — i.e., the inter‑port address displacement equals the section size = (row address space)/(number of sections ≈ number of ports). That is literally an offset fixed by the ratio of ports to rows. Claim 17 adds "an address inverter for each said address connection for said second port," claim 2/18 adds complementary data via an input data inverter, and claim 1 adds the per‑port comparison/declare‑fault logic (the claim 7/14/19 comparator).

A4. Motivation to combine (MPEP § 2143 rationales).

1. Same field, same problem, same solution family. All three references are memory‑BIST art addressing multiport inter‑port coupling/shorts; US 5,796,745 and US 6,510,530 even share the same architecture (programmable pattern/address generation + per‑port inverters + comparator). KSR: "familiar elements … according to known methods."
2. Express design objective. Wu & Gupta's title‑level promise ("detects both conventional single‑port faults and inter‑port shorts") with "no extra test time" supplies an explicit motivation to bolt that address‑inversion trick onto the programmable per‑port address generator of US 5,796,745. The patent's own summary touts the identical benefit — evidence that the goal was known, not discovered.
3. Predictable result. Inverting one address bit to move a port's access into the next‑over row/column, and inverting the data on that port, produces a predictable excitation of adjacent‑line shorts. KSR: "a finite number of identified, predictable solutions."
4. Degrees of freedom are trivial. Both references implement the offset with a handful of gates (1 XOR + 1 AND + 1 inverter per port; US 5,796,745 programmable latches), so there is no teaching away based on cost, and no array modification — the very objection the patent levels at "other methods" in its Background.

A5. Anticipation note. US 6,070,256/Wu & Gupta alone appear to disclose claims 2, 3, 7, 10, 11, 14 (and largely claims 8, 9, 12) — concurrent offset patterns, adjacent‑line coupling coverage, per‑port comparison. Where a reference anticipates, a fortiori it renders the claim obvious (the "epitome of obviousness" principle).

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4. Combination B — Claims 6 and 13 (the segmented/repeat‑segment claims)

Claims 6 and 13 require that the address generator "again consecutively address via the first port each memory location in the segment assigned the first port before addressing via the first port any memory location outside the first segment" — the specification's "each‑port‑does‑one‑segment‑at‑a‑time" embodiment (six March passes over 0 … (N/P)−1, then six more over N/P … (2N/P)−1, etc.).

Proposed rejection: Combination A + Hnatek / de Jonge (March C) + US 6,510,530.

• US 6,510,530 teaches the necessary partitioning into per‑port sections with simultaneous testing, and even the same physical mechanism (MSB of row address = section select). Once the memory is partitioned into per‑port sections, running the full March sequence over a section and then re‑running it over the next section is one of only two natural orderings (segment‑at‑a‑time, or wrap‑around through the whole space). KSR forecloses the argument that choosing between two known orderings is inventive.
• Hnatek and de Jonge et al. (both in the page's Non‑Patent Citations) supply the March sequence itself, including repeated passes with read‑verify‑then‑invert‑and‑write‑back. The patent's own specification concedes the redundancy ("the initialization pass could potentially be eliminated after the first segment is tested, so that only 5 passes are conducted for subsequent segment tests") — an admission that the segment loop is a test‑sequencing convenience, not a technical advance.
• Matsumura supplies the "repeat the whole algorithm per sub‑region" intuition in the multi‑port context (its RARCAS walks the full column address space per row).

Candid assessment: this is the patent's best defense. The page's prior art shows partitioning, concurrent offset testing, and full‑space March marches — but not an express disclosure of "exhaust the segment, then repeat the identical full BIST on the same segment before moving on." Expect a patentee to argue that the prior art, if anything, teaches marching the whole address space (US 5,796,745, Wu & Gupta, Matsumura), and that the claimed double‑pass of a single segment is a departure. The counter is that (i) the claim is a pure sequencing/loop‑boundary change with no asserted (or plausible) new fault‑coverage mechanism, (ii) the specification describes it as one of several "numerous embodiments" of the same idea, and (iii) US 6,550,032 (if available) does exactly this. A rejection here would likely need a declaration or a secondary reference keyed to "test each section independently, then advance."

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5. Combination C — Claims 15–19 (the "neighboring word lines" claims)

Primary: Matsumura in view of US 5,796,745 (and Wu & Gupta / US 6,070,256).

Matsumura expressly describes the mechanism claim 15 targets: "Two word lines with the same row addresses are selected and then the left (or right) port's column address is incremented, while the right (or left) port's column address is simultaneously decremented," with row/column sequencing (RARCAS) chosen so that "the proposed test pattern can … detect some other faults peculiar to multi‑port RAM, such as bridging faults between both ports' word lines with the same row address," at ≈12N versus 10N for a single‑port March.

US 5,796,745 claim 11 ("adjacent addresses … to test cell‑to‑cell, bitline, and wordline coupling sensitivities") and its programmable word‑line‑address‑bit inversion (for "wordline‑to‑wordline sensitivities") independently supply the offset that lands the ports on coupled word lines. US 6,070,256 adds the recognition that "the most likely inter‑port word line shorts are word line shorts within the same row and between adjacent rows."

The patent's own specification attributes the value of this arrangement to detecting "'weak' grounding" and, "[a]s a more severe test … having all ports accessing different words in the same row" — a configuration Matsumura's RARCAS produces essentially verbatim (same row address, both word lines driven; different column addresses). Motivation: same fault model (inter‑port word‑line bridging), same figure of merit (no added test time), same field. Claims 16–19 (complementary data; adjacent word lines; consecutive addressing via port 1; comparator) fall with the same combination plus US 6,510,530 (complementary data inverter; comparison/declare‑fault) and US 5,796,745 (address counter; compare circuitry).

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6. Combination D — Claim 20 (column‑group variant)

Claim 20 is the column‑group analogue of claim 6. Combination: US 5,796,745 + US 6,510,530 + Matsumura, with the column‑group partition supported by US 6,510,530's claim 14 (each port's address mux provides "either (r−1) row addresses and c column addresses, or r row addresses and (c−1) column addresses" — i.e., a section may be carved out of either the row or the column dimensions). The patent itself says the column‑group embodiment is for "all ports accessing different words in the same row" — exactly what Matsumura's same‑row‑address construct provides. The same candid caveat from § 4 applies to the "repeat the column group" limitation.

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7. US 6,550,032 — the reference that fits the patent's own best embodiment, and why it may be unavailable

The specification's incorporated‑by‑reference material is "co‑pending U.S. patent application Ser. No. 09/363,697, filed Jul. 28, 1991" (the internal inconsistency flagged in the summary section). The record now explains it: US 6,550,032 B1, "Detecting interport faults in multiport static memories," filed 1999‑07‑28, granted 2003‑04‑15, assignee LSI Logic, inventors Zhao, Puri, Irinki [sic] and Lombardi (application number and July‑28 date match; the patent's "1991" is evidently a typographical error for "1999"). It appears in the page's Similar Documents list.

Its content is directly on point for claims 6, 13 and 20: while a single‑port March C runs on the test port, concurrent accesses are performed on the other ports "two cells behind"/"two cells ahead" of the test address (a fixed offset), "requiring only as many memory operations as the associated single port test, thus keeping test time to a minimum," with a test circuit comprising "an address register, a data register, a comparator … and control logic" and address/data multiplexers.

Two serious caveats:

1. § 103(c) common ownership. Because US 6,550,032 and US 6,681,358 were both owned by LSI Logic at the time the invention was made, US 6,550,032 in its capacity as § 102(e) prior art is disqualified for use in a § 103 obviousness rejection under pre‑AIA 35 U.S.C. § 103(c)(1). A petitioner relying on it must either attack claims 6/13/20 under § 102 (where 103(c) does not apply) or remove it from the combination. This is the single biggest legal impediment to the cleanest obviousness case here.
2. Incorporation by reference cuts the other way too. A reference incorporated into the patent's own specification is part of the patent's disclosure; whether and how it can simultaneously serve as § 102(e) art against that same patent is contestable. Treat this as an open question, not a settled point.

Practical consequence: the strongest available combination for claims 6/13/20 is the one in § 4 above (US 5,796,745 + US 6,510,530 + March‑algorithm NPL), not a rejection built on US 6,550,032.

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8. Why the patent's own arguments against the prior art do not save it

The specification distinguishes three prior techniques. None of those distinctions reach the references above:

No teaching away. At most, the specification criticizes one specific algorithm (ascending/descending MARCH) for a specific deficiency at a specific topology. KSR: a critique that "merely expresses a general preference" or identifies a defect in one embodiment does not teach away from the general approach, and here the defect the applicant identified is cured by the very references at issue.

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9. Objective indicia (Graham factor 4)

The evidentiary record contains no evidence of nexus‑bearing secondary considerations:

• Commercial success — none shown; the patent lapsed for nonpayment of maintenance fees (reminder 2015‑08‑28; lapse effective 2016‑01‑20; "expired due to nonpayment … under 37 CFR 1.362," 2016‑02‑15), which is at least consistent with low commercial value, though not dispositive.
• Long‑felt but unsolved need / failure of others — negated by the 1991–1999 arc of prior art (Alves 1993; Yokoyama 1994; Matsumura 1995; US 5,796,745 1996/1998; Amin 1997; Wu & Gupta 1997; US 6,070,256 1998). The field was solving this problem continuously and successfully.
• Copying / industry praise / licensing — none in the record; the patent was apparently never asserted (the litigation section records no district court, ITC, PTAB or Federal Circuit proceeding). A never‑asserted, fee‑lapsed patent in a design‑for‑test space generates little weight in the secondary‑consideration calculus.
• Unexpected results — the only asserted advantage (same test time, added inter‑port coverage) is the predicted result stated in Wu & Gupta and Matsumura in advance of the filing date.

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10. Claim‑by‑claim conclusion

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11. Caveats, confidence, and what would change the answer

Confidence levels (explicit, per my operating rules):

• High confidence in the content of US 5,796,745 (claim language and address‑bit‑inversion passage verified from the patent text), Wu & Gupta ATS '97 (abstract and implementation passage verified, including the A_row[1] inversion and "no extra test time"), US 6,070,256 (claims verified; filed 1998‑02‑19, granted 2000‑05‑30), Matsumura MTDT 1995 (RARCAS passage and word‑line‑bridging coverage verified), and US 6,510,530 (claims verified; filed 1999‑09‑23).
• Moderate confidence in my characterization of Alves et al. (1993), Yokoyama et al. (1994) and Amin et al. (1997): I have their titles, venues and page ranges from the page's Non‑Patent Citations and secondary databases, but I did not retrieve their full texts, so I have not quoted them and have not relied on them to supply any limitation. They are useful chiefly as evidence of the crowded state of the art (secondary‑considerations rebuttal), not as primary references.
• Verified as to bibliographic data only: US 5,822,228 and US 5,909,404 are the only references on the patent's face; neither is multiport‑interport art, so neither is a § 103 vehicle here.
• Inference, flagged: that "Ser. No. 09/363,697, filed Jul. 28, 1991" in the specification corresponds to US 6,550,032 (application and July‑28 filing date match; the year appears to be a typographical error). I am treating this as a strongly supported inference, not a certainty.

Assumptions that, if wrong, change the analysis:

1. Effective filing date = 2000‑02‑22. No earlier priority is claimed on the face of the patent. If an undisclosed earlier priority existed, US 6,510,530 (1999‑09‑23) and US 6,550,032 (1999‑07‑28) could drop out as § 102(e) art, weakening the claim‑1 "ratio" mapping (though the 102(b) NPL — Wu & Gupta, Matsumura — would be unaffected).
2. Common ownership of US 6,550,032 and US 6,681,358 at the time of invention, which triggers the pre‑AIA § 103(c)(1) disqualification. If ownership were not common at the relevant time, US 6,550,032 becomes the single most dangerous reference against claims 6, 13 and 20.
3. Claim construction of "determined by a ratio of a number of ports to a number of address rows or address columns." If that phrase is construed narrowly to require an explicit arithmetic ratio (excluding a fixed two‑address or one‑bit inversion), claim 1's invalidity turns on US 6,510,530; if construed as any offset fixed by memory geometry, claim 1 falls to US 5,796,745 + Wu & Gupta alone.

One cross‑reference contradiction to flag explicitly. The earlier summary section noted the specification's cite to "Ser. No. 09/363,697, filed Jul. 28, 1991" as an intra‑document inconsistency and reported it without correction. The search results now permit a probable resolution — that application number and date correspond to US 6,550,032, filed 1999‑07‑28 — so the "1991" is almost certainly a typographical error for "1999." I have left the patent text quoted verbatim and have not altered it, consistent with the instruction to interpret identifiers literally.

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If you want to push this further, the two highest‑value next steps are (a) pull the full texts of Alves 1993, Yokoyama 1994 and Amin 1997 to test whether any of them expressly describes a fixed address offset between ports that is a function of the number of ports (which would close the claim 1 gap without needing US 6,510,530), and (b) confirm the ownership history of US 6,550,032 and US 09/510,009 as of early 2000, since that single fact determines whether the patent's best‑supported embodiment (claims 6/13/20) can be reached at all in a § 103 challenge.