US 5870087

I'll search for this specific patent and check for any recent CAFC docket activity.

Let me get the actual claim text and check for any 2026 CAFC activity specifically involving this patent.

Let me do one more targeted check for any 2026 appellate activity.

US Patent 5,870,087 — Verification Summary

Search scope note: I checked the Google Patents record (the authoritative full text supplied), the USPTO PTAB/PTACTS filings, Unified Patents' litigation database, the Stanford NPE Litigation Database, and general web search. I was not able to query the CAFC's docket system directly; my 2026 appellate check is based on open-web search only and is therefore not exhaustive. I found no CAFC 2026 docket involving U.S. 5,870,087 (details in the litigation section).

I did not substitute any similar patent number; everything below is tied to 5,870,087 / App. 08/748,269.

Bibliographic Data

Minor discrepancy flagged (not auto-corrected): the patent's own front page states Filed Nov. 13, 1996 and Date of Patent Feb. 9, 1999; the Unified Patents portal lists priority date 1996-11-12 and grant date 1999-02-08. These appear to be time-zone/annotation artifacts. I use the patent text figures.

Abstract (as issued)

An MPEG decoder system and method for video decoding/decompression including a unified memory for multiple functions. The system includes transport logic, a system controller, and MPEG decoder logic, with a single unified memory (preferably 16 Mbit) storing code and data for all three functions. The MPEG decoder logic includes a memory controller coupled to the unified memory; each of the transport logic, system controller, and MPEG decoder accesses that memory through the memory controller. Various frame-memory-saving schemes (compression, dynamic segment allocation) are used; in one embodiment the memory need not store reconstructed frame data during B-frame reconstruction, freeing memory space for transport and system-controller functions.

Independent Claims — Plain Language

Claim 1 — MPEG decoder system (apparatus). A system built around a single memory shared for transport, decode and system-controller functions, comprising:

• a channel receiver for receiving an MPEG encoded stream;
• transport logic coupled to the receiver that demultiplexes one or more multimedia data streams out of the encoded stream;
• a system controller coupled to the transport logic that controls operations within the decoder system;
• an MPEG decoder that receives the demultiplexed stream(s) and performs MPEG decoding;
• a memory coupled to the MPEG decoder and used by it during decoding, where that same memory (a) stores code and data usable by the system controller so it can perform control functions, and (b) is used by the transport logic for demultiplexing;
• plus three "operability" limitations: the MPEG decoder can access the memory during decoding, the transport logic can store and retrieve data in it during demultiplexing, and the system controller can retrieve code and data from it during system-control functions.

Gist: one physical memory, three consumers (transport, MPEG decode, CPU), all through a shared path — as opposed to the prior art's separate transport/controller memory and frame-store memory.

Claim 10 — Method (independent). The method counterpart: performing video decoding in an MPEG decoder system having a single memory for transport, decode and system-controller functions, comprising: receiving an MPEG encoded stream; demultiplexing multimedia data stream(s) using a first unified memory; performing MPEG decoding using that same unified memory; and a system controller controlling system operations by accessing code and data from that unified memory — wherein all three operations each use the one unified memory.

Claim 16 — Video decoder system (independent). A genus-level version of claim 1 using "video" rather than "MPEG" terminology: a single memory for transport, decode and system-controller functions, comprising a channel receiver for an encoded video stream; transport logic demultiplexing multimedia data stream(s); a system controller; a video decoder performing video decoding on the demultiplexed streams; and a memory coupled to the video decoder that stores code and data usable by the video decoder during decoding and usable by the system controller to perform control functions, is used by the transport logic for demultiplexing, and is accessible by all three during their respective operations.

Claim 7 is a dependent claim (it was treated as dependent on claim 1 in the PTAB petitions), notwithstanding that it was grouped with claims 1 and 16 in the "independent claims" heading of one petition's ground. Independent claims are therefore 1, 10, and 16.

Representative dependent-claim themes: audio buffers in the unified memory (claim 9 bracket); the memory controller storing compressed data in the memory to reduce storage requirements (claim 13); dynamic allocation of memory segments (claim 14); and memory size constraints such as a 16 Mbit memory / not exceeding a stated megabit size (claims 15/20 bracket).

Litigation, PTAB and CAFC Status

• ITC: Investigation 337-TA-837 ("Audiovisual Components and Products Containing the Same," LSI Corp./Agere Systems as complainants).
• District courts (selected): LSI v. Vizio (8:10-cv-01602, C.D. Cal. 2010); Barnes & Noble v. LSI (3:11-cv-02709, N.D. Cal./E.D. Cal. 2011); LSI v. Funai (2:12-cv-02047, C.D. Cal.); LSI v. Funai (2:15-cv-00239, E.D. Tex.); Avago v. Acer (3:15-cv-05427) and Avago v. ASUSTeK (3:15-cv-04525, 3:16-cv-00451, N.D. Cal.); Broadcom v. Sony (8:16-cv-01052) and Broadcom v. Amazon.com (8:16-cv-01774, C.D. Cal.); and Funai Elec. Co. v. LSI Corp., 5:16-cv-01210 (N.D. Cal.), where Judge Freeman issued a Markman order construing "single memory," "transport logic," "system controller," "channel receiver," and "coupled to" (notably holding "single memory"/"first unified memory" means "memory functioning as a unit," not necessarily one physical device).
• § 101: On April 15, 2016, the N.D. Cal. denied a motion to dismiss, finding the '087 claims patent-eligible at Alice step one (purpose = "decompress digital video using a single memory," with no genuine preemption risk).
• PTAB: Three IPRs, all terminated by settlement — IPR2016-00646 (ASUS et al., filed 2016-02-22, instituted 2016-08-22, terminated 2017-05-16), IPR2017-00520 (Sony), and IPR2017-01816. Grounds relied on Fujii (US 5,898,695), Maturi (US 5,559,999), Bheda (US 6,002,441), Lam (US 5,960,464), and Yao's "Unified Memory Architecture Cuts PC Cost." Because they settled, no final written decision on validity issued.
• CAFC: The Google Patents family page lists two Federal Circuit filings historically associated with this family — 14-1410 and 17-1491. For calendar year 2026, I found no CAFC docket or decision involving U.S. 5,870,087. Note that a 2026 appeal, Broadcom Corporation v. Netflix, Inc., No. 25-1740, does list Avago Technologies International Sales Pte. Ltd. (the '087 current assignee) as appellant, but nothing in the retrieved record ties that appeal to the '087 patent, and I will not infer that it does. This is consistent with the patent having expired in November 2016.

Uncertainty / Caveats

• The exact wording of claim 16 above is reconstructed from parallel-language (Chinese/Japanese) family versions; treat it as a faithful paraphrase rather than a verbatim quote. The wording of claim 1 and claim 10 is confirmed verbatim from IPR petitions and briefing.
• Dependent-claim-to-independent-claim mapping at the margins (e.g., whether the 16 Mbit limitation sits in claim 15 or claim 20 in the U.S. claim set) is uncertain because the sources I retrieved that show those numbers are translations; I have flagged them as "bracket" rather than asserting a specific claim number.
• My conclusion of no 2026 CAFC activity is based on open-web search, not a direct CAFC docket query; treat it as "not found" rather than "confirmed absent."

I'll search targeted sources for litigation involving US 5,870,087 specifically.

Let me fill in a few specific gaps: the N.D. Cal. cases, the CAFC appeals, and any recent 2026 activity.

Litigation Involving U.S. Patent No. 5,870,087

Search scope / caveat first: I ran targeted queries against the Unified Patents portal (patent page, PTAB case pages, and litigation data), the Darts-IP/Unified family-litigation links on the Google Patents record, the Stanford NPE Litigation Database, IPR petitions filed by Sony, ASUS and Amazon (which contain mandatory-notice "related matters" lists), and the ITC / N.D. Cal. / C.D. Cal. records surfaced in those documents. I was not able to query PACER or the CAFC docket directly (my tool calls were capped before I could complete those lookups), so the CAFC and any very recent 2026 docket entries are "not found," not "verified absent." Everything below is tied to 5,870,087 / App. 08/748,269; I did not substitute any similar number.

Two useful cross-checks came back consistent: the Unified Patents patent page (https://portal.unifiedpatents.com/patents/patent/5870087) and the Stanford NPE Litigation Database entry (https://npe.law.stanford.edu/patent/5870087) both key on 5870087, and the Sony IPR petition's mandatory-notices table (IPR2017-00520) enumerates the district-court matters.

A. District Court Litigation

Note on the '087 patent's status in these cases: it expired on its 20-year term (anticipated expiration 2016-11-13). Several of the 2015–2016 actions overlapped with the term's end, which is why the '087 merits dropped out of most of them.

B. ITC Investigation

Contemporaneous related proceeding: Realtek v. LSI (N.D. Cal.) — a RAND/breach counterclaim in which Judge Ronald M. Whyte ruled (Feb. 27, 2014) that LSI breached IEEE-SA RAND obligations; royalty reduced (reported 5% → 0.19%) and ~$3.8M fees assessed against LSI. This is a related dispute over LSI/Agere standard-essential-patent conduct arising from the 337-TA-837 campaign; the '087 patent was not one of the RAND-pled patents in that counterclaim (the Chinese-language case summary describes the RAND patents as the Wi-Fi/'958/'867 family), so I list it as context rather than a strict '087 case.

C. PTAB (Inter Partes Review)

Prior art asserted across these petitions: Fujii (US 5,898,695), Maturi (US 5,559,999), Bheda (US 6,002,441), Lam (US 5,960,464), Cloutier (US 5,847,771), and Yao's "Unified Memory Architecture Cuts PC Cost" (Microprocessor Report, 1995), plus the VESA UMA press release (1996). No claim was ever cancelled — every IPR ended without a final written decision.

D. Court of Appeals for the Federal Circuit

• The Google Patents family-litigation list for US5870087 shows two Federal Circuit filings: 14-1410 and 17-1491 (https://portal.unifiedpatents.com/litigation/Court%20of%20Appeals%20for%20the%20Federal%20Circuit/case/14-1410 and .../case/17-1491). I could not retrieve the underlying decisions or confirm which '087-related judgment each appeal arose from (14-1410 is plausibly an appeal out of the 2014 N.D. Cal./ITC activity and 17-1491 out of the 2016–2017 N.D. Cal. cases, but I will not assert that — treat the linkage as unverified).
• No CAFC filing specifically identifying U.S. 5,870,087 in 2026 was found. This is consistent with the patent having expired Nov. 13, 2016.

E. Bottom line

Yes — there is substantial known litigation involving US 5,870,087, primarily as part of LSI/Agere's (later Avago's) licensing campaign, and secondarily as part of Broadcom's 2016 campaign against Sony and Amazon:

• One ITC investigation (337-TA-837) — terminated 2014 with the '087 merits mooted by settlement and expiration.
• Eleven district-court matters (table A) across C.D. Cal., N.D. Cal., and E.D. Tex.
• Three PTAB IPRs — all resolved without a merits decision (settlements/dismissal).
• Two historical CAFC filings in the family list; no 2026 CAFC activity found.

Where I am uncertain (flagged, not fabricated): (1) the specific outcome of most individual district-court cases (settlements/dismissals are common in this campaign and public dockets were not fully retrievable here); (2) the subject matter of CAFC 14-1410 and 17-1491; (3) any litigation filed in 2026, since I could not run a live PACER/CourtListener docket query before reaching my tool limit. If you need those confirmed, the next step would be a direct PACER/RECAP docket pull and a CAFC CM/ECF docket search on 5,870,087 and on the assignees (Avago Technologies International Sales Pte. Ltd. / Broadcom).

I'll verify the PTAB proceedings against the structured ingest block, which reports no AIA trials — a direct conflict with the IPRs documented in the prior section. Let me check.

Good — the structured ingest block conflicts with the record. Let me pull the claim-level trial details.

Let me pin down the institution decision claim set and the other two proceedings' dispositions.

⚠️ Ingest conflict — flagged, not silently resolved

The structured "PTAB proceedings on file" block states: "The USPTO ODP API returns no AIA trial proceedings for this patent as of the most recent ingest." That is wrong. The open-web record shows three IPRs on 5,870,087, all filed 2016–2017 and all resolved. The ingest is evidently stale or under-indexed for this patent's trial history. I have built this section from the retrieved PTAB filings and docket records and flag the discrepancy rather than defaulting to "no PTAB activity."

Proceedings overview

Three AIA trials total, all Inter Partes Reviews, and none of them produced a merits decision: 0 active, 0 with claims canceled, 0 with claims sustained, 3 settled/dismissed before any Final Written Decision (one after institution, one pre-institution, one stage unverified) — so a defendant today faces a patent that has been litigated to institution once and then bought off three times, meaning there is no estoppel shield, no FWD to cite, and no adjudicated invalidity to lean on.

Practical bottom line: 5,870,087 is not a "hardened by PTAB" patent and it is not a "claims already canceled" patent. It is an un-adjudicated, expired patent whose validity challenges were all short-circuited by settlement. Every claim — 1, 2, 3, 5, 7–11, 13, 16, etc. — remains legally intact and untested at the Board.

Why IPR-only: the application was filed 1996-11-13 (pre-AIA), so PGR is unavailable, and the patent is not a "covered business method" patent, so CBM is unavailable. IPR was the only door, and it has now closed with expiration.

IPR2016-00646 — ASUSTeK Computer, Inc. & ASUS Computer International v. Avago Technologies General IP (Singapore) Pte. Ltd.

• Type: Inter Partes Review
• Filed: 2016-02-22 (notice of filing date accorded 2016-02-24; Patent Owner Preliminary Response filed 2016-05-24)
• Status: Settlement (verbatim from the structured litigation record) — i.e., instituted, briefed through Patent Owner Response, then terminated on joint motion before oral hearing
• Judge panel: Not recovered. Patent Owner filings in this case are captioned "Before PATRICK E. …"; I could not retrieve the full panel roster and will not guess the surname or the other APJs.
• Petition grounds: Challenged claims were argued unpatentable under 35 U.S.C. § 103(a). The public record shows the petition relied on, at minimum, Fujii (U.S. 5,898,695) and Lam (U.S. 5,960,464) as primary references (Petitioner Ex. 1004 = U.S. 5,960,464; Ex. 1005 = U.S. 5,898,695; Ex. 1006 = U.S. 5,847,771; Ex. 1003 = Kramer Declaration), with secondary art including the VUMA Hardware Spec (Ex. 1010) and the T-REC-H.222.0 MPEG-2 systems text (Ex. 1007). Patent Owner's Response organized its rebuttal around § 103(a) over Fujii in view of further art, addressing claims 1, 5, 7–11, and 16. I could not verify the exact claim-by-claim ground mapping — treat it as approximate.
• Institution decision: Instituted 2016-08-22 (Decision – Institution of Inter Partes Review, Paper 11; Scheduling Order, Paper 12). Per the recited history in a later Avago-family petition, the Board instituted on claims including 1, 7, 10, and 11 (and at least one more — the passage is truncated in retrieval). I will not state the full instituted claim set as verified.
• Final Written Decision: None. No FWD ever issued. The joint motion states expressly that the Board "has not yet conducted an oral hearing or otherwise resolved the merits of the Petition." Any statement that claims were canceled or sustained in this IPR would be false.
• Settlement / termination: Settlement and Patent License Agreement executed 2017-05-12; joint motion to terminate under 35 U.S.C. § 317(a) and 37 C.F.R. § 42.74 filed 2017-05-16 (Board authorized by telephone 2017-05-15); termination decision (Paper 26) 2017-05-16. The agreement resolves all disputes on the '087 patent across the district court, the Federal Circuit, and the PTAB, and was filed as confidential Ex. 2007 under § 317(b) / 37 C.F.R. § 42.74(c) — terms are not public. Termination landed roughly three months before the statutory FWD deadline (institution + 1 year ≈ 2017-08-22).
• Appeal: None. With no FWD, there was nothing to appeal under § 319.
• Defensive value: The PTAB found a reasonable likelihood that claims 1, 7, 10 and 11 were unpatentable over Fujii-based art — that institution decision is a roadmap you can read today, and because ASUS and Avago jointly requested termination, 35 U.S.C. § 315(e) estoppel expressly does not attach to ASUS. The other side of the coin: no FWD, so the institution decision carries no preclusive or stare-decisis effect and proves nothing about the merits.
• Sources: Unified Patents PTAB record · Joint Motion to Terminate, 2017-05-16 · Patent Owner Response, 2016-12-06

IPR2017-00520 — Sony Corporation v. Avago Technologies General IP (Singapore) Pte. Ltd.

• Type: Inter Partes Review
• Filed: 2016-12-21 (per Docket Alarm docket metadata; a December 2016 filing carrying an FY2017 case number is normal PTAB practice — the FY2017 series begins 2016-10-01)
• Status: Settlement — the Google Patents family record lists this case as "PTAB case IPR2017-00520 filed (Settlement)."
• Judge panel: Not recovered.
• Petition grounds: Not verified. Sony was adverse to Avago/Broadcom in the parallel Broadcom Corp. v. Sony Corp., No. SACV 16-1052 JVS (JCGx) (C.D. Cal.) MPEG patent litigation, and the '087 patent was in that case's asserted set — but I could not retrieve the IPR2017-00520 petition, so I will not state which claims or references it asserted. Do not attribute the "Maturi / Yao / Bheda" grounds to this case without verification; the Maturi-based grounds I retrieved appear in a later petition and their case attribution is uncertain.
• Institution decision: Not verified (i.e., unknown whether this settled pre- or post-institution).
• Final Written Decision: None. No FWD issued.
• Settlement / termination: Settled; exact termination date and terms not verified and, for the agreement, confidential. I am flagging this as an evidentiary gap rather than filling it.
• Appeal: None (no FWD).
• Defensive value: Limited direct value — this is a third-party infringement defendant buying peace, not a validity adjudication. Its main signal is that Sony valued the litigation risk highly enough to settle rather than take the '087 claims to a written decision.
• Source: Docket Alarm PTAB record, IPR2017-00520 · Google Patents family/litigation record

IPR2017-01816 — Amazon.com, Inc. & Amazon Web Services, Inc. v. Avago Technologies General IP (Singapore) Pte. Ltd.

• Type: Inter Partes Review
• Filed: 2017-07-18
• Status: Terminated (verbatim from the trial-data record) / dismissed — Petitioner filed a voluntary withdrawal of its request for IPR and the Board granted dismissal
• Judge panel: ARPIN, Administrative Patent Judge signed the 2017-08-18 Decision on Motion to Withdraw (Paper 6). Full merits-panel composition is not applicable — the case never reached a panel decision on the merits.
• Petition grounds: Not verified as to this case number. Retrieval surfaced a § 103(a) petition against the '087 patent organized into six grounds built on Fujii (U.S. 5,898,695), Maturi (U.S. 5,559,999), Bheda (U.S. 6,002,441), Lam (U.S. 5,960,464), and Yao's "Unified Memory Architecture Cuts PC Cost," with claim groups spanning claims 1–3, 7, 10–13, and 16–18 — but I could not confirm whether that petition is IPR2017-01816 or a sibling Amazon filing. Treat the reference list as attributable to the 2017 Amazon/Avago '087 challenge only with that caveat.
• Institution decision: None. The Board never made an institution determination. The joint motion is explicit: "Avago has not filed its Preliminary Response … and the Board has not made an institution determination nor conducted an oral hearing."
• Final Written Decision: None.
• Settlement / termination: Joint motion to dismiss under 35 U.S.C. § 314(b) / 37 C.F.R. § 42.71(a) filed 2017-10-25 (Board authorized by email 2017-10-24); termination decision granting dismissal (Paper 11) 2017-11-06. Driven by a broader Broadcom–Amazon settlement: the companion district court case Broadcom Corp. v. Amazon.com, Inc., No. 8:16-cv-01774 JVS (JCGx) (C.D. Cal.), was dismissed on 2017-10-06 upon notice of settlement. Agreement filed as confidential Ex. 1016; terms not public.
• Appeal: None.
• Defensive value: Essentially zero as a validity precedent — but no estoppel attaches (dismissal before institution; § 315(e)(2) requires a final written decision), so nothing here is foreclosed to a future challenger. Its real content is chain-of-custody evidence: it confirms the enforcing entity in 2017 was Avago Technologies General IP (Singapore) Pte. Ltd., with Avago identifying Broadcom Cayman L.P., Broadcom Limited, and related Avago/Broadcom holding entities as interested parties.
• Sources: Joint Motion to Dismiss, 2017-10-25 · Decision on Motion to Withdraw, 2017-08-18 · Patent Owner Mandatory Notice, 2017-08-30 · Docket Alarm search, patent:(5870087)

Strategic summary

Claim status: everything is UNTESTED. There is no claim of 5,870,087 that is canceled, and none that is sustained. Three petitions were filed and every one was resolved by agreement — one after institution (IPR2016-00646), one before any institution decision (IPR2017-01816), and one at an unverified stage (IPR2017-00520). No Final Written Decision exists for this patent, and accordingly no claim was ever construed by the Board on the merits — the only claim-construction law on this patent comes from the district courts (e.g., the Funai Elec. Co. v. LSI Corp., No. 5:16-cv-01210-BLF (N.D. Cal.) indefiniteness/construction ruling finding "single memory" and "first unified memory" mean "memory functioning as a unit," and the earlier LSI v. Barnes & Noble / 3:11-cv-2709 construction of "a single memory device which stores code and data for the transport logic, system controller and MPEG decoder functions"). Contradiction flagged against the previously generated section: that earlier section credited the "memory functioning as a unit" / not-limited-to-a-single-chip reasoning to Judge Freeman and the "single memory device" construction to Judge Chen; the retrieved Funai order actually reports Judge Chen as the source of the "single memory device" construction and the Funai court as adopting "memory functioning as a unit" while agreeing with Judge Chen that the term is not limited to a single chip. Use the district court orders themselves, not either summary.

Estoppel landscape — the shelf is empty and so is the blame. Because nothing reached a Final Written Decision:

• ASUS — expressly no § 315(e) estoppel, stated on the face of the joint motion ("because ASUS and Avago request this termination, no estoppel under 35 U.S.C. § 315(e) shall attach as to Petitioner ASUS").
• Amazon/AWS — no estoppel; dismissal occurred before institution and without any Board merits determination.
• Sony — presumptively no estoppel (settlement), though I could not verify whether institution preceded settlement; a post-institution settlement-in-fact without a Board termination decision would be the only scenario worth checking.
• Net effect for a defendant asserted today: no IPR estoppel bars any party, and no § 315(e)(2) "reasonably could have raised" trap applies. Every printed publication and patent these petitioners used — Fujii, Maturi, Bheda, Lam, and the Yao article — remains fully available to you in district court. That is the rare case where the patent's trial history is favorable to a challenger.

Pattern signals. (1) Three different, unrelated petitioners attacked this patent within eighteen months — ASUS (consumer PCs), Sony (consumer electronics), and Amazon/AWS (streaming/retail) — which is a strong market-wide signal that the enforcing entity was running a broad assertion campaign rather than a targeted one. (2) Amazon ran a coordinated multi-patent assault, simultaneously filing IPRs on at least four Avago/Broadcom patents — IPR2017-00963 (U.S. 6,744,387), IPR2017-00964 (U.S. 6,982,663), IPR2017-01112 (U.S. 6,341,375), and IPR2017-01816 (U.S. 5,870,087) — all four dismissed together on 2017-11-06 as part of a single settlement. (3) Patent Owner never appealed anything, because there was never a decision to appeal; the CAFC docket entries 14-1410 and 17-1491 associated with this family are not appeals from these IPRs. (4) No defensive aggregator is in the chain — there is no Unified Patents or RPX-filed IPR on this patent; the Google Patents listing that appears to attribute IPR2017-01816 and IPR2017-00520 to "Petitioner: Unified Patents" is a data-licensing/attribution artifact of Unified Patents' database, not a Unified Patents petition.

And the dispositive practical point: the patent is expired. Anticipated expiration 2016-11-13 (per the patent's own term calculation; the Unified Patents portal lists 2016-11-12 — the same ±1-day annotation artifact already flagged for the filing/grant dates). No further IPR can meaningfully be filed — institution would gain a defendant nothing beyond a costly race against a dead patent. All future defensive leverage is in district court and at the § 101/§ 112 level, not at the Board.

Recommended next steps

• No active proceedings to track. There is no institution deadline, no oral hearing, and no FWD due date outstanding for any of the three cases. The statutory one-year clock in IPR2016-00646 ran out with the 2017-05-16 termination; IPR2017-01816 was dismissed 2017-11-06; IPR2017-00520 settled.
• Do not cite a "PTAB decision" on this patent — there isn't one. If a demand letter, complaint, or damages theory invokes PTAB history on 5,870,087, correct it: three IPRs, zero Final Written Decisions, zero canceled claims. Anyone representing otherwise is misrepresenting the record.
• Salvage the one genuinely useful Board document. The 2016-08-22 institution decision in IPR2016-00646 is the closest thing to a merits assessment that exists; retrieve it from PTAB E2E / PTACTS (case IPR2016-00646, Paper 11) and read the Board's claim-1/claim-7/claim-10/claim-11 analysis. It is non-precedential and non-binding — an institution decision proves only a reasonable likelihood — but it is a free expert read on where the old art (Fujii in particular) bites.
• If you are defending, attack on the intrinsic record, not the Board record. The un-adjudicated, Most-constrained constructions are the leverage: the "memory functioning as a unit" versus "single memory device" split, the written-description gap that multiple petitioners pressed (that the claims recite a unified memory but never recite how it overcomes the 4-Mbit-granularity/16-Mbit cost problem the specification identifies as the prior-art barrier), and the § 112 indefiniteness fight that the Funai court resolved only narrowly in Avago's favor. Those arguments were never tested by the Board and remain open.
• Confirm the residual verification gaps before relying on this section. Two items are explicitly unverified and I have not filled them in: (i) the full instituted claim set and panel roster for IPR2016-00646; and (ii) the complete record for IPR2017-00520 (petition grounds, institution status, termination date, panel). Pull both from PTAB E2E and, if any of it matters to your position, say so on the record rather than citing this summary.

I'll search for the recorded assignment details, including reel/frame numbers and correspondents, since the Google Patents record lists the events but not those fields.

Let me try to pin down the specific reel/frame numbers and correspondents for this patent.

Assignment & Ownership Analysis — US 5,870,087

Sourcing note (read first). In this session I have no direct query capability against the USPTO Assignment Center / assignment.uspto.gov database — the only retrieval tool available to me is open-web search, which does not index reel/frame numbers, execution dates, or the correspondent of record field for this patent. What I could reconstruct comes from three sources, in descending reliability:

1. The Google Patents "reassignment" legal-events block in the authoritative full text supplied (which lists dates + conveyance types but was fetched without the per-event REEL/FRAME and correspondent fields).
2. A JETRO / KIPO ownership-history table (2016 snapshot) that independently lists the '087 assignment history as 2 records, with dates and parties.
3. Sibling Avago/LSI patents in the same corporate chain (e.g., US 7,955,904; US 6,526,076), whose legal-event blocks are indexed in search results and expose the group's blanket reel/frame numbers.

I have not fabricated any reel/frame, correspondent, or execution date. Where a field was not retrievable I say so explicitly. Verify at https://assignmentcenter.uspto.gov/ (patent number search) or https://assignment.uspto.gov/patent/index.html.

Inventors

Unusual-pattern check — NOT present / no data. LSI Logic was an operating semiconductor company, and the three applications this patent incorporates by reference (Ser. Nos. 08/654,321; 08/653,845; 08/689,300) are all LSI Logic in-house filings by Chau/Auld. That is the ordinary signature of a single-company inventor team, not a group of inventors who departed the assignee within 12 months. I found no evidence of Chau leaving LSI Logic, and I will not infer one. (Note: no inventor-employment data beyond the assignment itself is in the public record.)

Original assignee

• Entity on the issued patent: LSI Logic Corporation, Milpitas, California (electron/semiconductor design; assignee of record from the 1996-11-13 assignment).
• Primary line of business: semiconductor design and manufacture — custom ASICs and standard-chip MPEG / MPEG-2 audio-video decoder silicon.
• Did it ship a product embodying the claims? Yes — well supported by the patent's own text. The specification expressly identifies "LSI part no. L64005 … a device produced by LSI Logic" as a commercial MPEG decoder used as the memory-saving baseline (FIGS. 6a/6b discussion). LSI Logic's L64005/L64008 MPEG decoders were shipping parts. This is a product-embodying assignee, not a paper owner.
• Current status of the original assignee: LSI Logic Corp. changed its name to LSI Corporation (recorded 2012-03-09) and was thereafter acquired by Avago Technologies (merger agreement dated 2013-12-15; shareholder special meeting 2014-04-09; acquisition completed May 2014). Avago acquired Broadcom Corp. in Feb. 2016 and the combined company was renamed Broadcom Inc. in 2018. LSI is therefore not an independent entity — it is a brand/subsidiary inside the Broadcom group. The '087 patent's ownership of record now sits in the Avago (Broadcom) IP-holding chain (see below), current assignee listed as Avago Technologies International Sales Pte. Ltd. (Singapore).

Assignment timeline

The Google Patents legal-events block for '087 records the following. Reel/frame was retrievable for only one entry (marked); correspondents were not retrievable at all via open search and are therefore left blank rather than guessed.

1. 1996-11-13 (executed) / recorded 1996-11-13 — Reel not retrieved

• Conveyance: Assignment of assignors' interest (original, pre-issuance)
• Assignor: Kwok Kit Chau
• Assignee: LSI Logic Corporation
• Correspondent: not retrievable
• Context: Initial inventor-to-company assignment on the filing date (LSI Logic is the operating employer).

2. 2012-03-09 (executed) / recorded 2012-03-09 — Reel not retrieved

• Conveyance: Change of Name ("see document for details")
• Assignor: LSI Logic Corporation
• Assignee: LSI Corporation
• Correspondent: not retrievable
• Context: Internal reorg — change of name only (no change in beneficial ownership; confirmed by the JETRO/KIPO table listing "LSI LOGIC CORPORATION → LSI CORPORATION, 2012.03.09").

3. 2014-05-08 (executed) / recorded 2014-05-08 — Reel 032856 / Frame 0031 ✅ (reel/frame confirmed)

• Conveyance: Patent Security Agreement (grant of security interest)
• Assignor: LSI Corporation; Agere Systems LLC
• Assignee: Deutsche Bank AG New York Branch, as Collateral Agent
• Correspondent: not retrievable
• Context: Securitization — collateral grant over the LSI/Agere patent estate in connection with corporate financing; recorded two days after the Avago–LSI acquisition closed (~May 6, 2014).
• Reel/frame derivation: the later termination entry (item 6) is captioned "RELEASES RF 032856-0031", which expressly identifies the original security agreement's recording location.

4. 2015-02-17 (executed) / recorded 2015-02-17 — Reel not retrieved

• Conveyance: Assignment of interest
• Assignor: LSI Corporation
• Assignee: Avago Technologies General IP (Singapore) Pte. Ltd.
• Correspondent: not retrievable
• Context: Post-acquisition transfer to group IP subsidiary — Avago rolled the acquired LSI patent estate into its Singapore IP-holding entity (JETRO/KIPO table lists this as the final transfer, "LSI CORPORATION → AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE., 2015.02.17").

5. 2015-02-20 (executed) / recorded 2015-02-20 — Reel not retrieved

• Conveyance: Assignment of interest (second recording, LSI Corporation → Avago General IP)
• Assignor: LSI Corporation
• Assignee: Avago Technologies General IP (Singapore) Pte. Ltd.
• Correspondent: not retrievable
• Context: Administrative cleanup / second or corrective recording three days after item 4 — same counterparties, same direction; typical of a bulk bundle recorded in two tranches (not a substantive new transfer).

6. 2016-02-02 (executed) / recorded 2016-02-02 — Reel not retrieved (release of RF 032856/0031)

• Conveyance: Termination and Release of Security Interest in Patent Rights
• Assignor: Deutsche Bank AG New York Branch, as Collateral Agent
• Assignee: LSI Corporation; Agere Systems LLC
• Correspondent: not retrievable
• Context: Release of the item-3 security interest (closing out the Deutsche Bank collateral position).

7. 2016-02-11 (executed) / recorded 2016-02-11 — Reel/frame not confirmed (sibling Avago patents use 037808/0001)

• Conveyance: Patent Security Agreement
• Assignor: Avago Technologies General IP (Singapore) Pte. Ltd.
• Assignee: Bank of America, N.A., as Collateral Agent
• Correspondent: not retrievable
• Context: Securitization — replacement collateral grant after the Feb. 2016 release, coinciding with the Avago–Broadcom combination.

8. 2017-02-03 (executed) / recorded 2017-02-03 — Reel/frame not confirmed (sibling Avago patents use 041710/0001)

• Conveyance: Termination and Release of Security Interest in Patents
• Assignor: Bank of America, N.A., as Collateral Agent
• Assignee: Avago Technologies General IP (Singapore) Pte. Ltd.
• Correspondent: not retrievable
• Context: Release of the item-7 security interest — final event in the Google Patents legal-events block for '087.

Downstream merger events (not shown in the '087 legal-events block — flagged discrepancy). Google Patents lists the current assignee as Avago Technologies International Sales Pte. Ltd., but the '087 legal-events block ends at 2017-02-03 and shows no recording transferring Avago General IP → Avago International Sales. On sibling Avago/LSI patents (US 7,955,904; US 6,526,076) that transfer is recorded as a Merger, REEL 047196/0687 (recorded 2018-05-09, effective 2018-09-05; corrective at REEL 047630/0344), and a further transfer to Broadcom International Pte. Ltd., REEL 053771/0901 (2020-08-26). I could not confirm these specific reels carry the '087 patent, so I am not asserting them — but the "current assignee" label on Google Patents is only consistent with those merger recordings having occurred for '087 as well.

⚠️ Contradiction with the previously generated section — flagged

The earlier "Litigation/CAFC" section states the Google Patents current assignee is "Avago Technologies International Sales Pte. Ltd." while also noting the JETRO-family snapshot lists "Avago Technologies General IP (Singapore) Pte. Ltd." as final owner. Both are correct as of their respective dates: General IP (Singapore) was the owner of record 2015→2018, and the International Sales entity is the post-2018 merger successor. There is one date conflict between my assignment data and the earlier summary: the earlier section reports the Unified Patents portal listing priority 1996-11-12 / grant 1999-02-08, whereas every assignment/family record here gives filed & assigned 1996-11-13, issued 1999-02-09. I continue to treat the patent text and the recorded-assignment dates as authoritative.

Timeline diagram

timeline
    title Ownership of US 5870087
    1996 : Chau files application
         : Assigned to LSI Logic Corp
    1999 : Patent issued
    2012 : LSI Logic renamed LSI Corporation
    2014 : Avago completes acquisition of LSI
         : Deutsche Bank security interest recorded
    2015 : Assigned to Avago General IP Singapore
    2016 : Broadcom combination closes
         : Avago asserts patent vs ASUS and Sony
         : Patent expires
    2017 : Bank of America security interest released

NPE / troll-pattern signals

Verdict

Operating-company assertion.

The ownership chain is a single corporate family — LSI Logic Corp. → LSI Corp. (change of name, 2012-03-09) → Avago Technologies General IP (Singapore) Pte. Ltd. (assignment, 2015-02-17/20) — with intervening collateral security interests (Deutsche Bank recorded 2014-05-08 at REEL 032856/0031, released 2016-02-02; Bank of America recorded 2016-02-11, released 2017-02-03). None of these are NPE hallmarks: there is no shell-LLC transfer, no known NPE assignee, no chained-LLC cascade, and no bankruptcy. The original assignee (LSI Logic) shipped MPEG decoder silicon embodying the claims (its own L64005 part is cited in the specification), and the asserting successor (Avago/Broadcom) is an operating semiconductor company suing actual competitors (ASUS, Acer, Sony, Amazon), which is why the patent reads as a genuine operating-company assertion rather than a troll chain — notwithstanding that the '087 patent sat at the center of a large NPE-vs-defendant IPR fight in 2016–2017.

Verification links:

• USPTO Assignment Center: https://assignmentcenter.uspto.gov/
• USPTO Assignment (legacy UI): https://assignment.uspto.gov/patent/index.html
• Google Patents legal events: https://patents.google.com/patent/US5870087/en

Remaining gaps I could not close (stated rather than guessed): (a) the correspondent of record for all eight recordings; (b) the execution dates as distinct from recording dates (Google Patents shows a single date per event); (c) reel/frame for items 1, 2, 4, 5, 6; and (d) whether the post-2018 Avago→International Sales→Broadcom merger recordings cover the '087 patent. A direct Assignment Center pull (Assignments on the Web, reel/frame detail view) would resolve (a)–(d) and is the appropriate next step.

I'll research the prior-art citations for US 5,870,087. Let me start with the front-page patent citations and the IPR-cited references.

Let me research each cited reference individually.

Let me look up the specifics of each cited patent and the IPR references.

Prior-Art Analysis for US 5,870,087 — References & § 102 Mapping

Scope note (honest limitation): I retrieved the authoritative full text from Google Patents and the PTAB petition exhibits, but I was cut off by a tool step-limit before fully verifying the titles/abstracts of every front-page reference. Below I clearly separate (a) references I confirmed from (b) items I could only partially verify, and I flag anything I could not independently confirm rather than filling it in. Nothing is auto-corrected: all numbers are used literally as listed on the '087 record.

1. The two families of prior art relevant here

Important distinction that the request should not blur:

Because the IPRs settled, nothing in the IPR art was ever found to anticipate or render obvious any '087 claim. That is a legal-status fact you should not lose sight of when reading the mapping below.

2. Front-page (Examiner-cited) references

Confirmed from the '087 front page reproduced in the PTAB/IPR exhibit PDF (Docket Alarm, Exhibit 1008 of IPR2020-00479):
URL: https://www.docketalarm.com/cases/PTAB/IPR2020-00479/Google_LLC_v._Uniloc_2017_LLC/docs/01-28-2020-Petitioner/Exhibit-1008-Exhibit_1008.pdf

Critical timing point for § 102 purposes: the '087 application was filed November 13, 1996. Every one of these three references issued after that filing date (10/1997, 11/1997, 6/1998). Therefore none is § 102(a)/(b) "prior art by publication." Their only possible § 102 role is § 102(e) — i.e., a U.S. patent granted on an application filed before the '087 filing date. This is a real limitation on their anticipatory reach and is often overlooked.

Reference-by-reference

US 5,675,511 — Prasad (granted 10/1997)

• Full citation: U.S. Patent 5,675,511, to Prasad (Examiner-cited on '087).
• Date: granted October 1997; filed before 11/13/1996 → potential § 102(e) art.
• Description: I could not independently confirm the subject matter in this session. Given its placement on an MPEG-decoder front page alongside Goldberg and Nakamura and its mid-1990s DiviCom/compression-era provenance, it is consistent with a digital-video/decoder-system reference, but I am not asserting that description as fact.
• Potential § 102 claims: none supportable without the disclosure. Cannot responsibly map.

US 5,692,213 — Goldberg et al. (granted 11/1997)

• Full citation: U.S. Patent 5,692,213, to Goldberg et al. (Examiner-cited on '087).
• Date: granted November 1997; earlier-filed application → potential § 102(e) art.
• Description: not independently confirmed this session; title/subject matter flagged as unverified.
• Potential § 102 claims: cannot responsibly map without the disclosure text.

US 5,767,846 — Nakamura et al. (granted 6/1998)

• Full citation: U.S. Patent 5,767,846, to Nakamura et al., granted June 1998; Examiner-cited on '087 (confirmed on the front-page exhibit).
• Date: granted 6/1998, after the '087 filing date → potential § 102(e) art only.
• Description: appears to concern decoder/video-decoder subject matter, but I did not confirm the specification; treat the substance as unverified.
• Potential § 102 claims: most plausibly maps against the memory-organization claims — i.e., claim 7 (video-frame portion / system-controller portion / transport-buffer portion) and/or claim 1 / claim 16 (single memory shared by decode + controller functions) — if its disclosure shows a unified memory serving both a decoder and a controller. I cannot confirm that it does.

Bottom line on the three front-page references: I can confirm which references were cited and when they issued, but I was not able to re-verify their disclosures within this session, so I am declining to assert specific § 102 anticipation beyond the timing analysis. That is the honest state of the record.

3. IPR-asserted art (never adjudicated — settlement)

These were cited by IPR petitioners for § 103 obviousness (not § 102), in the three settled IPRs. Confirmed from the PTAB petition text (PTACTS):

• Maturi-based grounds: https://ptacts.uspto.gov/ptacts/public-informations/petitions/1494815/... and .../petitions/1478054/...
• The petition argued elements against claims 1, 2–3, 7, 16, 17.

Maturi — US 5,559,999 (the strongest § 102 candidate among the IPR art)

• What the petition record affirmatively attributes to Maturi (well documented in the PTACTS excerpts I retrieved):
  • pre-parser 22 = transport logic that demultiplexes → stores encoded access units ("frames") into the video channel buffer 20b / audio channel buffer 20d;
  • post-parser 24 reads access units out to video decoder 26 / audio decoder 28 (MPEG decoders);
  • host microcontroller 18 + channel controller 34 = system controller, reading/writing DRAM 20 over bus 36;
  • DRAM 20 contains a frame memory buffer 20e (decoded frames for display);
  • Maturi states DRAM 20 "can be placed inside the microcontroller."
• Date: US 5,559,999 — not independently confirmed this session (issue year per prior section ~1996).
• Potential § 102 mapping (Maturi alone):
  • Claim 1 / Claim 16 — Maturi alone appears to disclose elements 1.1–1.5, 1.7, 1.9 / 16.1–16.5, 16.7, 16.9 (channel receiver, transport logic, system controller, decoder, single DRAM coupled to the decoder and used by transport logic). The questionable element is 1.6/16.6 — the memory "stores code and data useable by the system controller." The petitioner did not rely on Maturi alone for this; it used Yao to supply the motivation to unify code storage. That signals A POSITA-level gap, i.e., Maturi alone is a weak § 102 basis for claim 1 but a plausible § 103 combination.
  • Claim 7 — Maturi's DRAM 20 (video-frame portion 20e + transport buffers 20b/20d) is asserted to disclose the "plurality of memory portions" limitation; the system-controller portion again requires Yao.
  • Claim 5 (anchor frame data) — plausibly disclosed by Maturi's frame memory buffer.
  • Claims 2–3, 17 — not met by Maturi alone; require Bheda (memory controller) → § 103.

Bheda — US 6,002,441

• Role: discloses an MPEG decoder in which the decoder itself includes the memory controller coupled to the memory.
• Potential mapping: dependent claim 2 (decoder includes memory controller coupled to the memory) and claim 3 (memory controller stores compressed data) — but only as part of a § 103 combination with Maturi/Fujii, not as § 102 anticipation. Date not independently confirmed this session.

Fujii — US 5,898,695

• Role: primary reference in the Fujii+Bheda ground. Grant date (1999) is after the '087 filing → § 102(e) art at best. Disclosure not verified this session; cannot responsibly map claims.

Lam — US 5,960,464

• Role: asserted in one IPR ground. Grant date (1999) after '087 filing → § 102(e) at best. Disclosure not verified this session; cannot responsibly map claims.

Yao — "Unified Memory Architecture Cuts PC Cost" (NPL)

• Role: motivation to combine for § 103 — it is an article, not a patent, and is not capable of anticipating any claim under § 102. Any § 102 argument built on Yao alone would fail as a matter of law.

4. Summary table — § 102 anticipation potential

Most relevant single reference overall: on the record I can actually support, Maturi (US 5,559,999) is the closest single-reference § 102 candidate — but even the petitioner treated the "system controller code/data in the unified memory" limitation (claim element 1.6/16.6) as requiring Yao, which means Maturi alone is better characterized as anticipatory only for the broader genus claims (1/16) and claim 5, and as a § 103 combination for the rest. That is precisely why the patent survived — no final decision ever issued.

5. What I could not verify (explicit)

1. The titles and disclosures of US 5,675,511 (Prasad) and US 5,692,213 (Goldberg) — I have the citation but not the substance.
2. The substance of US 5,767,846 (Nakamura) beyond its confirmed presence on the '087 front page and its 6/1998 grant date.
3. The disclosures of Fujii (5,898,695), Bheda (6,002,441), and Lam (5,960,464) — I have their roles in the IPR grounds but not their text.
4. The exact filing dates of the front-page references (needed to confirm § 102(e) status) — I inferred § 102(e) from their post-11/13/1996 grant dates, but did not confirm each application's filing date.

If you want, I can run a fresh, targeted pass on any single one of these (e.g., pull the full front page and "References Cited" from the Google Patents record, then retrieve each reference's abstract) to convert the "possible/unverified" entries above into firm § 102 statements.

I'll ground the § 103 analysis in the actual prior-art references identified in the earlier sections. Let me verify their disclosures.

Obviousness Analysis — U.S. Patent No. 5,870,087 under 35 U.S.C. § 103(a)

Note on scope: This analysis builds on the bibliographic, claim, and litigation sections already generated and does not repeat them. Because the '087 patent has a Nov. 13, 1996 filing date, pre-AIA § 102/103 governs. The patent is expired, and (as the earlier sections establish) all three IPRs settled or were dismissed without a final written decision on validity, so the obviousness question was never adjudicated to final judgment. The grounds below are the ones Petitioners actually advanced, and the Board's institution decisions are evidence only of a "reasonable likelihood" of unpatentability (e.g., the Board "already found a reasonable likelihood that claim 5 … is obvious in view of Fujii and Lam"). Source for the grounds: IPR2016-00646 Petitioner's Request for Oral Argument (https://www.docketalarm.com/cases/[PTAB](/ptab)/IPR2016-00646/Inter_Partes_Review_of_U.S._Pat._5870087/docs/04-06-2017-Petitioner/Oral_Hearing_Request-21-Petitioners_Request_for_Oral_Argument.pdf) and the IPR2017-01816 petition/declaration (https://www.docketalarm.com/cases/PTAB/IPR2017-01816/Inter_Partes_Review_of_U.S._Pat._5870087/docs/07-18-2017-Petitioner/Petition-2-Petition_for_Inter_Partes_Review.pdf).

1. Legal framework and the person of ordinary skill

Standard. Pre-AIA § 103(a) asks whether the subject matter as a whole would have been obvious at the time of invention to a person having ordinary skill in the art. Under Graham v. John Deere the inquiry considers (i) the scope and content of the prior art, (ii) the differences between the prior art and the claims, (iii) the PHOSITA's level of skill, and (iv) objective indicia. Under KSR Int'l v. Teleflex (2007), a combination is obvious where the improvement is a "predictable variation," where a "known technique" is applied to improve a similar device in the same way, or where there was a "design need or market pressure" and a finite number of identified, predictable solutions. Critically for this patent, KSR also teaches that "[t]he design incentive … may be found in the nature of the problem to be solved" — here, the '087 patent's own specification supplies that incentive almost verbatim.

PHOSITA (proposed). At November 1996, a person of ordinary skill in the art would have a B.S. in electrical/computer engineering (or equivalent) plus roughly 2–4 years of experience in digital video / MPEG decoder or ASIC design (or an M.S. with 1–2 years), and would be familiar with MPEG-1/MPEG-2 (ISO/IEC 11172 and the incorporated ISO/IEC 13818), MPEG transport/program streams, macroblock-based decoding, and DRAM/SDRAM memory-controller design. This is a mature, well-documented art by 1996 — a point that cuts strongly toward obviousness because the reference disclosures are highly combinable.

Claim-construction impact (favorable to the obviousness case). As noted in the earlier sections, the ITC and N.D. Cal. adopted the broad construction of "single memory"/"first unified memory" = "memory functioning as a unit" — not limited to one physical chip (see the TIPO compilation of the ITC Markman analysis, https://tiponet.tipo.gov.tw/downloads/module030/communication_103_3.pdf). Patent Owner had urged the narrow reading ("a single unified memory … with reduced memory requirements … i.e., less than 20 or 24 Mbits"), which the tribunal rejected. This is decisive for § 103: it means a multi-chip memory subsystem that "functions as a unit" (e.g., a main RAM plus on-chip memory that the system treats as one unified pool) can satisfy the limitation — so prior-art systems with a main memory and a small ancillary memory still read on the claim. The three "operability" clauses ("operable to access the memory during …") are functional and add essentially no structure.

Independent claims: 1 (MPEG apparatus), 10 (method), 16 (video-decoder-system genus). All three reduce to the same core: one memory pool used (a) by transport logic during demultiplexing, (b) by the decoder during decoding, and (c) by a system controller retrieving code and data. Every combination below is aimed at that core; the dependent claims (memory controller, compressed-data storage, dynamic allocation, anchor storage, memory partitioning, audio buffers, 16 Mb) are addressed in § 4.

2. The prior-art record (as relied on by Petitioners)

3. The core combinations and the motivation to combine

Combination A — Fujii alone (single-reference; anticipation, and a fortiori obviousness)

Fujii is the strongest single reference. It discloses the full tri-functional memory: transport logic (Program Packet Filter / Interface Unit 14) that stores and retrieves PID/TS header data in RAM 7 during demultiplexing; a system controller (microprocessor 12) whose "system control program + data" live in RAM 7; and decoder accesses to RAM 7 for I/P/B frame data. Petitioners asserted § 102(e) anticipation of claims 1, 7, 10, 11, and 16 over Fujii. Even if one were to find a missing literal element (e.g., whether RAM 7 and the video-decode buffer 9 are one "memory"), that gap is at most a trivial design choice ("memory functioning as a unit"), which § 103 supplies. No motivation-to-combine analysis is even required for a single-reference case; the obviousness framing is simply that any perceived difference is an insubstantial, predictable variation.

Combination B — Fujii + Lam (§ 103(a)) — claims 1, 5, 7–11, 16

• What Lam adds: the requirement (claim 5) that the memory store anchor-frame data during reconstruction of temporally compressed frames.
• Motivation: Fujii supports MPEG-2 and already stores I, P, and B frames; MPEG-2 by definition requires two anchor (I/P) frames in memory to reconstruct P and B frames — an invariant of the standard. Lam merely makes explicit what MPEG-2 decoding requires. The only two places Fujii could put anchor data are RAM 7 or the video-decode buffer; storing them in the main memory is the natural, predictable choice. Result: allowed claims read as an expected use of a reference frame store that any MPEG-2 decoder must have. This is the ground the Board found reasonably likely to succeed on claim 5.

Combination C — Fujii + Bheda (§ 103(a)) — claims 2–3, 17

• What Bheda adds: an MPEG-decoder memory controller (claim 2/17) and storing compressed data in memory (claim 3).
• Motivation: Any DRAM-based system necessarily includes a memory controller to map requests and arbitrate competing accesses; a POSITA would treat the controller as inherent/obvious. Placing the controller in the decoder (rather than with the CPU) is a recognized architectural benefit — "the decoder's memory-intensive tasks would benefit by the decoder being placed near the memory controller." Storing already-compressed (MPEG-encoded) data to save space is likewise conventional (and Bheda discloses it expressly). Predictable result; nothing unexpected in the combination.

Combination D — Fujii + Cloutier (§ 103(a)) — claims 7–9 (and the three-reference ground Fujii + Lam + Cloutier)

• What Cloutier adds: the partitioned memory buffers underlying claims 7–9 (video-frame portion, system-controller portion, transport-buffer portion, video-decode buffer, display-sync buffer, OSD buffer, audio buffers) in an MPEG set-top/decoder context.
• Motivation: Cloutier is the same field (MPEG digital set-top decoders) and discloses the conventional decoder subsystem blocks (demux, MPEG video decoder, MPEG audio decoder, buffers, D/A). Combining its buffer partitioning with Fujii's unified main memory is the routine substitution of one known functional-block partition for another.

Combination E — Maturi + Yao (§ 103(a)) — independent claims 1 and 16 (and claim 7)

• What Maturi adds: a decoder+microcontroller with a shared DRAM 20 partitioned into transport/header/channel/frame buffers, a pre-parser demuxing streams into those buffers, and the host microcontroller reading code/data from that DRAM for synchronization and system control — with the express statement that the DRAM can be inside the microcontroller.
• What Yao adds / why combine: the known UMA principle — sharing one memory between a CPU and a dedicated engine reduces total memory cost. KSR directly endorses this: applying a known technique (memory sharing) to improve a similar device (a decoder chipset) in the same way is obvious.
• Motivation: Code must be stored somewhere; Maturi discloses only RAM 18a and DRAM 20, and in the "inside-the-microcontroller" embodiment RAM 18a and DRAM 20 are co-located on one chip. Combining them into one unified memory is an architectural design choice with no loss of function, and by 1996 "main memory is almost always implemented using DRAMs." This combination reads directly on independent claims 1 and 16 because it supplies all three consumers (transport/demux; decoder access; system-controller code/data) sharing one DRAM.

Combination F — Maturi + Yao + Bheda (§ 103(a)) — claims 2–3, 17

Same as Combination E plus Bheda's memory controller and compressed-data storage, for the same reasons as Combination C.

4. Dependent claims — obviousness mapping

• Claim 2 / 12 / 17 (memory controller coupled to the memory; access through it). Inherent in any DRAM/SDRAM system; Bheda discloses it expressly. Reason: a controller is a functional necessity for partitioned DRAM access/arbitration.
• Claim 3 / 13 / 18 (memory controller stores compressed data to reduce storage). Disclosed by Bheda (MPEG-encoded data) and Maturi (storing still-compressed "access units"); the '087's own specification calls this the "compressed bitstream" technique and describes storing anchor and/or B frames in MPEG-compressed form — i.e., an admitted, known memory-saving expedient. Reason: MPEG data is already compressed on receipt; retaining it compressed is the obvious way to reduce footprint.
• Claim 4 / 14 / 19 (dynamic allocation of memory segments). Pure memory-management programming/algorithmic choice with a predictable benefit (reduce unused/fragmented space). The '087's incorporated-by-reference applications (Ser. Nos. 08/654,321, 08/653,845, 08/689,300 — filed May/Aug 1996) themselves evidence that dynamic-segment allocation was known work in this exact art. Reason: optimizing allocation to available segment sizes is a routine engineering step.
• Claim 5 (anchor-frame data stored during temporal reconstruction). Lam; and inherent to MPEG-2 reconstruction. Reason: MPEG-2 mandates two anchor frames for B/P reconstruction.
• Claim 7 (memory partitioned into video-frame portion, system-controller portion, transport-buffer portion). Maturi's partitioned DRAM (20a–20e); Cloutier's decoder buffers. Reason: mirroring decoder functional blocks in memory partitioning is conventional.
• Claim 8 (video-decode buffer, display-sync buffer, OSD buffer) and Claim 9 (audio buffers). Conventional set-top decoder buffers (Cloutier; and the '087's own FIG. 6 table recites these same buffers — vbv, video decode, display-sync, audio, A/V latency, audio-display sync, jitter — as known line items). Reason: standard MPEG system-decoder buffering.
• Claim 15 / 20 (memory ≤ 16 Mb / memory is 16 megabits). A numeric design choice dictated by the industry's 4-Mbit device granularity and the then-standard "16 Mbit of external memory" for MPEG decoders (EP 0 714 208). The '087 specification itself frames this as a commercial constraint ("it is desired to keep the memory requirements below … 16 Mb, since otherwise a memory device of 20 or 24 Mb would have to be used"). Under KSR, selecting a known, commercially standard part size — and the corollary "not exceeding 16 Mb" — is a predictable variation, not patentable subject matter, absent evidence of unexpected criticality.

5. Weak points — arguments that could defeat (or narrow) the § 103 case

A balanced analyst must flag where the obviousness theory is vulnerable; these are the arguments Patent Owner actually raised:

1. "Single memory" / physical-device limitation. Patent Owner argued the claims require one unified memory with reduced requirements (<20/24 Mbits), and that (a) Maturi discloses two memories (RAM 18a + DRAM 20) and (b) Fujii discloses RAM 7 and a separate video-decode buffer 9. Petitioners' answer — adopting the broad "memory functioning as a unit" construction, and pointing to Maturi's "inside-the-microcontroller" embodiment — is strong, but if a fact-finder instead credited a narrower reading requiring a single physical device that reduces total memory, the Maturi/Fujii grounds weaken materially. This is the single biggest uncertainty in the § 103 case.
2. Teaching away / "cannot combine." The '087's own background states prior systems kept separate memories "because of the separate bandwidth and processing requirements for each memory, as well as the memory size requirements," and EP 0 714 208 expressly says the 16 Mbit memory's capacity and bandwidth are "substantially completely used … practically impossible to carry out supplementary operations." A teaching-away argument (i.e., the art told engineers a unified memory for transport + control + decode would not work within 16 Mb) is the most potent non-obviousness theory. Petitioners would counter under KSR that a reference must be read as a whole and that the UMA literature (Yao/VESA) shows the art was moving toward unification.
3. Objective indicia. The '087 was the subject of a large LSI/Agere/Avago/Broadcom licensing and enforcement campaign (ITC 337-TA-837; the district-court and IPR trail summarized previously) and the technology saw real commercial adoption. Patent Owner could assert long-felt need, commercial success, and industry praise — though the nexus hurdle is real (success is attributable to the whole decoder chipset and to licensing, not necessarily to the claimed unified-memory arrangement), and the patent's expiration and the absence of any merits ruling cut against giving this much weight.
4. Procedural posture. Because no IPR reached a final written decision, there is no estoppel and no appellate affirmance either way. The grounds above were found merely "reasonably likely" at institution; they were never tested in a final written decision or on appeal.

6. Bottom line

Under pre-AIA § 103(a) and KSR, claims 1, 10, and 16 are highly vulnerable to obviousness, with the strongest single-reference attack being Fujii (U.S. 5,898,695) and the strongest multi-reference attacks being Fujii + Lam and Maturi + Yao (optionally + Bheda). The motivation to combine is unusually strong here because it comes from (i) the shared field and shared problem (reducing MPEG-decoder memory cost), (ii) the known UMA technique (Yao/VESA), (iii) machine-level design choices (memory controller; partitioned DRAM; storing code in DRAM; the 16 Mbit part size), and (iv) — most tellingly — the '087 patent's own admitted problem statement, which recites precisely the cost-and-16-Mb incentive that KSR treats as sufficient motivation. The dependent claims (memory controller, compressed-data storage, dynamic allocation, anchor-frame storage, buffer partitioning, audio buffers, 16 Mb) are each met by a specific secondary reference or by routine design choice.

The only significant obstacles are (1) the "single memory / reduced-requirements" limitation if construed narrowly (contra the adopted "functioning as a unit" construction), and (2) a teaching-away argument grounded in the '087 background and EP 0 714 208's bandwidth-exhaustion statement. If those are rejected (as the institution decisions suggest they likely were), the claims would fall.

Confidence / caveats: (a) The Maturi patent number (5,555,999) is taken from the earlier generated section and I could not independently re-verify it here — treat the number, not the disclosure, as the soft point; the disclosure (decoder 16 / microcontroller 18 / partitioned DRAM 20 / pre-parser 22 / channel controller 34) is corroborated by the PTAB petition excerpts. (b) The claim-to-number mapping for the dependent claims (esp. 15/20 for the 16 Mb limitation, and 19 for dynamic allocation) rests partly on machine-translated family text, so treat those specific numbers as "bracketed." (c) All statements about PTAB outcomes reflect settlement/dismissal without a final decision; nothing here should be read as an adjudicated validity holding.