US 6492692

I'll run targeted searches for the exact number against USPTO and CAFC sources, plus claim text.

Let me pull the actual claim text and run the CAFC-specific check.

US Patent 6,492,692 — Identified-Number Verification & Plain-Language Summary

A. Search results for the exact number 6492692

USPTO / patent databases: The number resolves cleanly to US 6,492,692 B1, granted 2002-12-10. No auto-correction was applied; several near-miss identifiers surfaced during the search and are not this patent (see Section E).

CAFC 2026 dockets: My first CAFC-directed query returned zero results. Two further follow-up queries (claim text + CAFC docket + abstract) returned a tool step-limit error rather than data, so I could not complete a live CAFC docket check. Treat the CAFC finding as a negative result from an incomplete search, not a certification. This is consistent with — but does not independently confirm — the earlier "no litigation" and "no PTAB proceeding" findings already generated for this patent in this analysis.

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B. Bibliographic summary (as literally recorded)

This matches the ownership/inventor record already established in the Assignment History section of this analysis (Seiko Instruments → SII Semiconductor 2016-02-12 → Ablic Inc.). No contradiction found.

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C. Abstract

I could not retrieve the abstract's verbatim wording from the search results (Google Patents returned only its indexed metadata for the abstract field, not the text; the Justia mirror returned the specification and claims but not the abstract block). Rather than quote from memory and risk fabricating language, here is a clearly-labeled paraphrase drawn from the specification's own stated objects and summary (the "Definitions"/summary passages in the full text):

The disclosure concerns a semiconductor integrated circuit in which an external electrically-connecting terminal (pad/bump) is superposed in two dimensions over a high-withstand-voltage insulated-gate field-effect transistor — specifically over its drain region — rather than being placed beside it. The transistor's drain has a two-part construction (a deep, low-density first drain region and a shallow, high-density second drain region within it), and an opening in the final protecting (passivation) film is superposed on the second drain region to expose the underlying metal. A bump is formed on that metal through the opening. Because the pad sits over the transistor's drain, chip area is reduced, and the gate-to-drain-contact spacing can be increased to raise electrostatic withstand voltage.

Flag: This is a paraphrase, not the patent's abstract text. If the verbatim abstract is needed, pull it from PatentCenter or the PDF front page.

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D. Plain-language overview of the independent claim(s)

The retrieved Justia claim block shows claims 1–8, with claim 1 as the only independent claim in that retrieved set (claims 2–8 all read "as claimed in claim 1" or a claim depending from it).

Claim 1 — the independent claim

Claim 1 is a device claim for a semiconductor integrated circuit, and it requires all of the following in combination:

1. a first-conductivity-type semiconductor substrate;
2. a second-conductivity-type field-effect transistor on the substrate surface, having a high-withstand-voltage drain made of two regions:
   • a first drain region = a deep, low-density second-conductivity-type impurity region, and
   • a second drain region = a shallow, high-density second-conductivity-type impurity region formed inside the surface of the first drain region;
3. an external electrically-connecting terminal electrically connected to the second drain region through a metal film, for connecting to an external circuit;
4. a protecting film covering and protecting the integrated circuit;
5. an opening hole in the protecting film, superposed on the second drain region, that exposes the metal film; and
6. a bump disposed on the metal through the opening hole.

In plain terms: the heart of the claim is a spatial relationship — the passivation opening (and hence the pad/bump that sits in it) sits directly above the high-density drain of a high-voltage transistor, with the bump landed on the metal film exposed through that opening. The high-voltage drain itself is the familiar double-diffused structure (deep lightly-doped region + shallow heavily-doped contact region).

The dependent claims (2–8), in plain terms

Uncertainty flag: The retrieved claim block ended mid-sentence at claim 8, and the title promises a "manufacturing method." I could not confirm whether claims beyond 8 exist and whether any method claim (e.g., to the dicing/flip-chip mounting steps described in the specification) issued. The earlier Prior Art and Obviousness sections likewise noted only claims 1–8 as verified and treated claim 1 as the sole independent claim. Verify the total claim set against PatentCenter before relying on it.

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E. False-positive identifiers encountered (do NOT conflate with this patent)

The instruction was to interpret identifiers literally. These surfaced and are different things:

• JP 6492692 B2 — Japanese Patent No. 6492692, issued 平成31年4月3日 (2019-04-03), to Nissan Motor Co. (日産自動車株式会社), titled "塗装乾燥装置及び塗装乾燥方法" (coating/paint drying apparatus and method). Completely unrelated — this is the Japanese number that the earlier Litigation and PTAB sections also flagged.
• US 4,073,055 appears in the references cited of this patent — it is prior art cited by the patent, not the patent.
• US 7,420,280 / US 8,674,507 / US 9,444,399 — later patents that cite US 6,492,692; they are forward citations, not this patent.
• The "6492692" transaction/docket IDs (Nevada state docket entry, Swiss filing ID) noted in the earlier Litigation section remain unrelated.

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F. Related same-inventor patents (useful identifier cross-check, not this patent)

The common-inventor search surfaced two siblings from the same Seiko Instruments group that share inventors with the '692 — relevant for disambiguation in any docket search:

• US 6,222,235 — "Small geometry high voltage semiconductor device" (Kazutoshi Ishii, Masaaki Kamiya, Yasuhiro Moya), 2001-04-24.
• US 6,022,792 — "Semiconductor dicing and assembling method" (Kazutoshi Ishii, Naoto Inoue, Koushi Maemura, Shoji Nakanishi, Kiyoaki Kadoi +3), 2000-02-08 — notably overlapping the '692's inventor roster and its dicing/mounting disclosure.

These are separate patents, but they are plausible sources of confusion in a naive patent-number search.

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G. Explicit uncertainties

1. CAFC 2026 dockets — not completed. My CAFC-directed search returned no hits, but follow-up queries hit a tool step limit, so I did not run a live CAFC docket query. State the CAFC result as "no results found in an incomplete search."
2. Abstract — not retrieved verbatim. Section C is a labeled paraphrase.
3. Total claim set — not fully verified. Only claims 1–8 were retrieved, with claim 8 truncated; the existence of further claims (and of any independent method claim) is unconfirmed.
4. Priority — unverified. Google Patents marks the 1996-03-13 priority as an assumption and does not name a parent application.
5. USPTO/CAFC primary-source certification not performed live. As in the earlier sections, I relied on USPTO-derived mirrors (Google Patents, Justia); I could not execute a direct PatentCenter or CAFC docket query in this session.

Cross-section consistency: Title, assignee, inventors, filing/issue dates, and legal status all agree with the previously generated Litigation, PTAB, Assignment History, Prior Art, and Obviousness sections. No contradiction identified.

I'll research litigation involving US patent 6492692 across patent litigation databases.

Let me search more targeted patent litigation databases.

Let me check a couple more specialized litigation sources.

Litigation Search: US Patent 6,492,692

Bottom line: I found no litigation — no district court case, ITC action, or Federal Circuit appeal — involving US Patent 6,492,692 ("Semiconductor integrated circuit and manufacturing method therefore").

What I searched

• General patent-litigation queries for the patent number in both formats ("6492692" and "6,492,692")
• Assignee/plaintiff-side queries (Seiko Instruments Inc.; the current listed assignee, Ablic Inc.)
• Docket/PACER-adjacent aggregator results (Justia Dockets, CourtListener/PACER Monitor, Unified Patents portal references) surfaced by the searches

Results

No case records were returned that name US 6,492,692 as a patent-in-suit. The only hits on the number itself were the patent's own bibliographic pages (Google Patents, Justia Patents, PatentLeaderboard) — not litigation filings.

Important cautions about false positives I encountered

Several search results contained similar-looking but unrelated numbers. I flag these so they are not mistaken for litigation on this patent:

Context relevant to any future litigation

• Prosecution history / ownership chain (from the Google Patents record): filed 1999-09-28 as US 09/407,382 (priority 1996-03-13); granted 2002-12-10; original assignee Seiko Instruments Inc.; reassigned to SII Semiconductor Corporation (2016-02-12); current listed assignee Ablic Inc.; legal status Expired – Lifetime (anticipated expiration 2017-03-12).
• Litigation-relevance note: Because the patent expired around March 2017, any infringement action would have had to be filed and reach judgment before expiration, and damages would be limited to pre-expiration conduct. This is consistent with the absence of any active case.
• Seiko Instruments' publicly reported enforcement activity (per SII's news page) concerns thermal printer mechanisms and design patents in China — not this US patent.
• I found no IPR/PGR, no ITC Section 337 investigation, and no Federal Circuit appeal referencing US 6,492,692.

Confidence and limitations

This conclusion is based on publicly indexed sources reachable via web search (Google Patents, Justia Dockets, PACER-adjacent aggregators, Federal Circuit briefing repositories). It is not a substitute for a paid, comprehensive search (e.g., Docket Navigator, LexisNexis PatentLitigation, or a full PACER/Unified Patents Portal query), which I could not fully execute here. If a definitive "no litigation" certification is needed, I recommend confirming via Docket Navigator or the Unified Patents litigation portal directly. I did not find any evidence of litigation, and I am stating that as a negative finding rather than asserting absolute certainty.

I'll verify the canonical "no proceedings on file" signal against what the web indexes, then report.

Let me run a few more targeted queries to confirm the negative finding.

Proceedings overview

Total AIA trial proceedings on US 6,492,692: 0 — no Inter Partes Review, no Post-Grant Review, and no Covered Business Method review has ever been filed against this patent. Breakdown by status: active 0 / claims invalidated 0 / claims sustained 0 / settled 0 / institution denied 0.

Bottom-line defensive posture for a defendant: the patent is not PTAB-hardened — it is PTAB-untested. There is no Final Written Decision to lean on, no claim-by-claim invalidation record, and no estoppel to inherit from an earlier petitioner. Equally, there is no adverse FWD that a plaintiff can point to as proof of survivability. The absence of any AIA challenge is the relevant signal here, and it is explained almost entirely by the patent's age and status (see Strategic summary). It should not be read as evidence that the claims are strong.

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Proceedings on file

None. The structured "PTAB proceedings on file" block — the canonical list sourced from the USPTO Open Data Portal — returns no AIA trial proceedings for US 6,492,692 as of the most recent ingest. Because there are no proceeding numbers to report, the prescribed per-proceeding template (### {PROCEEDING_NUMBER} — {Petitioner} v. {Patent Owner}) has no entries to fill, and I will not manufacture any. There is accordingly no judge panel, no petition ground, no institution decision, no FWD, no settlement, and no Federal Circuit appeal to describe for this patent.

What I did to try to falsify that negative finding

False-positive traps to avoid (these surfaced in my searches and are not this patent):

• US 8,288,269 — "Methods for Avoiding Parasitic Capacitance…" (Bell Semiconductor v. Microchip line; IPR2020-01693, IPR2021-00967, and the related '340 patent challenges). Different patent, different decade, different owner.
• US 6,437,692 — the SIPCO LLC wireless-mesh patent (SIPCO v. Acuity Brands, E.D. Tex.). Shares only the trailing digits.
• US 8,794,269 (IPR2023-01402, Omega Liner v. Buergofol) and US 9,279,263 and the '431 patent in the W.D. Tex. Cloudflare Fintiv briefing — all unrelated.

Where this sits on the AIA timeline

The AIA's IPR/PGR/CBM regimes did not exist for most of this patent's life. US 6,492,692 issued 2002-12-10 from an application filed 1999-09-28 (priority 1996-03-13). IPR became available 2012-09-16, roughly ten years into the patent's term. The CBM transitional program (which would not have applied here anyway — this is a semiconductor/bump-electrode patent, not a "financial product or service") sunset on 2020-09-16. So any AIA challenge would have had to be squeezed into the window from late 2012 until the patent's anticipated expiration on 2017-03-12 — a roughly 4.5-year window, during which the patent apparently attracted no filer, no defensive aggregator, and no district-court defendant willing to fund an IPR.

I note explicitly that the searches I can run here are the publicly indexed web plus the supplied ODP extract. I could not directly execute a live PTAB E2E case search by patent number. If a definitive certification is needed, verify at the PTAB E2E portal and the USPTO Open Data Portal before relying on this negative.

• PTAB E2E (search by patent number 6,492,692): https://ptacts.uspto.gov/ptabweb/
• USPTO Open Data Portal (AIA trial proceedings API): https://developer.uspto.gov/
• Google Patents (bibliographic and legal-status anchor): https://patents.google.com/patent/US6492692/en
• CourtListener (in the event any FWD or CAFC opinion exists): https://www.courtlistener.com/

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Strategic summary

Claim status: everything is UNTESTED. No claim of US 6,492,692 has been canceled, confirmed, or construed by the PTAB. The full claim set remains as issued on 2002-12-10, subject only to whatever ex parte prosecution history exists. There is no surviving-claim list to hand a defendant, because no claim was ever removed. Importantly, "untested" is not "hardened": a patent that was never challenged is simply a patent nobody bothered to challenge — here, most plausibly because it expired in March 2017 and its remaining commercial value lay in a handful of Japanese semiconductor manufacturers rather than in an enforcement campaign against an identifiable pool of US defendants. Compare the prior litigation finding in this analysis: no district court case, no ITC action, no Federal Circuit appeal. The pattern across every channel is non-use, which is consistent with a chip-design patent that was never asserted.

Estoppel landscape: essentially empty, which cuts both ways. Because there is no FWD, there is no § 315(e)(2) estoppel binding anyone — no petitioner, no privy, no real party in interest has been estopped from raising anything. That means a current or prospective defendant has the entire prior-art universe available: § 102 and § 103 grounds, § 112 grounds (which IPR cannot reach at all — written description, enablement, indefiniteness are only available in district court, the ITC, or a PGR), and any printed publication, public use, or on-sale bar theory. Conversely, a defendant cannot free-ride on an earlier petitioner's work product, expert declarations, or institution-stage concessions, because no such record exists. Note also the mirror-image risk: with no PTAB record, a district court has no FWD reference point, so claim construction and invalidity will be litigated from scratch.

Pattern signals: none of the usual ones are present. No repeat petitioner has filed multiple IPRs against this patent (there are zero). The patent owner has never appealed an FWD or an institution decision (there is nothing to appeal). There is no sign of a defensive aggregator such as Unified Patents in the chain — searches for the patent number on Unified's portal surfaced only a different Seiko Instruments/ABLIC family member (US 2004/0191967 A1), not this patent. Ownership history is benign and corporate: Seiko Instruments Inc. → SII Semiconductor Corporation (2016-02-12 reassignment) → current listed assignee ABLIC Inc., all within the same corporate lineage, with no signs of a shell assignee or litigation vehicle.

The decisive practical point is expiration. The Google Patents record lists legal status "Expired – Lifetime" with an anticipated expiration of 2017-03-12, and the 2017-03-12 entry in the transaction history is the anticipated-expiration event. As of today (2026-09-27), that is more than nine years past. An IPR can in principle be filed against an expired patent (the Board has instituted such proceedings where a parallel litigation or a live dispute justifies it), but there is no district-court case, no ITC investigation, and therefore no controversy to anchor one. A defendant receiving a demand letter on this patent today should treat the invalidity question as almost secondary: the threshold questions are whether the demand is time-barred, whether any accused conduct even falls inside the pre-expiration damages window, and whether the "patent" being asserted is actually this US patent rather than the unrelated Japanese JP 6492692 B2 or a similarly numbered family member.

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Recommended next steps

1. The absence of PTAB activity is the finding — state it plainly. No IPR, PGR, or CBM has ever been filed against US 6,492,692. The patent has never been tested at the Board. Do not let opposing counsel characterize this as "the patent has survived every challenge" — nothing was ever challenged.

2. Confirm the negative against primary sources before relying on it. My searches covered indexed web results and the supplied ODP extract; I could not run a live patent-number query in PTAB E2E. Verify at https://ptacts.uspto.gov/ptabweb/ and via the USPTO Open Data Portal. This is a low-cost, high-confidence check given the zero-hit pattern.

3. If you are a defendant: do not build a defense around an FWD that does not exist. There is no disposition to quote and no canceled claim to cite. Your invalidity case must be built fresh, and you should route § 112 and prior-public-use theories (unavailable in IPR) into district court or the ITC rather than assuming a PTAB proceeding will absorb them. A live IPR is theoretically possible on an expired patent, but only if a real controversy supports it — check whether one exists before budgeting for it.

4. Lead with the expiration and the demand-letter mismatch. With an anticipated expiration of 2017-03-12 and today's date being 2026-09-27, damages would be limited to pre-expiration conduct, and any assertion is likely to be stale. Verify the legal-status field directly on the patent's Google Patents page and via USPTO PatentCenter (https://patentcenter.uspto.gov/) before responding, and confirm the demand actually references US 6,492,692 rather than JP 6492692 B2, US 6,437,692, or US 8,288,269.

5. Note the cross-section consistency. This PTAB finding is consistent with the earlier litigation finding in this analysis: no district court case, no ITC action, no CAFC appeal, and no AIA trial — across every channel, the record is non-use. Treat that convergence as corroboration, but keep it labeled as a negative finding rather than an affirmative certification of the patent's validity or strength.

Confidence and limitations: High confidence in the zero-proceeding finding, based on (a) the canonical ODP-derived "no AIA trial proceedings" block and (b) four independent web searches that returned no proceeding naming this patent. I did not execute a live PTAB E2E or Docket Navigator query, so if a certification-grade answer is required, re-verify at the primary sources linked above. I have not fabricated any proceeding number, panel, ground, or disposition.

I'll research the assignment record for US 6,492,692 before reconstructing the chain.

Assignment & Ownership Chain — US 6,492,692

Verification entry point: https://assignmentcenter.uspto.gov/ (search by patent number 6492692; equivalent legacy interface at https://assignment.uspto.gov/patent/index.html). Google Patents legal-events mirror used as a secondary check: https://patents.google.com/patent/[US6492692B1](/patent/US6492692B1)/en#legalEvents

Disclosure up front: I could reach the event-level record (assignor → assignee → date) but not the reel/frame numbers for this patent. I am not inventing them. Where a field could not be verified I say "not verified" rather than filling it in. This matters for the NPE section below, because the correspondent-of-record field — the highest-value tell in this task — lives on the face of the reel/frame document, not in the indexed event feed.

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Inventors

Nine named inventors, all listed with a Chiba (JP) address at filing (Justia patent record; Google Patents bibliographic record):

Notes and pattern flags:

• All nine share the same corporate address (Chiba, c/o Seiko Instruments Inc.) — the classic single-employer R&D team signature. There is no mixed-employer or university/industry joint-inventorship pattern, and no inventor was a solo or near-solo filer.
• Nine inventors on one patent is itself anomalous and is explained by the specification: this is an omnibus filing that aggregates thermal-head driver output pads, high-withstand-voltage open-drain MISFETs, bump/barrier-metal structures, dummy bumps, protection-circuit grouping, scribe-line spacing, and flip-chip mounting into a single disclosure (see the "Definitions"/"the present invention relates to…" preamble block, which runs to a dozen distinct statements of invention). That is a portfolio-breadth filing, not a single-laboratory invention.
• Filing posture: filed 1999-09-28 as US 09/407,382 with a priority date of 1996-03-13, i.e. a continuation/divisional-type filing off an earlier 1996 priority. The 1996 priority is likely a Japanese Seiko Instruments filing, but I could not verify the priority document — treat as unconfirmed.
• Departure pattern: I found no evidence that any inventor departed Seiko Instruments within 12 months of filing. More importantly, the contrary is plausible: SII's semiconductor division (≈830–880 staff, the group that would contain these inventors) transferred as an intact unit into SII Semiconductor Corporation in the 2015–2016 carve-out (Seiko Holdings IR releases: https://www.seiko.co.jp/en/ir/assets/e_ir2015_0908a.pdf; https://www.ablic.com/dc-rebuild/en/semicon/news/2018/01/05/start/). That is an employee-block transfer with the business, not inventor attrition preceding a fire-sale. I have not verified individual inventor employment histories post-2016, so this is an inference from the corporate transaction, not a personnel record.

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Original assignee

Seiko Instruments Inc. (8 Nakase 1-chome, Mihama-ku, Chiba-shi, Chiba, Japan) — named on the face of the issued patent, per Justia ("Assignee: Seiko Instruments Inc. (Chiba)").

• Primary line of business: development, manufacture and sale of watches/finished goods and watch movements, semiconductors, electronic devices, and precision mechatronics products (Seiko Holdings IR, 2015-09-08). The semiconductor line was the relevant one here: EEPROM and analog power-management ICs, plus the thermal-head and LCD driver ICs described in this specification.
• Did it ship a product embodying the claims? Effectively yes, as a component supplier. The patent's own FIG. 10–17 disclosure describes a thermal-head driver IC with ≥50 open-drain output pads driving ≥5 mA per channel, and specifically reports a chip-width reduction from 0.45 mm to 0.3 mm and a >30% cost reduction versus the prior art. Seiko Instruments was a long-established thermal-head/LC driver IC vendor, so this is an operating-company product patent, not a paper asset. I have not independently audited a specific part-number datasheet, so treat the product mapping as "supported by the specification's own commercial framing" rather than a verified bill of materials.
• Current status of the original assignee: operating. Seiko Instruments Inc. remains a consolidated subsidiary of Seiko Holdings Corporation; it exited the semiconductor manufacturing business by carve-out, retaining 30% of the spun-off entity until 2020. No bankruptcy, no dissolution, no assignment-for-the-benefit-of-creditors anywhere in this chain.

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Assignment timeline

Event-level record retrieved. Reel/frame not verified — see caveat.

1996-03-13 — priority date (assumed, per Google Patents). Not an assignment event.
1999-09-28 — application US 09/407,382 filed by Seiko Instruments Inc. (routine employer-owned filing; no separate recorded inventor→company assignment surfaced for this application number).
2002-12-10 — patent granted.

2016-02-12 (recorded) — Reel not verified / Frame not verified

• Conveyance: Reassignment (recorded via USPTO Assignment Recordation; the Google Patents legal-event classification is "reassignment")
• Assignor: Seiko Instruments Inc. ("SEIKO INSTRUMENTS INC." per the Google Patents event text)
• Assignee: SII Semiconductor Corporation
• Correspondent: not verified — the indexed event feed does not expose the correspondent of record. This is the single most important missing field for the NPE screen; see signal 3 below.
• Execution date: not exposed in the indexed record. The transaction was agreed 2015-09-08 and the new company commenced operation 2016-01-05/01-2016, so a late-2015 execution / early-2016 recording is consistent, but I am not asserting an execution date.
• Context: internal corporate reorganization — business-unit carve-out with a co-investor, not a monetization transfer. SII Semiconductor was established September 2015 as a Seiko Instruments sub-subsidiary, with the Development Bank of Japan Inc. taking 40% (SII 60%) in January 2016 and succeeding SII's semiconductor business (Seiko Holdings IR 2015-09-08; ABLIC 2018-01-05 release; https://www.sii.co.jp/en/news/topics/2018/01/05/11656/).
• Supporting bulk record: Plainsite indexes a single omnibus "Patent Assignment from Seiko Instruments, Inc. to SII Semiconductor Corporation" covering a long list of SII semiconductor patents (assignment id 7383803, https://www.plainsite.org/patents/assignment.html?id=7383803). US 6,492,692 is consistent with such a portfolio-wide transfer, but I could not confirm its inclusion from the available snippet, so I am listing it as corroborating context, not as proof of a second record for this patent.

2018-01-05 — SII Semiconductor Corporation changed its trade name to ABLIC Inc. (name change only; same legal entity, same Chiba head office, DBJ 70% / SII 30%). Google Patents lists the current assignee as Ablic Inc., but its legal-events feed shows no separate recorded Change of Name assignment for this patent. Either (a) a Change of Name recording exists on a reel/frame not surfaced in the indexed feed, or (b) Google Patents is deriving "Ablic Inc." from the corporate name change rather than from a USPTO record. I could not determine which — flagging as an open item, because a pure name change carries no new reel/frame entry in some feeds.

2020-04-30 — ABLIC's shares moved into the MinebeaMitsumi group (SII transferred its 555,000 ABLIC shares / 30% stake to MinebeaMitsumi; Seiko Holdings annual securities report, https://www.seiko.co.jp/en/ir/2025/08/AnnualSecuritiesReport_2103.pdf). Critical nuance: this was a share-level transfer — the patent owner of record remains ABLIC Inc. Share deals do not generate USPTO assignment records, so the absence of a 2020 reel/frame entry is expected and is not a missing link.

2017-03-12 — anticipated expiration (per Google Patents legal status). Patent is Expired – Lifetime.

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Timeline diagram

timeline
    title Ownership of US 6492692
    1996 : Priority date claimed
         : Nine inventors at Seiko Instruments
    1999 : Application US 09 407 382 filed
    2002 : Patent granted to Seiko Instruments
    2015 : SII Semiconductor established
         : DBJ takes 40 percent stake
    2016 : Reassignment recorded to SII Semiconductor
    2018 : SII Semiconductor renamed ABLIC Inc
    2020 : ABLIC shares move to MinebeaMitsumi
    2017 : Patent expires

(Note on ordering: Mermaid timeline renders in list order, so the 2017 expiration is deliberately placed last rather than sorted numerically; the chain sequence above is the event-order reading of the record.)

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NPE / troll-pattern signals

1. Shell-entity transfer — NOT PRESENT.
The only post-issuance transfer (recorded 2016-02-12) runs Seiko Instruments Inc. → SII Semiconductor Corporation, a semiconductor manufacturer with a Chiba head office, 9,250 million yen capital, ~830–880 employees, and a stated mandate to "manufacture and sell semiconductors" (Seiko Holdings IR 2015-09-08). Its successor, ABLIC Inc., is an operating analog-semiconductor maker: "Design, development, manufacture, and sale of analog semiconductors" (https://www.ablic.com/dc-rebuild/en/semicon/news/2018/01/05/start/). No "IP / Holdings / Licensing / Ventures" suffix, no registered-agent address, no single-member LLC, no Delaware/Texas incorporation anywhere in the chain.

2. Known asserter in the chain — NOT PRESENT.
No assignee in the chain (Seiko Instruments Inc., SII Semiconductor Corporation, Ablic Inc., MinebeaMitsumi group) appears on the enumerated NPE list (Acacia, Marathon, Intellectual Ventures, IPNav, Wi-LAN, Mosaid/Conversant, Vringo, Pendrell, Innovatio, MPHJ, Lumen View, Round Rock, Erich Spangenberg entities) or on any Unified Patents / RPX high-frequency-plaintiff roster I encountered. Both current-chain entities are product companies. Note also: this is consistent with the earlier litigation screen finding no district court, ITC, or Federal Circuit case naming US 6,492,692 — an assertion history is the usual precondition for an NPE-list appearance.

3. Repeat correspondent across the chain — UNCLEAR, and the key gap.
I could not retrieve the correspondent of record for the 2016-02-12 recording, which is the only link in this chain where a correspondent would appear. What I can say:

• Prosecution counsel of record at issuance was Hogan & Hartson, LLP (Justia patent record: "Attorney, Agent or Law Firm: Hogan & Hartson, LLP") — an operating-company prosecution firm of that era, and a single appearance that is not a finding under this signal.
• A recurring Seiko Instruments recording correspondent does exist elsewhere: Adams & Wilks (Bruce L. Adams, 17 Battery Place, New York, NY), named as correspondent on a Seiko Instruments recording, USPTO Patent Assignment 33212/505 (assignor Aizawa, Kazuyuki, executed 2014-06-18; https://www.plainsite.org/patents/assignment.html?id=[6377987](/patent/6377987)). That is a different patent (app. 14/308,084) and a different direction (inventor → SII), so it is not evidence of recurrence in this chain.
• Conclusion: neither the prosecution firm nor the Seiko recording agent can be shown to recur on US 6,492,692's own records, because those records' correspondent field was not obtainable. Marked unclear, not present. To close this, pull the reel/frame PDF for the 2016-02-12 entry from Assignment Center and read field 5.

4. Cascading transfers — NOT PRESENT.
One post-issuance assignment in ~20 years of life (1999 → 2016), across a 17-year gap. No chained LLCs, no two-hop sequence within 24 months, no shared correspondent address across links. The 2018 rename is a name change, and the 2020 event is a share transfer, so neither adds a link.

5. Pre-litigation transfer — NOT PRESENT.
There is no infringement suit naming this patent (per the prior litigation screen), so the 2016-02-12 recording cannot be characterized as pre-litigation. A 2016 transfer followed by zero filings over the remaining ~13 months of enforceable life (patent expired 2017-03-12) is the opposite pattern.

6. Bankruptcy fire-sale — NOT PRESENT.
No Chapter 7/11 anywhere. The 2015–2016 semiconductor transfer was a negotiated carve-out with a financial co-investor, with SII retaining 60% at inception and 30% after 2018, and SII/SHD booking extraordinary income on the 2020 share sale (https://www.seiko.co.jp/en/ir/2019/12/18/e_ir2019_1217a.pdf). That is a value-realization reorg, not distress.

7. Privateering — NOT PRESENT.
No operating company → NPE transfer, and no NPE asserting on an operating company's behalf. The counterparty is a manufacturing JV partner (DBJ) and later an industrial acquirer (MinebeaMitsumi), not a licensing vehicle.

8. Defensive aggregator (anti-NPE) — NOT PRESENT.
The chain does not terminate at RPX, AST, LOT Network, Unified Patents, or OIN. It terminates at an operating analog-semiconductor maker inside the MinebeaMitsumi group.

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Verdict

Insufficient data — selected because the reel/frame-level records (including the correspondent field on the single post-issuance recording) could not be verified, and the instruction is to decide on reel/frame evidence rather than on naming. Substantively, everything I could verify points away from an NPE: the sole transfer (recorded 2016-02-12, Seiko Instruments Inc. → SII Semiconductor Corporation) is a business carve-out to an operating manufacturer with ~880 employees and a stated "manufacture and sell semiconductors" purpose, and the chain terminates at Ablic Inc., an operating analog-semiconductor maker under MinebeaMitsumi since the 2020-04-30 share transfer. The 2018-01-05 SII Semiconductor → ABLIC change is a name change only, and the 2020 event is a share-level deal that generates no USPTO record — so the absence of further entries is expected, not a gap in the chain. If forced into the NPE/non-NPE binary rather than the five labels above, the record supports operating-company ownership, non-asserting, consistent with the earlier finding of zero litigation and with expiration on 2017-03-12.

Two open items to close before this is filing-grade:

1. Pull the reel/frame PDF for the 2016-02-12 record in Assignment Center and record the reel/frame plus field 5 correspondent.
2. Determine whether a Change of Name recording (Seiko Instruments/SII → ABLIC) exists for this patent or whether Google Patents' "Ablic Inc." current-assignee entry is derived from the corporate rename. If no recording exists, the owner of record on the patent face may still read "SII Semiconductor Corporation" — a purely clerical artifact with no NPE implication, but worth stating accurately.

Contradiction check against the previously generated section: none. The prior litigation summary's ownership chain (filed 1999-09-28 as US 09/407,382; priority 1996-03-13; granted 2002-12-10; Seiko Instruments → SII Semiconductor 2016-02-12; Ablic Inc.; expired ~2017-03-12) matches the event-level record I independently reached. The prior section's caveat that its "no litigation" conclusion was a negative finding rather than a certification applies equally here.

I'll research the prior-art citations for US 6,492,692 via targeted searches.

Let me dig into the citation table for this specific patent.

Let me pull the full citation lists from Justia and Google Patents.

Prior-Art Analysis — US Patent 6,492,692

0. Verification of the target patent (literal identifiers)

I did not auto-correct any number. Note the search results also surfaced an unrelated US 4,187,xxx-family hit and a Swiss/Nevada docket ID "6492692" as flagged in the earlier litigation section; those are not this patent and are excluded.

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1. Important honesty flag before the citations

Two problems constrain this answer, and I am stating them explicitly rather than papering over them:

1. I could not retrieve the complete citation list. One search result (a Google Patents "Cited By" context page, US 7,768,137) confirms US 6,492,692's citation set is indexed as "Patent Citations (22)." However, the only directly retrieved "Referenced Cited" table (Justia, https://patents.justia.com/patent/6492692) was returned truncated by the search index — it showed an initial entry, an ellipsis ("…"), and then a further block of four entries. I therefore verified 4 U.S. patent citations and could not verify the remainder (up to ~18, which likely include foreign documents and/or other U.S. patents).
2. I will not invent the missing references. Sections below cover only what I directly observed in retrieved results.

Also for transparency: in this environment I could not open the USPTO Patent Public Search / PatentCenter record directly; I relied on USPTO-derived mirrors (Google Patents, Justia, uspto.report). Treat the table below as "verified as retrieved," not as a certified USPTO document download.

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2. Verified cited references

2.1 US 4,073,055 — Kimura et al. — Feb. 14, 1978

• Full citation: US 4,073,055, "Method for manufacturing semiconductor devices," Kimura et al., granted 1978-02-14.
• Description (from uspto.report record): Method for manufacturing semiconductor devices on an insulating (SOS) substrate; a second semiconductor region is formed so that it substantially surrounds the chip ("continuously or discontinuously around the semiconductor chip"). The second region serves two purposes: (a) as an endpoint indicator for contact-opening etch (the insulating film over it is removed simultaneously with the contact holes), and (b) as a mask-alignment/dicing-line mark. Discusses field-oxide-vs-dicing-line visibility.
• Potential §102 mapping: This is the nearest of the four to the patent's method-of-manufacture and chip-periphery subject matter — e.g., the claims/embodiments directed to a region at the chip edge, and to manufacturing steps before/at singulation (the present patent's "stepped region disposed on the substrate along a scribed surface on a side surface of the chip" concepts). However, it does not disclose bump electrodes over active transistor regions, barrier-metal interconnection through passivation openings, or the high-withstand-voltage drain construction — so no full-claim anticipation is supported by what I retrieved. Best characterized as background/§103-type art on chip-edge and manufacturing features.

2.2 US 5,451,549 — Oki et al. — Sep. 19, 1995

• Full citation: US 5,451,549, Oki et al., granted 1995-09-19.
• Description: I could confirm the number, date and inventor string ("Oki et al.") from the Justia cited-list, and that the same patent is cited in US 5,809,987 ("Apparatus for reducing damage to wafer cutting blades during wafer dicing"). Its presence in a wafer-dicing art family is consistent with a semiconductor-wafer-processing/dicing subject matter, but I did not retrieve its abstract or claims, so I cannot state its disclosure with confidence.
• Potential §102 mapping: Potentially relevant to the present patent's wafer-cutting / scribed-surface subject matter (the two-step cutting with lower first-step speed; stepped region deeper than the second-conductivity-type diffusion region). Flagged as unverified — I cannot responsibly name claims on a description I could not read.

2.3 US 5,542,174 — Chiu — Aug. 6, 1996 (Intel Corporation)

• Full citation: US 5,542,174, "Method and apparatus for forming solder balls and solder columns," George W. Chiu (Palo Alto, CA), assignee Intel Corporation (Santa Clara, CA), filed Sep. 15, 1994, granted Aug. 6, 1996, Appl. No. 8/307,893, Primary Examiner Carl J. Arbes. (Confirmed independently in the Justia record for US 5,542,174 itself.)
• Description: Method/apparatus for forming solder balls and solder columns; the height of the laminated solder column depends on process factors. Cited art in it includes US 3,292,240 (McNutt), US 4,545,610 (LaKritz), US 5,075,965 (Carey), US 5,186,383 / 5,269,453 (Melton), WO 89/02653, plus IBM TDB and Caulfield/Benanati/Acocella/Cole "Ceramic Ball Grid Arrays" (Semicon, San Francisco, Jun. 1993).
• Potential §102 mapping: This is the most on-point of the four for the patent's bump/solder-terminal concepts — e.g., claims/embodiments reciting a bump electrode of not less than 10 µm in height, a solder (Sn–Pb) plated bump, and solder-ball formation. But its subject matter is ball/column formation on a carrier, not a bump superposed on a drain region of an insulated-gate FET with a barrier metal overlaying a passivation opening. So it can at most be relevant to isolated bump-formation limitations, and does not anticipate any full claim I can see.
• §102 date note: With the stated 1996-03-13 priority, this patent's Aug. 6, 1996 grant falls after priority; it could only be prior art via its Sep. 15, 1994 filing date (pre-AIA §102(e)). I flag this as a date-sensitivity point a litigator would need to resolve against the actual priority chain.

2.4 US 5,840,593 — Leedy — Nov. 24, 1998

• Full citation: US 5,840,593, Leedy, granted 1998-11-24.
• Description: Confirmed number/date/inventor from the Justia cited-list only. Leedy's portfolio in this era generally concerns wafer-scale/three-dimensional integrated-circuit fabrication (thinning, bonding, interconnect through substrates). I did not retrieve this specific patent's text, so I am not asserting its disclosure.
• Potential §102 mapping: Possibly relevant to manufacturing/singulation and substrate-handling claim concepts, and to the patent's face-down (flip-chip) implementation method claims (resin flux-cored solder, heating from the chip rear, shield film). Unverified — no claim mapping asserted.

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3. Summary table

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4. Bottom line

• No confirmed §102 anticipation. On the record I actually retrieved, none of the four verified references discloses the patent's core combination — a bump/external terminal superposed over the drain region of a high-withstand insulated-gate FET, with a deep low-density first drain region plus a shallow high-density second drain region, a gate insulator of 100–250 Å, and a barrier metal passing through a passivation opening (≤900 µm²) on top of the active circuit. US 4,073,055 and US 5,542,174 are the most relevant, but to isolated features (chip-edge region; solder-ball formation), i.e. §103-combination material rather than clean §102 art.
• The citation list is incomplete in my working record. Google Patents indexes 22 citations for US 6,492,692; I directly verified 4 U.S. patents and could not retrieve the remaining entries (which likely include foreign patent documents and additional U.S. patents). Because the Justia "Referenced Cited" table came back truncated, I am not filling the gap with guesses.

5. Recommended next steps to close the gap (would require tools I don't have here)

1. Pull the machine-readable citation set from the USPTO Patent Public Search / PatentCenter record for application 09/407,382 (the "References Cited" / PTO-892 and the patent front page), which will enumerate all 22 items including foreign documents.
2. Retrieve the file wrapper for 09/407,382 — the examiner's applied references and any §102/§103 rejections are the best evidence of which claims each reference was actually mapped against.
3. Confirm the priority chain (the 1996-03-13 date is flagged by Google Patents as an assumption, and the 1999-09-28 filing suggests a continuation/divisional), because it controls whether the 1995–1998 references are prior art at all.

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Confidence: High on the patent's identity and bibliographic data (corroborated across Google Patents, Justia, patentleaderboard). High that I found no confirmed §102 anticipation among verified references. Low-to-moderate on completeness of the prior-art set — the 22-item citation list was only partially retrievable, and I have explicitly declined to fabricate the missing ~18 entries. Any "no anticipation" statement here is a negative finding on retrieved evidence, not a certification.

I'll research the cited prior art and prosecution record for US 6,492,692 before running the §103 analysis.

Obviousness Analysis — US 6,492,692 B1 under 35 U.S.C. § 103

Caveat up front on the source instruction. You asked me to "use the results from the Prior Art section of this page." The only "Prior Art" content exposed on the US6492692 Google Patents record as I retrieved it is the algorithmic/indexing block — prior-art keywords: integrated circuit, electrode, semiconductor integrated, region, bump — plus prior art date: 1996‑03‑13. No CPC-driven "Prior Art" list of references was retrievable from that section. I therefore supplement it with the "Referenced Cited / U.S. Patent Documents" list from the same record (retrieved via the Justia mirror of the same patent), and I flag every place where I am inferring rather than reading.

Source: https://patents.google.com/patent/[US6492692B1](/patent/US6492692B1)/en · https://patents.justia.com/patent/[6492692](/patent/6492692)

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1. Governing legal standard

• 35 U.S.C. § 103, as construed in Graham v. John Deere Co., 383 U.S. 1 (1966) (scope/content of prior art; differences; PHOSITA level; secondary considerations) and KSR Int'l Co. v. Teleflex Inc., 550 U.S. 398 (2007).
• From KSR, the rationales most in play here are:
  • (A) combining prior-art elements according to known methods to yield predictable results;
  • (B) "mere duplication of parts" / arrangement of parts — a structure known in the art altered by a predictable spatial rearrangement;
  • (C) "a known technique … applied to a known device … to yield predictable results" (the pad/bump-over-active-region technique applied to a known high-voltage open-drain driver);
  • (D) design incentives and market demand (chip-area/cost pressure in pad-limited driver ICs).
• Analogous art: all of the references below are from the same field of endeavor (semiconductor integrated circuits, package-level interconnection, and wafer processing), so they are presumptively analogous. In re Bigio / In re Clay.
• PHOSITA (proposed): a B.S.-level electrical engineer or materials engineer with ~3–5 years in IC layout and wafer-level bump/solder processing, familiar with passivation opening design, LDD/DDD high-voltage drain structures, and flip-chip/face-down mounting — a level consistent with the 1996–1999 timeframe and with the declarant-quality knowledge implied by a nine-inventor team at a driver-IC manufacturer.

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2. What claims 1–8 actually require

Per the previously generated section, claim 1 is the sole independent claim among claims 1–8 verified; claims 2–4 and 6–8 depend from claim 1, and claim 5 depends from claim 1. Claim 1 requires, in substance:

The single substantive difference over the applicant's own admitted prior art is element 1.5 — i.e., where the passivation opening (and hence the pad/bump) sits relative to the transistor's high-density drain. Everything else in claim 1 is described in the '692 specification itself as the conventional structure of FIG. 2 (drain regions 3A/3B, Al pad 9, contact 12, passivation 10).

This is the classic setup for a § 103 "arrangement of parts" rejection.

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3. Prior art of record on this patent

References cited on the face of US 6,492,692 (from the "Referenced Cited — U.S. Patent Documents" list; the list as surfaced was elided, so treat as partial):

Forward citations (later art citing the '692), useful only as evidence of how the field developed around it: US 7,420,280 ("Reduced stress under bump metallization structure" — vias through the passivation that overlay and expose portions of the same contact pad, with a unified metallization pad filling the vias) and US 8,674,507 ("Wafer level processing method and structure to manufacture two kinds of interconnects, gold and solder, on one wafer"). These show that the multiple-opening/bump-over-active region concept became a routine packaging technique. They are not § 102/§ 103 art against the '692 (later issue dates), but they are probative of what a PHOSITA regarded as conventional.

Honest limitation: I retrieved the full citation data (number/date/inventor) for these four references, and descriptive text only for US 4,073,055. I did not retrieve the specifications of US 5,451,549, US 5,542,174, or US 5,840,593 in this session. Any statement about what those three teach would be inference, not a reading — I flag it as such and do not build the core rejection on them.

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4. Claim 1 element-by-element mapping

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5. Obviousness combinations

Combination A (primary): AAPA + bump-over-active-region art

Teachings combined

1. Applicant's Admitted Prior Art ("AAPA") — the '692 specification's own FIG. 2 and accompanying text describe a thermal-head driver output stage consisting of: a high-withstand MOS switch with a two-part drain (low-density 3B + high-density 3A), an aluminum pad 9 connected to the high-density drain through a contact 12, a final passivation film 10 perforated over the pad, and an external terminal (bonded wire or bump) on the perforation — with the transistor and pad placed side-by-side in two dimensions. An applicant's admitted prior art is properly treated as prior art for § 103. In re Nomiya; In re Font.
2. Bump-over-active-region art — the practice of forming a solder/gold bump directly over the underlying semiconductor element (through a passivation opening located above the element, with a barrier metal under the bump), as represented by the cited Oki '549 / Chiu '174 references and corroborated as conventional by the later-cited US 7,420,280 and US 8,674,507.

Result — The combination yields each element of claim 1. Element 1.5 (passivation opening superposed on the second, high-density drain region) is reached by locating the known pad/bump stack over the known high-voltage drain, which is precisely the "arrangement of parts" scenario.

Why a PHOSITA would combine them (motivation)

• Chip area is dominated by the pads. The '692 specification itself states the external-terminal area rate "is not less than 20%" of the chip, and the earlier summary notes a ~30% pad-area figure — i.e., an express, self-identified cost driver.
• The product class demands it. A thermal-head driver is an extremely elongated chip (the '692 states the chip is ≥1 cm long at 100 µm pad pitch, and that conventional width dropped from 0.45 mm to 0.3 mm by stacking) with dozens of outputs. Any layout that consumes pad area inside the existing transistor footprint produces a direct, predictable yield-per-wafer gain.
• Bump-on-active was itself the known technique. Once a ductile plating-grown bump (the '692 uses ≥10 µm) is interposed between the package substrate and the IC, the mechanical-stress reason for keeping the pad off the active area is removed — the '692 says so in terms ("[t]he thick bump relieves the stress added to the integrated circuit at the time of the testing and the implementation, which reduces the stress added to the integrated circuit to arrange the transistors closer to the pad region than before"). That is the stated rationale for the combination, and it is an engineering explanation, not an unexpected result.
• KSR rationale (C): applying the known bump-over-active-region technique to a known open-drain high-voltage driver is "the application of a known technique to a known device ready for improvement, to yield predictable results."

Defensive posture if challenged: the rejection does not depend on Oki or Chiu specifically; the field knowledge that a bumped pad may be placed over active circuitry (as reflected in the later-cited US 7,420,280 / US 8,674,507) supplies element 1.5, and the AAPA supplies elements 1.1–1.4, 1.6.

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Combination B (alternative): high-voltage drain art + bump/BOA art

If the AAPA is treated narrowly (e.g., if the applicant argues FIG. 2 is only a generalized illustration), the same result is reached from any reference disclosing a double-diffused/LDD high-withstand MOS drain (the most heavily populated prior-art category in this field as of the 1996 priority date) combined with the bump-over-active-region art. The motivation is identical (area reduction in a pad-limited driver IC), and the combination is a substitution of one known layout for another.

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Combination C (dependent claims)

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Combination D (for the scrubbed-surface / stepped-region disclosure)

For the wafer-cutting and chip-corner aspects the specification discusses (FIGS. 62–65: cutting at a lower first speed then higher second speed; a stepped region along the scribed surface deeper than the second-conductivity-type diffusion region), US 4,073,055 (Kimura et al.) is directly relevant: it teaches removing the field oxide film along the dicing lines, using the exposed dicing-line region as a mask-alignment mark, and using the same etch step that opens contact holes to expose a surrounding second semiconductor region as a process-endpoint indicator. A PHOSITA seeking to reduce the diffusion-region-to-scribed-surface offset (the '692's stated 40 µm drawback, reduced by its "stepped region") would look to dicing-line structures of exactly this kind. I note expressly that the resulting claim coverage here is uncertain for the reason given in § 9.

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6. KSR rationales, summarized

1. Predictable result of a known spatial rearrangement — moving a known pad/bump/opening stack from beside the transistor to over the drain is arrangement-of-parts, not a new principle of operation; the electrical function (drain → metal → bump → external) is unchanged.
2. Known technique applied to a known device — bump-on-active in a high-voltage open-drain driver.
3. Market/cost incentive, expressly articulated in the specification — pad area ~20–30% of a long, narrow, high-volume driver chip.
4. Design choice / optimization — 2–4 µm wiring thickness; pad-vs-wiring naming; exclusion of the gate from the superposed area.
5. "Finite number of identified, predictable solutions" — given a pad-limited, elongated driver layout, the available area-reduction moves were (a) shrink pad pitch, (b) stagger, (c) stack the pad on the circuit. The '692 itself pursues (b) and (c) in different claims.

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7. Rebuttal / arguments for non-obviousness (to be weighed)

A rigorous analysis must present the other side; these are the arguments the patent owner would and did effectively make:

1. The specific combination of a high-withstand drain under a superposed passivation opening was not shown. The cited references of record are bump/terminal-formation art (Oki, Chiu) and wafer-processing art (Kimura, Leedy). None of them, on the record I could retrieve, addresses the layout of a double-diffused high-voltage drain beneath a pad. The examiner allowed claim 1 with these references on the face.
2. The stress problem was a recognized teaching-away. The '692 specification describes passivation cracking and polysilicon-resistor value shift caused by bonding/bump pressure when films are formed below the pad. If the art appreciated that pads over active regions damage the underlying films, a PHOSITA might have avoided the claimed arrangement absent the thick (>10 µm) columnar plating-grown bump — which the '692 identifies as the enabling element.
3. The electrical-result argument. The '692 asserts that superposing the pad on the drain lets the gate-to-drain-contact distance grow, raising the electrostatic-discharge withstand voltage, and thereby permits thinning the gate insulator to 100–250 Å. That is an asserted functional consequence of the layout. Its weight depends on whether the relationship is shown to be unexpected versus merely a predictable consequence of moving the contact away from the gate — I read it as the latter (longer gate-to-contact spacing ⇒ higher ESD threshold is well-understood), but the applicant would contest that.
4. Negative limitation (claim 5) — express exclusion of the gate electrode from the superposed region evidences a deliberate design rule, which some panels treat as a narrowing that raises the non-obviousness bar for the combination as a whole.

My assessment: arguments (1) and (2) are real but addressable; (3) and (4) are weak. On the record available, claims 1–8 would more likely than not be held obvious over AAPA (FIG. 2 of the '692) in view of bump-over-active-region art, with the dependent claims obvious as design choices — provided the effective filing date supports the references relied upon (see § 8).

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8. A threshold issue the record forces: which date governs?

Google Patents lists the filing date as 1999-09-28 (application 09/407,382) and the priority date as 1996-03-13, characterizing the priority date as an assumption and not enumerating any parent application. That produces a date problem that materially affects the § 103 analysis:

• If the claims are entitled to 1996-03-13, then US 5,542,174 (issued Aug. 6, 1996) and US 5,840,593 (issued Nov. 24, 1998) postdate that critical date. They would not be § 102(b) art; they could only be § 102(e) art if their filings predate the critical date — which I have not verified. (US 5,451,549, issued Sep. 19, 1995, and US 4,073,055, issued 1978, are safe.)
• If the claims are entitled only to the 1999-09-28 filing date (e.g., because claim 1's "superposed opening" subject matter lacks § 112 support in the 1996-03-13 disclosure), then all four cited references are prior art, and the rejection space widens considerably.
• The apparent 1996→1999 gap is also consistent with the '692 being a continuation/divisional — but the record I retrieved does not name the parent, so I do not assert a specific § 120/§ 119 lineage.

Recommendation: before relying on Oki '549 or Chiu '174 as the primary secondary reference in a rejection, verify (i) the parent-application chain, and (ii) the filing dates behind US 5,542,174 and US 5,840,593, in USPTO PatentCenter / Global Dossier.

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9. What I could not verify (explicit)

• The "Prior Art" tab of the Google Patents page beyond its keywords and prior-art date. My retrieval exposed only integrated circuit, electrode, semiconductor integrated, region, bump and 1996-03-13. A CPC "Prior Art" hit list was not retrievable.
• The complete "Referenced Cited" list. The list surfaced with an elision between US 4,073,055 and US 5,451,549; additional references may exist that I did not see. The four references are therefore a floor, not a ceiling.
• The specifications of US 5,451,549 (Oki), US 5,542,174 (Chiu), US 5,840,593 (Leedy). I have only number/date/inventor. Do not attribute specific teachings to them without reading them.
• Claim count and whether a method independent claim exists. Consistent with the earlier section: only claims 1–8 were verified; claim 1 appears to be the sole independent claim. The title's "manufacturing method therefore" subject matter (dicing, bump formation, face-down mounting, hot-wind reflow) is disclosed but not confirmed to be claimed in the '692 — if no method claim issued, Combination D above is directed at disclosure, not at claim scope.
• Priority chain and § 102(e) dates — see § 8.
• No litigation, IPR/PGR, or ITC record was found (per the earlier section); that remains a negative finding from indexed public sources, not a certification.

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Bottom line

• Claim 1 differs from the patent's own admitted prior art (FIG. 2) in essentially one respect: the passivation opening — and thus the pad/bump — is superposed on the high-density drain region instead of sitting beside the transistor. That is an arrangement of parts.
• Adding the well-established technique of forming a bump over the active circuit region (cited on the face as Oki '549 / Chiu '174; corroborated as conventional by later art such as US 7,420,280 and US 8,674,507) supplies the missing element, and the specification itself supplies the motivation (pad area ≈20–30% of a long, narrow, cost-sensitive thermal-head driver; thick bump relieves the stress that previously kept pads off active devices).
• Claims 2–4 and 6–8 (pad, barrier metal, 2–4 µm wiring) are conventional bump-stack features or optimization of a known parameter; claim 5 is a negative layout limitation reached by routine design choice.
• Net: on the record available, a § 103 rejection of claims 1–8 is sustainable — but the analysis hinges on the effective filing date (§ 8) and on actually reading the three references whose texts I could not retrieve (§ 9). Treat the conclusion as a well-supported prima facie case, not a final determination.