US 10025731

US patent 10025731, titled "Memory module and circuit providing load isolation and noise reduction," was assigned to Netlist Inc. The inventors are Hyun Lee, Jayesh R. Bhakta, Jeffrey C. Solomon, Mario Jesus Martinez, and Chi-She Chen. The patent was filed on May 18, 2015, and issued on July 17, 2018.

Abstract:
The patent describes a memory module with a printed circuit board (PCB) that includes at least one connector for a computer system's memory controller. This module features multiple memory devices on the PCB and a circuit. The circuit has a first set of bi-directional ports connected to at least one memory device, and a second set of bi-directional ports connected to the connector. A switching circuit within the module selectively links ports from the second set to ports from the first set. Crucially, each port in both sets incorporates a correction circuit designed to reduce noise in signals transmitted between these port sets.

Plain-Language Overview of Independent Claims:

• Claim 1 (Memory Module): This claim describes a memory module that features a circuit board (PCB) with a connector to attach to a computer's memory controller. The module also has several memory chips on the board. A key component is a specialized circuit that has two sets of ports: one set connects to the memory chips, and the other connects to the module's main connector. This circuit can selectively link these two sets of ports using a "switching sub-circuit." Additionally, each port in both sets includes a "correction circuit" to reduce unwanted electrical noise in the signals passing through them.

• Claim 10 (Method of Use): This claim outlines a method for operating the memory module described in Claim 1. The method involves providing such a memory module. Then, it requires "activating" the circuit to perform two main functions: first, to selectively connect the internal memory chips to the external memory controller through the specified ports, and second, to activate the built-in correction circuits to reduce signal noise.

• Claim 17 (Circuit): This claim focuses specifically on the circuit component itself, rather than the entire memory module. It describes a circuit designed to be placed on a PCB. This circuit has a first set of bi-directional ports intended to connect to memory devices, and a second set of bi-directional ports intended to connect to a main connector that interfaces with a computer's memory controller. Like in Claim 1, it includes a switching sub-circuit for selective coupling between these port sets and a correction circuit in each port to reduce signal noise.

• Claim 20 (General Circuit): This claim describes a more general version of the circuit, not limited specifically to memory devices. It details a circuit with a first set of bi-directional ports configured to connect to multiple "subsystems" (which could be memory devices or other components). It also has a second set of bi-directional ports configured to connect to one or more other "subsystems." Similar to the other claims, this circuit includes a switching sub-circuit for selective port coupling and a noise-reducing correction circuit within each port.

Legal Status and Litigation:
US10025731B1 is currently active and is scheduled to expire on July 30, 2029.
The patent family is involved in ongoing litigation:

• A US case was filed in the Texas Eastern District Court (case number 2:25-cv-00557).
• The first worldwide family litigation has been filed.
• Another US case was filed in the Delaware District Court (case number 1:25-cv-00863).
• A US case was filed with the International Trade Commission (case number 337-TA-1472).
• A PTAB case, IPR2025-01431, was filed and is currently pending (Instituted).
  No specific CAFC 2026 dockets were found for US10025731 directly in the provided authoritative patent text or through a targeted search for "US10025731 CAFC 2026". However, given the active PTAB IPR and ongoing district court cases, appeals to the CAFC in 2026 or later are possible depending on the progression of these cases.US patent 10025731, titled "Memory module and circuit providing load isolation and noise reduction," was assigned to Netlist Inc. The inventors are Hyun Lee, Jayesh R. Bhakta, Jeffrey C. Solomon, Mario Jesus Martinez, and Chi-She Chen. The patent was filed on May 18, 2015, and issued on July 17, 2018.

Abstract:
The patent describes a memory module with a printed circuit board (PCB) that includes at least one connector configured to be operatively coupled to a memory controller of a computer system. This module features a plurality of memory devices on the PCB and a circuit. The circuit has a first set of bi-directional ports operatively coupled to at least one memory device, and a second set of bi-directional ports operatively coupled to the at least one connector. A switching circuit within the module is configured to selectively operatively couple one or more ports of the second set of ports to one or more ports of the first set of ports. Importantly, each port in both the first set and the second set comprises a correction circuit designed to reduce noise in one or more signals transmitted between these port sets.

Plain-Language Overview of Independent Claims:

• Claim 1 (Memory Module): This claim describes a memory module comprising a circuit board (PCB) equipped with a connector for attachment to a computer system's memory controller. The module also contains multiple memory devices mounted on this PCB. A central feature is a circuit that includes a first set of bi-directional ports connected to at least one memory device each, and a second set of bi-directional ports connected to the main connector. This circuit further incorporates a "switching sub-circuit" which can selectively connect ports from the second set to ports from the first set. Additionally, each port within both the first and second sets is equipped with a "correction circuit" to reduce noise in signals transmitted between these port sets.

• Claim 10 (Method of Using a Memory Module): This claim outlines a method for operating a memory module within a computer system. The method begins by providing a memory module that includes a PCB with a connector (for a memory controller) and multiple memory devices. This module also features a circuit as described in Claim 1, with its first and second sets of bi-directional ports, switching capabilities, and correction circuits. The method then involves "activating" this circuit to perform two actions: first, to selectively connect at least one port from the second set to at least one port from the first set (thereby establishing communication paths); and second, to activate the circuit to reduce noise in the signals transmitted.

• Claim 17 (Circuit for a Memory Module): This claim describes a specific circuit for use in a memory module. The circuit comprises a first set of bi-directional ports, each configured to connect to at least one memory device on a printed circuit board. It also includes a second set of bi-directional ports, each configured to connect to at least one connector on the printed circuit board, where this connector is designed to couple with a computer system's memory controller. The circuit further has a "switching sub-circuit" for selectively linking ports from the second set to ports from the first set. Each port in both sets is provided with a correction circuit to reduce noise in the transmitted signals.

• Claim 20 (General Circuit for Subsystems): This claim presents a more generalized circuit. It comprises a first set of bi-directional ports, each configured to be operatively coupled to at least one subsystem from a plurality of subsystems. It also includes a second set of bi-directional ports, each configured to be operatively coupled to at least one subsystem from one or more other subsystems. This general circuit also features a "switching sub-circuit" for selectively operatively coupling ports from the second set to ports from the first set. Additionally, each port in both the first and second sets contains a correction circuit to reduce noise in signals transmitted between the port sets.

Legal Status and Litigation:
US10025731B1 is currently active and is projected to expire on July 30, 2029.
The patent family is involved in multiple litigation proceedings:

• A US case (2:25-cv-00557) has been filed in the Texas Eastern District Court.
• The first worldwide family litigation for this patent has been initiated.
• Another US case (1:25-cv-00863) has been filed in the Delaware District Court.
• A US case (337-TA-1472) is pending before the International Trade Commission.
• A PTAB (Patent Trial and Appeal Board) case, IPR2025-01431, has been filed and is currently in the "Instituted" stage.

As of April 26, 2026, no specific dockets for US10025731 were found in the CAFC 2026 dockets. However, given the ongoing district court and PTAB proceedings, appeals to the CAFC in 2026 or later are a possibility as these cases progress.