US 10025731

US patent 10025731, titled "Memory module and circuit providing load isolation and noise reduction," was assigned to Netlist Inc. The inventors are Hyun Lee, Jayesh R. Bhakta, Jeffrey C. Solomon, Mario Jesus Martinez, and Chi-She Chen. The patent was filed on May 18, 2015, and issued on July 17, 2018.

Abstract:
The patent describes a memory module with a printed circuit board (PCB) that includes at least one connector for a computer system's memory controller. This module features multiple memory devices on the PCB and a circuit. The circuit has a first set of bi-directional ports connected to at least one memory device, and a second set of bi-directional ports connected to the connector. A switching circuit within the module selectively links ports from the second set to ports from the first set. Crucially, each port in both sets incorporates a correction circuit designed to reduce noise in signals transmitted between these port sets.

Plain-Language Overview of Independent Claims:

• Claim 1 (Memory Module): This claim describes a memory module that features a circuit board (PCB) with a connector to attach to a computer's memory controller. The module also has several memory chips on the board. A key component is a specialized circuit that has two sets of ports: one set connects to the memory chips, and the other connects to the module's main connector. This circuit can selectively link these two sets of ports using a "switching sub-circuit." Additionally, each port in both sets includes a "correction circuit" to reduce unwanted electrical noise in the signals passing through them.

• Claim 10 (Method of Use): This claim outlines a method for operating the memory module described in Claim 1. The method involves providing such a memory module. Then, it requires "activating" the circuit to perform two main functions: first, to selectively connect the internal memory chips to the external memory controller through the specified ports, and second, to activate the built-in correction circuits to reduce signal noise.

• Claim 17 (Circuit): This claim focuses specifically on the circuit component itself, rather than the entire memory module. It describes a circuit designed to be placed on a PCB. This circuit has a first set of bi-directional ports intended to connect to memory devices, and a second set of bi-directional ports intended to connect to a main connector that interfaces with a computer's memory controller. Like in Claim 1, it includes a switching sub-circuit for selective coupling between these port sets and a correction circuit in each port to reduce signal noise.

• Claim 20 (General Circuit): This claim describes a more general version of the circuit, not limited specifically to memory devices. It details a circuit with a first set of bi-directional ports configured to connect to multiple "subsystems" (which could be memory devices or other components). It also has a second set of bi-directional ports configured to connect to one or more other "subsystems." Similar to the other claims, this circuit includes a switching sub-circuit for selective port coupling and a noise-reducing correction circuit within each port.

Legal Status and Litigation:
US10025731B1 is currently active and is scheduled to expire on July 30, 2029.
The patent family is involved in ongoing litigation:

• A US case was filed in the Texas Eastern District Court (case number 2:25-cv-00557).
• The first worldwide family litigation has been filed.
• Another US case was filed in the Delaware District Court (case number 1:25-cv-00863).
• A US case was filed with the International Trade Commission (case number 337-TA-1472).
• A PTAB case, IPR2025-01431, was filed and is currently pending (Instituted).
  No specific CAFC 2026 dockets were found for US10025731 directly in the provided authoritative patent text or through a targeted search for "US10025731 CAFC 2026". However, given the active PTAB IPR and ongoing district court cases, appeals to the CAFC in 2026 or later are possible depending on the progression of these cases.US patent 10025731, titled "Memory module and circuit providing load isolation and noise reduction," was assigned to Netlist Inc. The inventors are Hyun Lee, Jayesh R. Bhakta, Jeffrey C. Solomon, Mario Jesus Martinez, and Chi-She Chen. The patent was filed on May 18, 2015, and issued on July 17, 2018.

Abstract:
The patent describes a memory module with a printed circuit board (PCB) that includes at least one connector configured to be operatively coupled to a memory controller of a computer system. This module features a plurality of memory devices on the PCB and a circuit. The circuit has a first set of bi-directional ports operatively coupled to at least one memory device, and a second set of bi-directional ports operatively coupled to the at least one connector. A switching circuit within the module is configured to selectively operatively couple one or more ports of the second set of ports to one or more ports of the first set of ports. Importantly, each port in both the first set and the second set comprises a correction circuit designed to reduce noise in one or more signals transmitted between these port sets.

Plain-Language Overview of Independent Claims:

• Claim 1 (Memory Module): This claim describes a memory module comprising a circuit board (PCB) equipped with a connector for attachment to a computer system's memory controller. The module also contains multiple memory devices mounted on this PCB. A central feature is a circuit that includes a first set of bi-directional ports connected to at least one memory device each, and a second set of bi-directional ports connected to the main connector. This circuit further incorporates a "switching sub-circuit" which can selectively connect ports from the second set to ports from the first set. Additionally, each port within both the first and second sets is equipped with a "correction circuit" to reduce noise in signals transmitted between these port sets.

• Claim 10 (Method of Using a Memory Module): This claim outlines a method for operating a memory module within a computer system. The method begins by providing a memory module that includes a PCB with a connector (for a memory controller) and multiple memory devices. This module also features a circuit as described in Claim 1, with its first and second sets of bi-directional ports, switching capabilities, and correction circuits. The method then involves "activating" this circuit to perform two actions: first, to selectively connect at least one port from the second set to at least one port from the first set (thereby establishing communication paths); and second, to activate the circuit to reduce noise in the signals transmitted.

• Claim 17 (Circuit for a Memory Module): This claim describes a specific circuit for use in a memory module. The circuit comprises a first set of bi-directional ports, each configured to connect to at least one memory device on a printed circuit board. It also includes a second set of bi-directional ports, each configured to connect to at least one connector on the printed circuit board, where this connector is designed to couple with a computer system's memory controller. The circuit further has a "switching sub-circuit" for selectively linking ports from the second set to ports from the first set. Each port in both sets is provided with a correction circuit to reduce noise in the transmitted signals.

• Claim 20 (General Circuit for Subsystems): This claim presents a more generalized circuit. It comprises a first set of bi-directional ports, each configured to be operatively coupled to at least one subsystem from a plurality of subsystems. It also includes a second set of bi-directional ports, each configured to be operatively coupled to at least one subsystem from one or more other subsystems. This general circuit also features a "switching sub-circuit" for selectively operatively coupling ports from the second set to ports from the first set. Additionally, each port in both the first and second sets contains a correction circuit to reduce noise in signals transmitted between the port sets.

Legal Status and Litigation:
US10025731B1 is currently active and is projected to expire on July 30, 2029.
The patent family is involved in multiple litigation proceedings:

• A US case (2:25-cv-00557) has been filed in the Texas Eastern District Court.
• The first worldwide family litigation for this patent has been initiated.
• Another US case (1:25-cv-00863) has been filed in the Delaware District Court.
• A US case (337-TA-1472) is pending before the International Trade Commission.
• A PTAB (Patent Trial and Appeal Board) case, IPR2025-01431, has been filed and is currently in the "Instituted" stage.

As of April 26, 2026, no specific dockets for US10025731 were found in the CAFC 2026 dockets. However, given the ongoing district court and PTAB proceedings, appeals to the CAFC in 2026 or later are a possibility as these cases progress.

Known litigation involving US patent 10025731 includes the following:

• Jurisdiction: Texas Eastern District Court

  • Case Number: 2:25-cv-00557
  • Filing Date: Not explicitly provided in the available information.
  • Plaintiff(s): Not explicitly provided in the available information.
  • Defendant(s): Not explicitly provided in the available information.
  • Outcome or Current Status: Active, indicated as "Critical" litigation.

• Jurisdiction: Delaware District Court

  • Case Number: 1:25-cv-00863
  • Filing Date: Not explicitly provided in the available information.
  • Plaintiff(s): Not explicitly provided in the available information.
  • Defendant(s): Not explicitly provided in the available information.
  • Outcome or Current Status: Active litigation.

• Jurisdiction: International Trade Commission (ITC)

  • Case Number: 337-TA-1472
  • Filing Date: Not explicitly provided in the available information.
  • Plaintiff(s): Not explicitly provided in the available information.
  • Defendant(s): Not explicitly provided in the available information.
  • Outcome or Current Status: Active litigation.

• Jurisdiction: Patent Trial and Appeal Board (PTAB)

  • Case Number: IPR2025-01431
  • Filing Date: Not explicitly provided in the available information.
  • Plaintiff(s) / Petitioner: Not explicitly provided in the available information.
  • Defendant(s): Not explicitly provided in the available information.
  • Outcome or Current Status: Pending - Instituted.

Proceedings overview

One AIA trial proceeding is on file for US patent 10025731, which is currently in "Trial Instituted" status. This means that at least some claims of the patent are actively being challenged and reviewed for patentability by the PTAB. For a defendant, this indicates that the patent's validity is currently under scrutiny, which may weaken the patent owner's assertion posture.

IPR2025-01431 — [[[Samsung Electronics Co.](/litigations/by-defendant/Samsung%20Electronics%20Co.), Ltd.](/litigations/by-plaintiff/Samsung%20Electronics%20Co.%2C%20Ltd.) et al.](/litigations/by-plaintiff/Samsung%20Electronics%20Co.%2C%20Ltd.%20et%20al.) v. Netlist Inc.

• Type: Inter Partes Review
• Filed: 2025-08-29
• Status: Trial Instituted. The Patent Trial and Appeal Board (PTAB) has decided to initiate a review of at least some of the challenged claims of US10025731.
• Judge panel: The specific judge panel for this proceeding is not available in the provided search results. The USPTO Director now holds authority over institution decisions, consulting with at least three PTAB judges, but the ultimate decision rests with the Director.
• Petition grounds: The specific claims challenged, the prior art cited, and the statutory basis (§ 102 / § 103 / § 112) for the petition grounds are not detailed in the provided search results.
• Institution decision: The status "Trial Instituted" confirms a decision has been issued. However, the exact date of institution and the specific reasoning or claims instituted are not available in the provided search results. The last modification date on file for this IPR is 2026-05-11, which may be close to the institution date.
• Final Written Decision (if issued): Not yet issued, as the status is "Trial Instituted."
• Settlement / termination: Not applicable at this stage, as the proceeding is active.
• Appeal: Not applicable at this stage.
• Defensive value: This active IPR indicates that the patent's validity is currently being challenged by Samsung Electronics Co., Ltd. et al. While no claims have been canceled yet, the institution of trial means the PTAB found a "reasonable likelihood that the petitioner would prevail" on at least one challenged claim. This uncertainty can be leveraged by a defendant to negotiate.

Strategic summary

All claims of US10025731 remain untested by a Final Written Decision, but are currently under challenge in IPR2025-01431. No claims have been definitively canceled or sustained by the PTAB at this point.

The estoppel landscape will primarily impact the petitioner, Samsung Electronics Co., Ltd. et al. If any claims are ultimately found unpatentable, Samsung and its privies would be statutorily estopped from asserting in district court or the ITC any ground that was raised or reasonably could have been raised during the IPR (§ 315(e)(2)). For other potential defendants, all prior-art grounds remain theoretically available, though the arguments presented by Samsung in IPR2025-01431 may be highly persuasive or illustrative of the patent's weaknesses.

Regarding pattern signals, only one IPR proceeding (IPR2025-01431) is currently on file for this patent. The petitioner, Samsung Electronics Co., Ltd. et al., is a major operating company, suggesting a direct interest in challenging the patent rather than acting as a defensive aggregator. There is no information in the provided search results to indicate aggressive PTAB appeals by the patent owner or multiple IPRs from the same petitioner.

Recommended next steps

For IPR2025-01431, the status is "Trial Instituted," meaning the PTAB trial is ongoing. The Final Written Decision is typically due within one year from the institution date. While the precise institution date is not available in the provided information, given the "last modified" date of 2026-05-11, the Final Written Decision would likely be due around May 2027. A defendant facing assertion of this patent should monitor the progress of IPR2025-01431 closely. Upon the issuance of the institution decision, it would be crucial to review the PTAB's reasoning, the claims instituted for review, and the prior art grounds. This information, once public, will be critical for assessing the strength of the ongoing challenge and for informing any defensive strategy. The official PTAB documents for IPR2025-01431, including the institution decision, would be accessible through the USPTO PTAB E2E system.

Inventors

• Hyun Lee (Netlist Inc.)
• Jayesh R. Bhakta (Netlist Inc.)
• Jeffrey C. Solomon (Netlist Inc.)
• Mario Jesus Martinez (Netlist Inc.)
• Chi-She Chen (Netlist Inc.)

All inventors were presumably employed by Netlist Inc. at the time of filing, as Netlist Inc. is listed as the original assignee. No unusual patterns of inventors departing the original assignee within 12 months of filing are readily apparent from the patent record.

Original assignee

The original assignee on the issued patent US10025731 is Netlist Inc. Netlist Inc. designs and manufactures high-performance memory subsystems for servers and data centers. They ship products embodying the claims of their patents, including memory modules. Netlist Inc. is currently an operating company.

Assignment timeline

• 2015-11-20 (executed) / recorded 2015-11-20 — Reel 036814/0670
  • Conveyance: SECURITY AGREEMENT
  • Assignor: NETLIST, INC.
  • Assignee: SVIC NO. 28 NEW TECHNOLOGY BUSINESS INVESTMENT L.L.P.
  • Correspondent: DLA PIPER LLP (US), ATTN: INTELLECTUAL PROPERTY, P.O. BOX 2758, RESTON, VA 20195-2758. This correspondent recurs in this chain.
  • Context: Securitization where Netlist Inc. granted a security interest in the patent to SVIC No. 28 New Technology Business Investment L.L.P..
• 2023-11-20 (executed) / recorded 2023-11-20 — Reel 062635/0681
  • Conveyance: RELEASE OF SECURITY INTEREST
  • Assignor: SVIC NO. 28 NEW TECHNOLOGY BUSINESS INVESTMENT L.L.P.
  • Assignee: NETLIST, INC.
  • Correspondent: DLA PIPER LLP (US), ATTN: INTELLECTUAL PROPERTY, P.O. BOX 2758, RESTON, VA 20195-2758. This correspondent recurs in this chain.
  • Context: Release of the security interest, returning full beneficial ownership of the patent to Netlist Inc..

Timeline diagram

timeline
    title Ownership of US 10025731
    2008 : Priority date
    2015 : Application filed by Netlist
         : Security agreement to SVIC
    2018 : Patent granted
    2023 : Security interest released

NPE / troll-pattern signals

1. Shell-entity transfer — Not present. The transfers reflect a security agreement and its subsequent release involving the operating company Netlist Inc. and a financing entity, SVIC No. 28 New Technology Business Investment L.L.P..
2. Known asserter in the chain — Not present. SVIC NO. 28 NEW TECHNOLOGY BUSINESS INVESTMENT L.L.P. is not identified as a known patent assertion entity, and Netlist Inc. is an operating company.
3. Repeat correspondent across the chain — Present. DLA PIPER LLP (US) appears as the correspondent for both the 2015-11-20 security agreement (Reel 036814/0670) and the 2023-11-20 release of security interest (Reel 062635/0681).
4. Cascading transfers — Not present. The two recorded events are related to a single security interest transaction and its release over an eight-year period, not multiple consecutive transfers in a short timeframe.
5. Pre-litigation transfer — Not present. The most recent recorded transfer event (release of security interest) was on 2023-11-20 (Reel 062635/0681). Litigation cases involving this patent were filed in 2025, which is more than six months after the last transfer.
6. Bankruptcy fire-sale — Not present. Netlist Inc. remains an active operating company.
7. Privateering — Not present. There is no indication from the assignment records or publicly available information that Netlist Inc. transferred the patent for assertion by a third party on its behalf.
8. Defensive aggregator (anti-NPE) — Not present. The patent is currently owned by Netlist Inc., an operating company, and is not held by a known defensive aggregator.

Verdict

Operating-company assertion
The assignment records clearly indicate that the patent was subject to a security agreement and subsequently returned to Netlist Inc., an operating company. Netlist Inc. is actively involved in litigation concerning this patent, as shown by multiple pending cases filed in 2025. This pattern is consistent with an operating company asserting its intellectual property.

USPTO Assignment Center search for US10025731: https://assignmentcenter.uspto.gov/patent/[10025731](/patent/10025731)

The most relevant prior art for US patent 10025731, titled "Memory module and circuit providing load isolation and noise reduction," includes patents and patent applications that predate its earliest priority date of April 14, 2008. These references address various aspects of memory module design, buffering, power management, and signal integrity. The distinct features of US10025731, as described in Claim 1, revolve around a memory module that incorporates a circuit with first and second sets of bi-directional ports, a switching sub-circuit for selective coupling between these ports, and, crucially, a dedicated correction circuit within each of these ports configured to reduce noise in transmitted signals.

Below are selected prior art references from the "Patent citations" section of US10025731 on Google Patents, along with an assessment of their potential to anticipate Claim 1 under 35 U.S.C. § 102:

1. U.S. Patent No. 6,374,323 B1

• Full Citation: Pettey et al., U.S. Patent No. 6,374,323 B1, "Memory module."
• Publication/Filing Date: Filed May 22, 1998; Granted April 16, 2002.
• Brief Description: This patent describes a fundamental memory module comprising a printed circuit board, a connector, and a plurality of memory integrated circuit devices. It details the physical arrangement and interconnection of these components, focusing on the electrical pathways for data and control signals.
• Potential Anticipation of Claim(s) under 35 U.S.C. § 102: While US6374323B1 establishes the basic structure of a memory module, including a PCB, connector, and memory devices, it does not disclose the active "circuit" elements central to US10025731's Claim 1. Specifically, it lacks a switching sub-circuit for selective port coupling and, more importantly, individual noise correction circuits within each port. Therefore, it does not anticipate the key functional aspects of Claim 1 related to load isolation and active noise reduction.

2. U.S. Patent No. 6,857,038 B1

• Full Citation: Johnson et al., U.S. Patent No. 6,857,038 B1, "Modular buffer for memory modules with improved buffering."
• Publication/Filing Date: Filed September 27, 2001; Granted February 15, 2005.
• Brief Description: This patent introduces a modular buffer designed to be integrated with memory modules. The buffer includes host data pins for connection to a memory controller and memory data pins for connection to memory devices. Its primary purpose is to reduce electrical loading on the memory bus and enhance overall signal integrity through buffering.
• Potential Anticipation of Claim(s) under 35 U.S.C. § 102: This patent is more relevant as it discusses a "modular buffer" acting as a "circuit" with input/output pins (analogous to first and second sets of ports) and aims to improve signal integrity and reduce loading. While the concept of buffering inherently helps with signal quality, US6857038B1 does not explicitly teach a "switching sub-circuit configured to selectively operatively couple one or more ports" or a "correction circuit configured to reduce noise" specifically within each port of the sets of ports, as required by Claim 1 of US10025731. The buffering described is a general improvement rather than specific per-port noise correction.

3. U.S. Patent No. 7,188,198 B2

• Full Citation: Kirkwood et al., U.S. Patent No. 7,188,198 B2, "Fully buffered DIMM with improved read data path."
• Publication/Filing Date: Filed August 31, 2004; Granted March 6, 2007.
• Brief Description: This patent describes a Fully Buffered Dual In-line Memory Module (FBDIMM) architecture, which utilizes an Advanced Memory Buffer (AMB) to handle all signal traffic (data, address, command) between a memory controller and DRAM devices. The AMB re-drives signals to mitigate signal degradation and reduce electrical load.
• Potential Anticipation of Claim(s) under 35 U.S.C. § 102: US7188198B2 details an AMB that functions as a "circuit" with ports, effectively re-driving signals to improve signal integrity, which is a form of noise reduction. However, Claim 1 of US10025731 specifically calls for a "switching sub-circuit configured to selectively operatively couple" and distinct "correction circuits" embedded within each individual port for noise reduction. While an FBDIMM's AMB provides significant signal conditioning, the patent does not clearly articulate the granular, per-port noise correction elements or the explicit selective coupling mechanism described in US10025731's Claim 1.

4. U.S. Patent No. 7,281,084 B2

• Full Citation: Bhakta et al., U.S. Patent No. 7,281,084 B2, "Memory controller with memory power management."
• Publication/Filing Date: Filed September 24, 2004; Granted October 9, 2007.
• Brief Description: This patent discloses a memory controller that implements power management techniques for memory devices. It focuses on dynamically controlling power to individual memory ranks or devices, allowing inactive components to be logically isolated and thereby reducing overall power consumption.
• Potential Anticipation of Claim(s) under 35 U.S.C. § 102: This reference is highly relevant to the "load isolation" and "power dissipation" benefits mentioned in US10025731. The dynamic control of power states to effectively isolate inactive memory components aligns with the function of a "switching sub-circuit configured to selectively operatively couple" ports to achieve logical isolation and power reduction. However, US7281084B2 primarily addresses power management and does not explicitly teach or suggest the integration of "correction circuits configured to reduce noise" within each port of the communication pathways, which is a key distinguishing feature of Claim 1 of US10025731.

5. U.S. Patent Application Publication No. 2007/0055836 A1

• Full Citation: Pettey et al., U.S. Patent Application Publication No. 2007/0055836 A1, "Memory module having improved signal integrity."
• Publication/Filing Date: Filed September 1, 2006; Published March 8, 2007.
• Brief Description: This application describes a memory module that includes a buffer device designed to enhance signal integrity. The buffer re-drives signals and may incorporate elements for impedance matching or other signal conditioning techniques to counteract signal degradation over transmission lines.
• Potential Anticipation of Claim(s) under 35 U.S.C. § 102: This patent application is among the most relevant due to its explicit focus on "improved signal integrity" on a memory module using a "buffer device." This buffer device functions as a "circuit" with associated I/O (ports). The re-driving and signal conditioning mentioned are direct methods of "reducing noise." If the buffer device's architecture implicitly or explicitly includes noise reduction elements integrated with its I/O ports that function as "correction circuits," it could anticipate the signal integrity aspect of Claim 1. However, the extent of anticipation hinges on whether the application details the "correction circuit" within each port and also a "switching sub-circuit configured to selectively operatively couple" the ports as described in Claim 1 of US10025731. While very close in scope regarding signal integrity, the precise combination and granularity of the elements in Claim 1 of US10025731 may still offer patentable distinction.

Under 35 U.S.C. § 103, an invention is considered obvious if the differences between the claimed invention and the prior art are such that the subject matter as a whole would have been obvious at the time the invention was made to a person having ordinary skill in the art (PHOSITA). The analysis requires identifying prior art, identifying the differences between the prior art and the claimed invention, and determining if there was a motivation for a PHOSITA to combine or modify the prior art to arrive at the claimed invention with a reasonable expectation of success.

US patent 10025731 describes a memory module that includes a printed circuit board with at least one connector, a plurality of memory devices, and a circuit. The circuit comprises a first set of bi-directional ports coupled to the memory devices, a second set of bi-directional ports coupled to the connector, a switching sub-circuit configured to selectively couple ports between the two sets, and a correction circuit associated with each port. The correction circuit is designed to reduce noise in signals transmitted between the ports. The correction circuit can include a coarse correction element (e.g., programmable impedance matching circuit), a fine correction element (e.g., a self-adjusting damper circuit), a filter element, and a repeater/amplifier element.

Prior Art as Described in US10025731

The patent itself describes the "Description of the Related Art" as follows, effectively outlining the conceptual prior art that existed at the time of the invention (priority date April 14, 2008):

1. System 10 (FIG. 1): This system incorporates a multiplexer-demultiplexer 12 to isolate unused subsystems 16, 18, thereby reducing the load on drivers. [cite: The present application relates generally to the field of electrical signal integrity and more specifically to circuits for improving electrical signal integrity. Description of the Related Art. Traditional systems sometimes incorporate multiplexers and/or demultiplexers to help quiet inactive signal paths, minimizing the overall dynamic power dissipation, and isolating unused subsystems. FIG. 1 schematically illustrates an example of such a system 10 which incorporates a multiplexer- demultiplexer 12 to isolate unused subsystems of a plurality of subsystems 16 , 18.] However, this arrangement can introduce "transmission line discontinuity regions," leading to signal reflections, distortions, and degraded system performance. [cite: the multiplexer and/or demultiplexer 12 can present transmission line discontinuity regions in electronic systems (e.g., in electronic systems with signal paths with electrical lengths longer than 1 ⁇ 4 of the wavelength of the operational frequency or the signal transition rate). In such systems, signal reflections may occur, changing wave characteristics and degrading system performance.]
2. System 20 (FIG. 2): This system uses device select signals 22, 24 (e.g., chip select signals) to logically isolate unused memory devices by not activating their address, control, and/or device select signals. [cite: In memory applications, some systems control “chip select” or device select signals, along with the memory address and control signals, based on the device select signals, in order to disable memory devices when they are not being accessed. FIG. 2 schematically illustrates an example of such a system 20 which isolates unused subsystems of a plurality of subsystems 16 , 18 using device select signals 22 , 24 (e.g., chip select signals).] The drawbacks of this approach include introducing timing delays on signal paths and failing to address power dissipation issues adequately. [cite: Generating controllable address and device select signals can introduce timing delays on the device select, address, and control paths. In addition, this arrangement does not address the power dissipation and may degrade performance degradation by, for example, requiring that secondary control signals be generated for the memory devices.]

These descriptions serve as the foundational "prior art" from which the claimed invention seeks to differentiate itself, highlighting the problems that a PHOSITA would be motivated to solve.

Motivation for a Person Having Ordinary Skill in the Art (PHOSITA)

A PHOSITA in the field of memory system design, observing the limitations of the conventional approaches (System 10 and System 20) as described in the patent, would be motivated to develop a memory module that simultaneously achieves effective load isolation, reduces power consumption, and significantly improves signal integrity. The patent explicitly articulates these motivations:

• Higher speed processors and memory densities lead to increased power dissipation and memory access time, impairing system performance. [cite: However, higher speed processors and higher memory densities translate to higher power dissipation and increased memory access time, impairing the performance of the system.]
• Impedance mismatches further degrade performance and power efficiency. [cite: Additionally, impedance mismatches between the system board, the memory boards, and the memory devices may also substantially degrade the performance and power efficiency of traditional memory systems.]
• Multiplexers, while providing isolation, introduce signal integrity issues due to transmission line discontinuities and reflections. [cite: In such systems, signal reflections may occur, changing wave characteristics and degrading system performance.]
• Device select signals cause timing delays and do not fully address power dissipation. [cite: Generating controllable address and device select signals can introduce timing delays on the device select, address, and control paths.]

The overarching motivation would be to overcome these well-recognized challenges in high-performance memory systems, seeking a solution that maintains or improves system speed and capacity without compromising signal integrity or excessively increasing power consumption.

Obvious Combinations of Prior Art

A PHOSITA, aiming to solve the identified problems, would have found it obvious to combine elements and principles from the described prior art and general engineering knowledge to arrive at the claimed invention.

1. Combining Load Isolation with Signal Integrity Improvement:

   • Switching Sub-Circuit (Load Isolation): The concept of isolating inactive memory subsystems to reduce load and power consumption was known, as evidenced by System 10 (multiplexer-demultiplexer) and System 20 (device select signals). A PHOSITA would be motivated to employ a switching mechanism (which the patent describes as a "switching sub-circuit 140" that can function as a "bidirectional multiplexer-demultiplexer" or a "router" [cite: The switching sub-circuit 140 comprises or is characterized as a bidirectional multiplexer-demultiplexer in certain embodiments. In other embodiments, the switching sub-circuit 140 comprises or is characterized as a router.]) to selectively couple active memory devices/ranks while isolating inactive ones. This directly addresses the goal of reducing dynamic power consumption by providing a known static value to un-driven ports. [cite: the switching sub-circuit 140 isolates and provides a known static value to all un-driven ports, thereby reducing any dynamic power consumption associated with floating or toggling electrical nodes.]
   • Correction Circuit (Noise Reduction): Recognizing that the very act of switching (as in System 10) or driving signals across longer or more complex paths can introduce signal integrity issues, a PHOSITA would be motivated to integrate signal conditioning elements into the signal paths.

2. Specific Elements of the Correction Circuit:

   • Coarse Correction Element (Programmable Impedance Matching): Impedance mismatches are a fundamental cause of signal reflections in high-speed transmission lines, as acknowledged by the patent. [cite: Additionally, impedance mismatches between the system board, the memory boards, and the memory devices may also substantially degrade the performance and power efficiency of traditional memory systems.] The use of impedance matching circuits to mitigate reflections is a well-established engineering practice. A PHOSITA would foresee the benefit of a "programmable impedance matching circuit" [cite: the at least one coarse correction element 152 comprises at least one programmable impedance matching circuit in certain embodiments.] (e.g., using programmable resistors [cite: the programmable impedance matching circuit 160 may comprises at least one programmable resistor 162.]) to dynamically adjust to varying load conditions or transmission line characteristics, especially after a switching element, to reduce noise. This would be a conventional response to a known problem.
   • Filter Element: Filters are standard components in electrical engineering used to remove unwanted frequency components or noise from signals. The patent mentions that the "filter element 156 may reduce noise from the one or more signals where the noise includes a predetermined range of frequencies" [cite: The filter element 156 may reduce noise from the one or more signals where the noise includes a predetermined range of frequencies.]. Common types like band-pass, low-pass, or high-pass filters [cite: In other embodiments, the filter element 156 comprises at least one other type of a filter such as a notch filter, a low-pass filter, or a high-pass filter.] would be obvious choices for a PHOSITA to address noise, including cross-coupling. [cite: the filter elements 156 reduce or filter out cross-coupling between signals, for example.]
   • Repeater/Amplifier Element: High-speed signals degrade over transmission lines due to attenuation and dispersion. Repeaters and amplifiers are routinely used to restore signal strength, reshape waveforms, and improve slew rates, thereby enhancing signal quality. The patent notes that the "repeater/amplifier element 158 reshapes the signal, which may be deteriorated due to transmission over lossy transmission lines having discontinuity regions" [cite: the repeater/amplifier element 158 reshapes the signal, which may be deteriorated due to transmission over lossy transmission lines having discontinuity regions.]. Their inclusion to "improve the signal quality of the one or more signals" [cite: the correction circuit 150 further comprises at least one repeater/amplifier element 158 , which improves the signal quality of the one or more signals.] would be a conventional engineering solution.
   • Fine Correction Element (Self-Adjusting Damper): While the patent refers to specific provisional applications for its "self-adjusting damper circuit 170" [cite: Examples of self-adjusting damper circuits 170 in accordance with certain embodiments described herein are described in U.S. Provisional Application No. 61/044,825, filed Apr. 14, 2008, and copending U.S. application Ser. No. 12/422,912, filed by the assignee of the present application on Apr. 13, 2009.], the general concept of dampening signal reflections and oscillations to smooth signals is a known technique in signal integrity. If these provisional applications were not enabling or if other dampening circuits were publicly known before the priority date and applicable in this context, then the inclusion of a damper circuit to "further reduces signal reflections due to impedance mismatches and/or reduces other noise" [cite: the at least one fine correction element 154 of the correction circuit 150 further reduces signal reflections due to impedance mismatches and/or reduces other noise.] would be an obvious design choice for a PHOSITA seeking to refine signal quality after coarse impedance matching.

The combination of a switching sub-circuit for selective load isolation (addressing the problems of System 10 and System 20) with a comprehensive correction circuit employing established signal integrity techniques (impedance matching, filtering, amplification, and dampening) to counteract the inherent signal degradation in high-speed memory systems, would represent a logical and foreseeable advancement to a PHOSITA at the time of invention. The patent explicitly states the problems and proposes solutions that are generally known remedies for those specific problems, thereby establishing a strong motivation for combination.