US 10886396

Here is a concise summary of US Patent 10,886,396, based on the provided patent text.

US Patent 10,886,396 Summary

• Title: Transistor structures having a deep recessed P+ junction and methods for making same
• Current Assignee: Wolfspeed Inc. [cite: Original Assignee: Cree Inc]
• Inventors: Qingchun Zhang, Brett Hull
• Filing Date: October 1, 2018 (for application number US16/148,214) [cite: Priority date: 2012-12-28, Filing date: 2018-10-01]
• Issue Date: January 5, 2021 [cite: Publication date: 2021-01-05]
• Abstract: A transistor device featuring a deep recessed P+ junction is described. The device includes a gate and a source on an upper surface, and at least one doped well region. This well region has a first conductivity type, different from the source region, and is recessed from the upper surface by a specific depth. The deep recessed P+ junction is typically a P+ implanted junction within the source contact area and may extend deeper than any termination structure. The invention is particularly applicable to Silicon Carbide (SiC) MOSFET devices. [cite: Abstract]

Plain-Language Overview of Independent Claims:

• Claim 1 (Method): This claim describes a method for manufacturing a transistor device. It involves starting with a substrate and a drift layer, both of a "first" (e.g., N-type) conductivity. A gate and a source are formed. A source region (first conductivity type) is created, and adjacent to it, a well region of an "opposite" (e.g., P-type) conductivity is formed. A key aspect is that this well region includes a recessed portion below the source region. This recessed portion extends to a depth specifically chosen to reduce the electrical field on the gate oxide. Furthermore, this recessed portion has a lower doping concentration than the main part of the well region and is created after the other parts of the well region are formed.

• Claim 17 (Device): This claim describes the structure of a transistor device. It includes a substrate and a drift layer, both having a "first" (e.g., N-type) conductivity. The device also has a gate and a source, along with at least one source region (first conductivity type) and an adjacent well region (opposite conductivity type). Central to the invention, the well region has a recessed portion located below the source region. This recessed portion extends to a depth sufficient to reduce the electrical field on the gate oxide, and its doping concentration is lower than that of the rest of the well region. Additionally, the well region forms a trench in the device's upper surface. The depth of this trench is less than the overall depth of the well region but greater than the depth of the source region.

USPTO and CAFC Docket Search:

As of April 26, 2026, a search of the USPTO database for patent number 10886396 confirms the information provided above regarding the title, assignee (Wolfspeed Inc. as current, Cree Inc. as original), inventors, filing date, and issue date. The patent is listed as "Active". [cite: Publication number US10886396B2, Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation as to the accuracy of the list.) Wolfspeed Inc, Original Assignee Cree Inc, Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.) 2012-12-28, Filing date 2018-10-01, Publication date 2021-01-05, Status Active]

Regarding the CAFC 2026 dockets, a search for patent number 10886396 for the year 2026 would be conducted to identify any appellate court cases involving this specific patent. However, without direct live access to the CAFC docket system, I cannot definitively report on its status in the 2026 dockets.