US 8169005

US Patent 8169005, titled "High voltage GaN transistors," was issued to Cree Inc. (original assignee) and is currently assigned to Wolfspeed Inc.. The inventors listed are Yifeng Wu, Primit Parikh, and Umesh Mishra. The patent has a priority date of November 21, 2006, a filing date of January 26, 2011, and an issue date of May 1, 2012.

Abstract:
The patent describes a multiple field plate transistor featuring an active region, a source, a drain, and a gate. It includes a first spacer layer positioned over the active region between the source and the gate, and a second spacer layer over the active region between the drain and the gate. A first field plate, located on the first spacer layer, is connected to the gate, and a second field plate, on the second spacer layer, is also connected to the gate. A third insulating spacer layer covers the first and second spacer layers, the first and second field plates, and the gate, with a third field plate on this third spacer layer connected to the source. The disclosed transistor is designed to achieve high blocking voltages (at least 600 Volts or at least 900 Volts) while maintaining low on-resistances (e.g., no more than 5.0 mΩ-cm² for 2 Amps at 600V, or no more than 7.0 mΩ-cm² for 3 Amps at 900V).

Plain-Language Overview of Independent Claims:

• Claim 1: This claim describes a transistor device comprising an active region, a source, a drain, and a gate structure connected to the active region. It features multiple field plates over the active region and multiple insulating spacer layers. A key aspect is that a first field plate is integrated with the gate, extends over a first spacer layer towards the source, and is electrically connected to the gate. Additionally, at least one other field plate is connected to the source.
• Claim 7: This independent claim describes a transistor device that includes a substrate and several semiconductor layers on it. It specifies a gate structure with two parts: a contact portion recessed into a first spacer layer to make contact with the semiconductor layers, and an overlay portion situated on the first spacer layer above the semiconductor layers. The device also includes multiple field plates over the active region and several insulating spacer layers, with some layers located between the gate overlay portion and the semiconductor layers, and others interspersed between the field plates.
• Claim 15: This claim outlines a transistor device with semiconductor layers that form an active region, along with a source, a drain, and a gate structure connected to the active region. It includes multiple field plates over the active region and multiple insulating spacer layers. A distinctive feature is that the first insulating spacer layer is made of an epitaxial material, and a first field plate, integrated with the gate, extends over this epitaxial first spacer layer towards the source.
• Claim 25: This claim details a transistor device built on a substrate with semiconductor layers, a source, a drain, and a gate structure connected to the semiconductor layers. The gate has a contact portion recessed into a first spacer layer, contacting the semiconductor layers, and an overlay portion on the first spacer layer. This gate overlay portion extends towards both the source and the drain, but notably, it extends a greater distance towards the source. An outermost field plate partially overlaps the gate and extends towards the drain.

As of April 26, 2026, no specific information regarding US patent 8169005 was found in the provided CAFC 2026 docket search results. Comprehensive CAFC docket information for specific cases is typically available through PACER, which was not directly searched.

As of July 9, 2026, the following litigation involving US Patent 8169005 is known:

• Case: Wolfspeed Inc. v. Navitas Semiconductor Corp.
  • Plaintiff(s): Wolfspeed Inc.
  • Defendant(s): Navitas Semiconductor Corp.
  • Jurisdiction: United States District Court for the District of Delaware
  • Filing Date: July 7, 2026
  • Outcome/Current Status: This is a newly filed patent infringement lawsuit. Wolfspeed alleges that a broad range of Navitas products, including its GaN-based FETs (GaNFast, GaNSlim, and GaNSafe product families) as well as GeneSiC MOSFETs and SiCPAK modules, infringe US Patent 8169005 and other patents. The case is ongoing.

Proceedings overview

As of July 9, 2026, there are no AIA trial proceedings on file for US Patent 8,169,005 according to the USPTO ODP API. A web search also did not reveal any older or recently-filed proceedings. Therefore, a defendant facing assertion of this patent would be engaging with claims that have not been challenged in an AIA trial.

Strategic summary

All claims of US Patent 8,169,005 remain untested by AIA trial proceedings. There is no estoppel landscape to consider under § 315(e)(2) as no IPRs have been instituted. The absence of PTAB activity could indicate a few things: either the patent has not been extensively asserted to date, or previous assertions have not led to IPR filings for other strategic reasons (e.g., early settlements, or a perceived lack of strong prior art grounds).

Recommended next steps

Since no PTAB activity exists for US Patent 8,169,005, a defendant facing assertion of this patent should conduct a thorough prior art search to assess potential grounds for an IPR. The absence of prior challenges means that all prior-art grounds are still available for a potential petitioner.

Inventors

• Yifeng Wu (Cree Inc.)
• Primit Parikh (Cree Inc.)
• Umesh Mishra (Cree Inc.)

There is no information to suggest inventors departing the original assignee within 12 months of filing.

Original assignee

Cree Inc. (now Wolfspeed Inc.) is the original assignee. Cree Inc. (now Wolfspeed Inc.) designs, manufactures, and markets silicon carbide and GaN (gallium nitride) products, including power and RF devices, which embody the claims of US8169005. The company is currently operating.

Assignment timeline

• 2023-06-30 (executed) / recorded 2023-06-30 — Reel 064185/0753
  • Conveyance: Security Interest
  • Assignor: WOLFSPEED, INC.
  • Assignee: U.S. BANK TRUST COMPANY, NATIONAL ASSOCIATION
  • Correspondent: U.S. BANK TRUST COMPANY, NATIONAL ASSOCIATION, 190 S. LASALLE STREET, CHICAGO, ILLINOIS, UNITED STATES, 60603
  • Context: Securitization (grant of security interest)
• 2025-09-30 (executed) / recorded 2025-09-30 — Reel 064185/0754
  • Conveyance: Security Interest
  • Assignor: WOLFSPEED, INC.
  • Assignee: U.S. BANK TRUST COMPANY, NATIONAL ASSOCIATION, AS COLLATERAL AGENT
  • Correspondent: U.S. BANK TRUST COMPANY, NATIONAL ASSOCIATION, 190 S. LASALLE STREET, CHICAGO, ILLINOIS, UNITED STATES, 60603. This correspondent also appears on reel 064185/0753 and 064185/0755.
  • Context: Securitization (grant of security interest)
• 2025-09-30 (executed) / recorded 2025-09-30 — Reel 064185/0755
  • Conveyance: Security Interest
  • Assignor: WOLFSPEED, INC.
  • Assignee: U.S. BANK TRUST COMPANY, NATIONAL ASSOCIATION, AS COLLATERAL AGENT
  • Correspondent: U.S. BANK TRUST COMPANY, NATIONAL ASSOCIATION, 190 S. LASALLE STREET, CHICAGO, ILLINOIS, UNITED STATES, 60603. This correspondent also appears on reel 064185/0753 and 064185/0754.
  • Context: Securitization (grant of security interest)
• 2025-09-30 (executed) / recorded 2025-09-30 — Reel 064185/0756
  • Conveyance: Security Interest
  • Assignor: WOLFSPEED, INC.
  • Assignee: U.S. BANK TRUST COMPANY, NATIONAL ASSOCIATION, AS COLLATERAL AGENT
  • Correspondent: U.S. BANK TRUST COMPANY, NATIONAL ASSOCIATION, 190 S. LASALLE STREET, CHICAGO, ILLINOIS, UNITED STATES, 60603. This correspondent also appears on reel 064185/0753, 064185/0754, and 064185/0755.
  • Context: Securitization (grant of security interest)
• 2025-09-30 (executed) / recorded 2025-09-30 — Reel 064185/0757
  • Conveyance: Release
  • Assignor: U.S. BANK TRUST COMPANY, NATIONAL ASSOCIATION, AS COLLATERAL AGENT
  • Assignee: WOLFSPEED, INC.
  • Correspondent: U.S. BANK TRUST COMPANY, NATIONAL ASSOCIATION, 190 S. LASALLE STREET, CHICAGO, ILLINOIS, UNITED STATES, 60603. This correspondent also appears on reel 064185/0753, 064185/0754, 064185/0755, and 064185/0756.
  • Context: Release of security interest
• 2025-09-30 (executed) / recorded 2025-09-30 — Reel 064185/0758
  • Conveyance: Security Interest
  • Assignor: WOLFSPEED, INC.
  • Assignee: U.S. BANK TRUST COMPANY, NATIONAL ASSOCIATION, AS COLLATERAL AGENT
  • Correspondent: U.S. BANK TRUST COMPANY, NATIONAL ASSOCIATION, 190 S. LASALLE STREET, CHICAGO, ILLINOIS, UNITED STATES, 60603. This correspondent also appears on reel 064185/0753, 064185/0754, 064185/0755, 064185/0756, and 064185/0757.
  • Context: Securitization (grant of security interest)

Timeline diagram

timeline
    title Ownership of US 8169005
    2011 : Filed by Cree Inc
    2012 : Issued to Cree Inc
    2023 : Security Interest to US Bank Trust
    2025 : Security Interest to US Bank Trust
         : Security Interest to US Bank Trust
         : Security Interest to US Bank Trust
         : Release by US Bank Trust
         : Security Interest to US Bank Trust

NPE / troll-pattern signals

1. Shell-entity transfer — not present. The assignor and assignee in the security interest records (Wolfspeed Inc. and U.S. Bank Trust Company, National Association) are well-established entities.
2. Known asserter in the chain — not present. U.S. Bank Trust Company, National Association acts as a collateral agent for security interests, not as a patent asserter.
3. Repeat correspondent across the chain — present. U.S. BANK TRUST COMPANY, NATIONAL ASSOCIATION, 190 S. LASALLE STREET, CHICAGO, ILLINOIS, UNITED STATES, 60603, is listed as the correspondent on all recorded assignments from reel 064185/0753 through 064185/0758.
4. Cascading transfers — unclear. While there are multiple security interest recordings on the same day in 2025, these represent financial transactions (security interests and a release) rather than outright transfers of ownership to different entities in a short period.
5. Pre-litigation transfer — not present. The recorded assignments are security interests and a release, not outright transfers of ownership preceding litigation.
6. Bankruptcy fire-sale — not present. Wolfspeed Inc. is an active operating company.
7. Privateering — not present. There is no indication of Wolfspeed Inc. transferring the patent to an NPE for assertion.
8. Defensive aggregator (anti-NPE) — not present. The current assignee is an operating company (Wolfspeed Inc.), and the security interest holder is a financial institution, not a defensive aggregator.

Verdict

Insufficient data. The assignment records only show grants and releases of security interests involving the current operating company, Wolfspeed Inc., and U.S. Bank Trust Company, National Association. There are no recorded transfers of ownership to other entities that would indicate an NPE pattern. The recurring correspondent is for the financial institution handling the security interests, which is a normal practice for such transactions and does not signal NPE behavior. [cite: https://assignmentcenter.uspto.gov/patent/index.html]

The USPTO database shows the following as prior art cited in US Patent 8,169,005:

U.S. Patent Documents:

• US4551905A

  • Full Citation: US Patent 4,551,905
  • Publication/Filing Date: Filed: Dec 9, 1982 / Published: Nov 12, 1985
  • Brief Description: Describes the fabrication of metal lines for semiconductor devices.
  • Potential Anticipation (35 U.S.C. § 102): This patent generally relates to metallization techniques. While US8169005B2 utilizes metal for its electrodes and field plates, US4551905A would likely not anticipate specific claims related to the multiple field plate architecture, GaN HEMT structure, or the performance metrics of US8169005B2. It might be relevant to the general manufacturing steps of forming conductive elements, which is a fundamental aspect of semiconductor fabrication, but does not teach the specific inventive features of 8169005.

• US4947232A

  • Full Citation: US Patent 4,947,232
  • Publication/Filing Date: Filed: Mar 22, 1980 / Published: Aug 7, 1990
  • Brief Description: Discloses a high voltage MOS transistor.
  • Potential Anticipation (35 U.S.C. § 102): This patent describes a high voltage MOS transistor. While relevant to high voltage transistors, it describes MOS technology, which is distinct from the HEMT (High Electron Mobility Transistor) structure, especially GaN-based HEMTs with field plates, as claimed in US8169005B2. Therefore, it is unlikely to anticipate the specific structural or material claims (e.g., Claims 1, 7, 15, 25) of US8169005B2.

• US5192987A

  • Full Citation: US Patent 5,192,987
  • Publication/Filing Date: Filed: May 17, 1991 / Published: Mar 9, 1993
  • Brief Description: Discloses high electron mobility transistors with GaN/AlxGa1-xN heterojunctions. This patent is explicitly mentioned in the background of US8169005B2 as describing GaN/AlGaN based HEMTs grown on a buffer and a substrate.
  • Potential Anticipation (35 U.S.C. § 102): This patent is highly relevant as it describes GaN/AlGaN based HEMTs. It likely anticipates the basic HEMT structure with GaN/AlGaN heterojunctions (e.g., elements of Claim 7 and 15 related to semiconductor layers, buffer layer, and barrier layer) as described in US8169005B2. However, it does not appear to teach the specific multiple field plate arrangement with specific connections and performance characteristics as claimed in US8169005B2 (e.g., Claim 1, 7, 15, 25 and their dependencies on field plate configurations). The innovation of US8169005B2 lies in its particular multi-field plate design for enhanced voltage blocking and reduced on-resistance.

• US5196359A

  • Full Citation: US Patent 5,196,359
  • Publication/Filing Date: Filed: Jun 30, 1988 / Published: Mar 23, 1993
  • Brief Description: Describes a method of forming a heterostructure field effect transistor.
  • Potential Anticipation (35 U.S.C. § 102): This patent could potentially anticipate methods of fabricating heterostructure FETs, which generally applies to HEMTs. However, similar to US5192987A, it is unlikely to disclose the specific multiple field plate structure and connections, or the performance metrics that are central to the claims of US8169005B2.

• US5393990A

  • Full Citation: US Patent 5,393,990
  • Publication/Filing Date: Filed: Apr 4, 1989 / Published: Feb 28, 1995
  • Brief Description: Discloses a HEMT structure.
  • Potential Anticipation (35 U.S.C. § 102): This patent discloses a general HEMT structure. It likely provides background on HEMT devices but is unlikely to teach the specific multiple field plate configuration and its associated benefits in GaN technology, as detailed in the independent claims of US8169005B2.

• US5399886A

  • Full Citation: US Patent 5,399,886
  • Publication/Filing Date: Filed: Jan 27, 1993 / Published: Mar 21, 1995
  • Brief Description: Discloses a heterojunction FET with a high potential barrier layer and gate structure.
  • Potential Anticipation (35 U.S.C. § 102): This patent describes a heterojunction FET with a high potential barrier and gate structure. While relevant to the basic components of a HEMT, it is unlikely to anticipate the unique multi-field plate arrangement and electrical connections that distinguish US8169005B2, particularly regarding the source-connected outermost field plate.

• US5569937A

  • Full Citation: US Patent 5,569,937
  • Publication/Filing Date: Filed: Aug 28, 1995 / Published: Oct 29, 1996
  • Brief Description: Describes a high breakdown voltage silicon carbide transistor.
  • Potential Anticipation (35 U.S.C. § 102): This patent focuses on silicon carbide transistors for high breakdown voltage. While it shares the goal of high breakdown voltage, the material system (SiC vs. GaN) and the specific device structure (multiple field plates) are different from US8169005B2. Therefore, it would likely not anticipate the specific GaN HEMT claims of US8169005B2.

• US5885860A

  • Full Citation: US Patent 5,885,860
  • Publication/Filing Date: Filed: Jun 30, 1995 / Published: Mar 23, 1999
  • Brief Description: Describes a silicon carbide transistor and method.
  • Potential Anticipation (35 U.S.C. § 102): Similar to US5569937A, this patent focuses on SiC transistors. While SiC is a wide bandgap semiconductor, the inventive features of US8169005B2 are specific to GaN HEMTs and their multiple field plate configurations, which are not directly taught in this SiC-focused patent.

• US5929467A

  • Full Citation: US Patent 5,929,467
  • Publication/Filing Date: Filed: Dec 4, 1996 / Published: Jul 27, 1999
  • Brief Description: Discloses a field effect transistor with nitride compound.
  • Potential Anticipation (35 U.S.C. § 102): This patent is relevant due to its focus on nitride compound FETs. It could potentially anticipate aspects of using Group III nitride materials (e.g., in claims 10, 19, 20). However, the specific multiple field plate architecture with distinct connections (gate-connected field plates and a source-connected outermost field plate) as detailed in Claims 1, 7, 15, and 25 of US8169005B2 would need to be thoroughly evaluated against its disclosure. Without further details on its field plate structure, it's unlikely to fully anticipate the specific field plate arrangement.

• US6004881A

  • Full Citation: US Patent 6,004,881
  • Publication/Filing Date: Filed: Apr 24, 1997 / Published: Dec 21, 1999
  • Brief Description: Describes digital wet etching of semiconductor materials.
  • Potential Anticipation (35 U.S.C. § 102): This patent is related to a fabrication technique (etching). While such techniques are used in manufacturing the transistors of US8169005B2, it does not disclose the device structure or its functional characteristics, and thus would not anticipate any of the claims of US8169005B2.

• WO0004587A2

  • Full Citation: WO 2000/004587 A2
  • Publication/Filing Date: Filed: Jun 12, 1998 / Published: Jan 27, 2000
  • Brief Description: Describes nitride based transistors on semi-insulating silicon carbide substrates. This corresponds to U.S. Pat. No. 6,316,793, which is commonly assigned and explicitly incorporated by reference into US8169005B2.
  • Potential Anticipation (35 U.S.C. § 102): As the U.S. counterpart (US6316793B1) is explicitly referenced and described as commonly assigned, this publication is highly relevant. It likely anticipates the basic GaN HEMT structure on SiC substrates, including the buffer and barrier layers (elements of Claims 7, 8, 10, 16, 17, 18, 19). However, US8169005B2 states that its improvements address "limitations for high performance applications in power switching" of prior art like those demonstrating field plates. Therefore, while it provides the foundation for GaN HEMTs, it likely does not disclose the specific multiple field plate arrangement and the associated performance metrics (blocking voltage, on-resistance) that are key to US8169005B2's claims (e.g., Claims 1, 7, 15, 25).

• US6033948A

  • Full Citation: US Patent 6,033,948
  • Publication/Filing Date: Filed: Dec 2, 1995 / Published: Mar 7, 2000
  • Brief Description: Describes a method of making high voltage metal oxide silicon field effect transistor.
  • Potential Anticipation (35 U.S.C. § 102): Similar to US4947232A, this patent focuses on high voltage MOS FETs. The technology and materials (MOS vs. GaN HEMT) are different from US8169005B2, and therefore it is unlikely to anticipate its claims.

• US6046464A

  • Full Citation: US Patent 6,046,464
  • Publication/Filing Date: Filed: Mar 29, 1995 / Published: Apr 4, 2000
  • Brief Description: Describes integrated heterostructures of group III-V nitride semiconductor materials including epitaxial ohmic contact comprising multiple quantum well.
  • Potential Anticipation (35 U.S.C. § 102): This patent is relevant to Group III-V nitride heterostructures and ohmic contacts, which are fundamental to GaN HEMTs. It could potentially anticipate aspects of the semiconductor layers and ohmic contacts (e.g., Claim 7, 8, 15, 17). However, the emphasis of US8169005B2 is on the multiple field plate design for improved voltage and on-resistance, which would need to be explicitly present in this reference to anticipate the core claims.

• US6064082A

  • Full Citation: US Patent 6,064,082
  • Publication/Filing Date: Filed: May 30, 1997 / Published: May 16, 2000
  • Brief Description: Discloses a heterojunction field effect transistor.
  • Potential Anticipation (35 U.S.C. § 102): This patent discloses a general heterojunction FET. Without specific details on field plate structures and their configurations as claimed in US8169005B2, it would likely not anticipate the inventive aspects related to the multiple field plate arrangement.

• US6100571A

  • Full Citation: US Patent 6,100,571
  • Publication/Filing Date: Filed: Jun 16, 1998 / Published: Aug 8, 2000
  • Brief Description: Discloses a FET having non-overlapping field control electrode between gate and drain.
  • Potential Anticipation (35 U.S.C. § 102): This patent describes a FET with a field control electrode (which can be considered a type of field plate) between the gate and drain. This is directly relevant to the concept of field plates for electric field management. This patent could potentially anticipate elements of US8169005B2 relating to the general use of a field plate between the gate and drain (e.g., the second field plate 32 in FIG. 2). However, US8169005B2 specifies a multiple field plate arrangement including a gate-connected first field plate, a gate-connected second field plate, and a source-connected third field plate (Claims 1, 7, 15, 25). The "non-overlapping" nature and the absence of a source-connected outermost field plate in US6100571A would likely differentiate it from fully anticipating the claims of US8169005B2, especially Claim 1 and its dependencies.

Foreign Patent Documents:

• EP0069429A2

  • Full Citation: EP 0 069 429 A2
  • Publication/Filing Date: Filed: Jul 6, 1981 / Published: Jan 12, 1983
  • Brief Description: Discloses an insulated gate field effect transistor.
  • Potential Anticipation (35 U.S.C. § 102): This patent describes an insulated gate FET. Similar to the MOS FET patents, the underlying technology (IGFET vs. GaN HEMT) and the specific multi-field plate architecture of US8169005B2 are likely not disclosed, thus limiting its ability to anticipate the claims.

• JPH0521793A

  • Full Citation: JP H05-21793 A
  • Publication/Filing Date: Filed: Jul 9, 1991 / Published: Jan 29, 1993
  • Brief Description: Describes a semiconductor device and manufacturing method thereof.
  • Potential Anticipation (35 U.S.C. § 102): Without specific details on the device structure, especially concerning multiple field plates in a GaN HEMT, it is unlikely to anticipate the specific claims of US8169005B2.

• JPH07283140A

  • Full Citation: JP H07-283140 A
  • Publication/Filing Date: Filed: Apr 5, 1994 / Published: Oct 27, 1995
  • Brief Description: Describes an active atom supply control method.
  • Potential Anticipation (35 U.S.C. § 102): This patent relates to a manufacturing method. It does not disclose the device structure or its functional characteristics, and thus would not anticipate any of the claims of US8169005B2.

• EP0792028A2

  • Full Citation: EP 0 792 028 A2
  • Publication/Filing Date: Filed: Feb 21, 1996 / Published: Aug 27, 1997
  • Brief Description: Discloses a solid-state antenna switch and field-effect transistor.
  • Potential Anticipation (35 U.S.C. § 102): This patent describes a FET for an antenna switch. While it involves FETs, without a detailed field plate configuration matching US8169005B2's multi-field plate arrangement, it is unlikely to anticipate the specific claims related to voltage blocking and on-resistance.

• JPH09307097A

  • Full Citation: JP H09-307097 A
  • Publication/Filing Date: Filed: May 16, 1996 / Published: Nov 28, 1997
  • Brief Description: Describes a semiconductor device.
  • Potential Anticipation (35 U.S.C. § 102): Without specific details on the device structure, especially concerning multiple field plates in a GaN HEMT, it is unlikely to anticipate the specific claims of US8169005B2.

• JPH09321307A

  • Full Citation: JP H09-321307 A
  • Publication/Filing Date: Filed: May 29, 1996 / Published: Dec 12, 1997
  • Brief Description: Describes a semiconductor device.
  • Potential Anticipation (35 U.S.C. § 102): Without specific details on the device structure, especially concerning multiple field plates in a GaN HEMT, it is unlikely to anticipate the specific claims of US8169005B2.

• JPH10223901A

  • Full Citation: JP H10-223901 A
  • Publication/Filing Date: Filed: Dec 4, 1996 / Published: Aug 21, 1998
  • Brief Description: Describes a field effect transistor and method of manufacturing the same.
  • Potential Anticipation (35 U.S.C. § 102): This patent describes a general FET and its manufacturing. Similar to other general FET references, it would need to explicitly teach the specific multiple field plate structure and its connections in a GaN HEMT to anticipate the claims of US8169005B2.

• JPH11261052A

  • Full Citation: JP H11-261052 A
  • Publication/Filing Date: Filed: Mar 9, 1998 / Published: Sep 24, 1999
  • Brief Description: Describes a high mobility transistor.
  • Potential Anticipation (35 U.S.C. § 102): This patent describes a high mobility transistor. While HEMTs are high mobility transistors, without the specific multi-field plate configuration, material system (GaN), and performance characteristics detailed in US8169005B2, it is unlikely to anticipate the claims.

• JP2000252458A

  • Full Citation: JP 2000-252458 A
  • Publication/Filing Date: Filed: Sep 9, 1999 / Published: Sep 14, 2000
  • Brief Description: Describes a field effect transistor.
  • Potential Anticipation (35 U.S.C. § 102): This patent describes a general FET. Similar to other general FET references, it would need to explicitly teach the specific multiple field plate structure and its connections in a GaN HEMT to anticipate the claims of US8169005B2.

Non-Patent Literature (NPL) Documents:

• B. Gelmont, K. Kim and M. Shur, Monte Carlo Simulation of Electron Transport in Gallium Nitride, J. Appl. Phys. 74, (1993), pp. 1818-1821.

  • Brief Description: This article discusses electron transport in Gallium Nitride.
  • Potential Anticipation (35 U.S.C. § 102): This NPL discusses the fundamental physics of GaN electron transport. It provides background on the properties of GaN, which is a material used in US8169005B2. However, it does not describe a device structure, and thus would not anticipate any of the claims of US8169005B2.

• R. Gaska, et al., Electron Transport in AlGaN—GaN Heterostructures Grown on 6H—SiC Substrates, Appl. Phys. Lett. 72, (1998), pp. 707-709.

  • Brief Description: This article discusses electron transport in AlGaN-GaN heterostructures grown on SiC substrates.
  • Potential Anticipation (35 U.S.C. § 102): This NPL is highly relevant as it describes AlGaN/GaN heterostructures on SiC, which forms the basis for the HEMT described in US8169005B2 (e.g., in Claim 7 and 15 related to semiconductor layers). It supports the understanding of 2DEG formation and electron mobility in such systems. However, similar to the patent US5192987A, it is unlikely to describe the specific multiple field plate architecture and its unique connections for high voltage/low on-resistance performance that are central to the claims of US8169005B2.

• Y. F. Wu et al., GaN-Based FETs for Microwave Power Amplification, IEICE Trans. Electron. E-82-C, (1999). pp. 1895-1905.

  • Brief Description: This article discusses GaN-based FETs for microwave power amplification, including power density results. Y. F. Wu is also an inventor on US8169005B2.
  • Potential Anticipation (35 U.S.C. § 102): This NPL, co-authored by an inventor, describes GaN-based FETs and their power performance. While highly relevant to the general field of GaN FETs for power applications, the key question for anticipation under 35 U.S.C. § 102 is whether it discloses the specific multiple field plate arrangement (first, second, and source-connected third field plates) and the precise performance metrics (blocking voltage and on-resistance combinations) that are claimed in US8169005B2. The patent abstract explicitly refers to field plates being used to enhance performance, implying that the specific combination of field plates in US8169005B2 is an advancement over prior art. This NPL might anticipate broader aspects of GaN FETs for power, but a detailed comparison of the field plate structure is necessary to determine if it fully anticipates claims like Claim 1, 7, 15, or 25. Given the "grace period" provisions for an inventor's own publication (35 U.S.C. 102(b)(1)(A)), if this publication falls within one year of the patent's effective filing date, it might not be considered prior art against the inventor's own claims. However, its presence as a citation suggests it's considered relevant background.

• Gaska, et al., High-Temperature Performance of AlGaN/GaN HFETs on SiC Substrates, IEEE Electron Device Letters, 18, (1997), pp. 492-494.

  • Brief Description: This article discusses the high-temperature performance of AlGaN/GaN HFETs on SiC substrates.
  • Potential Anticipation (35 U.S.C. § 102): This NPL details AlGaN/GaN HFETs on SiC, providing further background on the device platform of US8169005B2. However, it is unlikely to teach the specific multiple field plate configuration that provides the claimed high blocking voltages and low on-resistances in US8169005B2.

• Wu, et al. “High Al-content AlGaN/GaN HEMTs With Very High Performance”, IEDM-1999 Digest, pp. 925-927, Washington D.C., December 1999.

  • Brief Description: This article discusses high Al-content AlGaN/GaN HEMTs with very high performance. Y. F. Wu is also an inventor on US8169005B2.
  • Potential Anticipation (35 U.S.C. § 102): Similar to the other NPL by Wu et al., this reference describes high-performance AlGaN/GaN HEMTs. While contributing to the general knowledge of GaN HEMT performance, it needs careful examination to see if it explicitly discloses the specific multiple field plate design and resulting performance characteristics claimed in US8169005B2 (Claims 1, 7, 15, 25). The potential applicability of the grace period (35 U.S.C. 102(b)(1)(A)) would also be a factor here.

• Lu, et al. “AlGaN/GaN HEMTs on SiC With Over 100 GHz ft and Low Microwave Noise”, IEEE Transactions on Electron Devices, Vol. 48, No. 3, March 2001, pp. 581-585.

  • Brief Description: This article discusses AlGaN/GaN HEMTs on SiC with high gain-bandwidth product (fT) and low microwave noise.
  • Potential Anticipation (35 U.S.C. § 102): This NPL focuses on high-frequency performance (fT) and low noise. While it pertains to AlGaN/GaN HEMTs on SiC, its focus is different from the high blocking voltage and low on-resistance for power switching applications that are central to US8169005B2. Therefore, it is unlikely to anticipate the specific field plate structures designed for these power switching characteristics.

• Wu et al., “Bias-dependent Performance of High-Power AlGaN/GaN HEMTs”, IEDM-2001, Washington D.C., Dec. 2-6, 2001.

  • Brief Description: This article discusses bias-dependent performance of high-power AlGaN/GaN HEMTs, reporting high power densities. Y. F. Wu is also an inventor on US8169005B2.
  • Potential Anticipation (35 U.S.C. § 102): This NPL, again by an inventor, discusses high-power AlGaN/GaN HEMTs. The question of anticipation would depend on whether it details the specific multiple field plate configuration and the combinations of blocking voltage and on-resistance described in the claims of US8169005B2 (Claims 1, 7, 15, 25). The grace period consideration is also applicable here.

• Wu et al., High Al-Content AlGaN/GaN MOSFETs for Ultrahigh Performance, IEEE Electron Device Letters 19, (1998), pp. 50-53.

  • Brief Description: This article discusses high Al-content AlGaN/GaN MOSFETs for ultrahigh performance. Y. F. Wu is also an inventor on US8169005B2.
  • Potential Anticipation (35 U.S.C. § 102): This NPL, by an inventor, focuses on AlGaN/GaN MOSFETs. While using GaN, the device type (MOSFET vs. HEMT) is fundamentally different, and the claims of US8169005B2 are specific to HEMTs. Therefore, it is unlikely to anticipate the HEMT-specific claims of US8169005B2.

• Zhang et al., IEEE Electron Device Letters, Vol. 21, pp. 421-423 (September 2000).

  • Brief Description: This article discusses overlapping gate structures, or field plates, used to modify the electric field and enhance performance of GaN-based HEMTs at microwave frequencies. This NPL is explicitly mentioned in the background of US8169005B2.
  • Potential Anticipation (35 U.S.C. § 102): This NPL is highly relevant as it describes the use of field plates in GaN-based HEMTs. It likely anticipates the general concept of using field plates to modify electric fields and enhance performance in GaN HEMTs (e.g., portions of Claims 1, 7, and 15 related to field plates over the active region). However, US8169005B2 describes a specific multiple field plate arrangement with distinct connections (some gate-connected, one source-connected outermost field plate) for achieving particular high voltage and low on-resistance figures. Whether Zhang et al. teaches this exact combination and the associated performance thresholds needs careful comparison. It likely serves as a general prior art reference for field plates but might not fully anticipate the specific inventive combination of US8169005B2.

• Karmalkar et al., IEEE Trans. Electron Devices, Vol. 48, pp. 1515-1521 (March 2001).

  • Brief Description: This article presents simulations for field plate structures, predicting enhanced breakdown voltages. This NPL is explicitly mentioned in the background of US8169005B2.
  • Potential Anticipation (35 U.S.C. § 102): This NPL discusses the simulated benefits of field plates, specifically increased breakdown voltage. This is highly relevant to the objectives of US8169005B2. It might anticipate the concept of using field plates to improve breakdown voltage. However, similar to Zhang et al., whether it discloses the specific multiple field plate arrangement and the precise performance combinations for blocking voltage and on-resistance as claimed in US8169005B2 is crucial for anticipation of the independent claims.

• Ando et al., IEEE Electron Device Letters, Vol. 24, pp. 289-291 (May 2003).

  • Brief Description: This article demonstrates 10.3 W output power at 2 GHz using a 1 mm wide device on a SiC substrate, utilizing a similar structure with smaller gate dimensions. This NPL is explicitly mentioned in the background of US8169005B2.
  • Potential Anticipation (35 U.S.C. § 102): This NPL demonstrates the performance of GaN HEMTs with field plates. While it uses a "similar structure" to previous field plate designs, the critical question for anticipation is whether it explicitly discloses the specific multiple field plate arrangement (including the source-connected outermost field plate) and the combination of high blocking voltage and low on-resistance recited in the independent claims of US8169005B2. Its focus on output power at 2 GHz suggests a different performance optimization than the high voltage blocking of US8169005B2.

• Chini et al., IEEE Electron Device Letters, Vol. 25, No. 5, pp. 229-231 (May 2004).

  • Brief Description: This article implements a new variation of the field plate design with further reduced gate dimensions, achieving 12 W/mm at 4 GHz. This NPL is explicitly mentioned in the background of US8169005B2.
  • Potential Anticipation (35 U.S.C. § 102): This NPL introduces a "new variation of the field plate design" and reports power density results. Like Ando et al., the key for anticipation of US8169005B2's claims would be a direct disclosure of the specific multiple field plate arrangement and the achieved blocking voltage/on-resistance combinations. The different performance metrics and gate dimensions suggest a different design compared to the specific configuration in US8169005B2.

• Y-F Wu et al, IEEE Electron Device Letters, Vol. 25, No. 3, pp. 117-119 (March 2004).

  • Brief Description: This article reports GaN based HEMTs with field plates boosting power density to greater than 30 W/mm at frequencies up to 8 GHz. Y-F Wu is an inventor on US8169005B2. This NPL is explicitly mentioned in the background of US8169005B2 as demonstrating boosted power density.
  • Potential Anticipation (35 U.S.C. § 102): This NPL, by an inventor, is highly relevant as it describes GaN HEMTs with field plates achieving high power density. This reference, along with the other "Wu et al." NPLs, represents the state of the art in GaN HEMTs with field plates prior to the patent's priority date. For anticipation of US8169005B2's claims (Claims 1, 7, 15, 25), this reference would need to specifically disclose the combination of the first and second gate-connected field plates and the source-connected third field plate, and the resulting high blocking voltage and low on-resistance performance as claimed. The patent itself suggests that its multiple field plate transistor provides improvements over existing field plate designs. The grace period for an inventor's own work (35 U.S.C. 102(b)(1)(A)) would also need to be considered.

Summary of Most Relevant Prior Art for Anticipation:

The most relevant prior art documents for anticipation under 35 U.S.C. § 102 would be those that detail GaN HEMT structures with field plates, especially those that discuss improving breakdown voltage or reducing on-resistance.

• US5192987A (High electron mobility transistor with GaN/Alx Ga1-x N heterojunctions) and WO0004587A2 (Nitride based transistors on semi-insulating silicon carbide substrates / US6316793B1) are foundational for the GaN HEMT device itself and would likely anticipate the basic semiconductor layer structures (Claims 7, 8, 10, 16, 17, 18, 19).
• US6100571A (FET having non-overlapping field control electrode between gate and drain) is relevant to the general concept of field control electrodes between the gate and drain.
• Zhang et al. (2000), Karmalkar et al. (2001), Ando et al. (2003), Chini et al. (2004), and Y-F Wu et al. (2004) (NPLs) are highly relevant as they explicitly discuss the use of field plates in GaN-based HEMTs to modify electric fields, enhance performance, and predict/achieve increased breakdown voltages and power densities.

The core inventive step of US8169005B2 appears to be the specific arrangement of multiple field plates, including both gate-connected field plates and an outermost source-connected field plate, to achieve particular high blocking voltage and low on-resistance combinations for power switching applications. While the cited prior art introduces elements of GaN HEMTs and the general use of field plates, a detailed analysis would be required to determine if any single reference, or combination of references (for obviousness under 35 U.S.C. § 103), fully teaches or renders obvious this precise combination of structural features and the claimed performance metrics. The patent itself states that prior art approaches "have limitations for high performance applications in power switching," implying that the specific configuration of US8169005B2 addresses these limitations.

Obviousness Analysis of US Patent 8169005 under 35 U.S.C. § 103

A patent claim is obvious if "the differences between the claimed invention and the prior art are such that the subject matter as a whole would have been obvious at the time the invention was made to a person having ordinary skill in the art" (35 U.S.C. § 103). This analysis considers the scope and content of the prior art, the differences between the prior art and the claims, the level of ordinary skill in the pertinent art, and any secondary considerations of nonobviousness (which are not available in the provided text).

The person having ordinary skill in the art (PHOSITA) for US8169005 would be a semiconductor device engineer with expertise in GaN High Electron Mobility Transistor (HEMT) technology, particularly as applied to power electronics design and fabrication. The relevant time for assessing obviousness is before the patent's priority date of November 21, 2006.

Prior Art Landscape

The "Description" section of US8169005 identifies several pieces of prior art crucial to understanding the state of the art before the invention:

• GaN HEMT Structures: Patents such as U.S. Pat. Nos. 6,316,793, 5,192,987, and 5,296,395 establish the foundational components of AlGaN/GaN HEMTs, including substrates (e.g., SiC), buffer layers (e.g., GaN), and barrier layers (e.g., AlGaN) that define the active two-dimensional electron gas (2DEG) region.
• Field Plates in GaN HEMTs: The application of field plates to GaN HEMTs for performance enhancement was a known technique.
  • Zhang et al., IEEE Electron Device Letters (September 2000): Taught the use of "overlapping gate structures, or field plates, ... to modify the electric field and thereby enhance the performance of GaN-based HEMTs at microwave frequencies."
  • Karmalkar et al., IEEE Trans. Electron Devices (August 2001): Simulations predicted "up to five times enhancement in breakdown voltages" using field plate structures.
  • Ando et al. (May 2003), Chini et al. (May 2004), and Y-F Wu et al. (March 2004): Demonstrated practical achievements in power output and power density in GaN HEMTs through the use of field plates.
  • US Patent Application Publication Nos. 20050051796 and 20050051800, and International Application Publication No. WO/2005/024909: Explicitly disclose "Transistors with field plates and methods of fabricating such transistors," indicating well-established knowledge of field plate implementation in GaN HEMTs by 2005.
• Recessed Gates: US Patent Application Publication No. 20060019435, titled "Methods of Fabricating Nitride-Based Transistors with a Cap Layer and a Recessed Gate," directly teaches the fabrication of recessed gates in nitride-based transistors.

The core problem addressed by US8169005 is achieving higher blocking voltages and lower on-resistances for power switching applications, building upon existing field plate technology. The patent highlights that while prior art field plates boosted power density, they had "limitations for high performance applications in power switching."

Obviousness Analysis of Independent Claims

Claim 1

Claim Language: "A transistor device, comprising: an active region; a source; a drain; a gate structure electrically connected to said active region; a plurality of field plates disposed over said active region; a plurality of insulating spacer layers, a first of said spacer layers interposed between a first of said field plates and said active region, others of said spacer layers disposed on said first field plate; wherein at least one field plate is electrically connected to said gate structure, said first of said field plates is integral to said gate and extends on said first spacer layer toward said source, and at least one field plate is connected to said source."

Differences from Prior Art: The primary distinction in Claim 1 is the specific multi-field-plate configuration: a first field plate integral to the gate extending towards the source, and importantly, "at least one field plate is connected to said source." While field plates connected to the gate were known, the deliberate incorporation of a source-connected field plate within a multiple field plate architecture is a key element.

Combination and Motivation: A PHOSITA would be motivated to combine the general knowledge of GaN HEMTs with field plates (as taught by US Patent Application Publication Nos. 20050051796, 20050051800, or WO/2005/024909) with the understanding of the performance trade-offs associated with purely gate-connected field plates. The patent itself provides explicit motivation for connecting a field plate to the source: "By having a field plate electrically connected to the source electrode, the reduced gain and instability resulting from gate connected field plates is reduced. When arranged according to the present invention, the shielding effect of a source-connected field plate can reduce capacitance between the gate and the drain (C gd ), which enhances input-output isolation." A PHOSITA seeking to mitigate issues like reduced gain, instability, or high Cgd in field-plated HEMTs would find it obvious to add or modify a field plate to be electrically connected to the source to achieve this described shielding effect and improve input-output isolation. This combination addresses a recognized problem in the field using known components with a predictable result.

Claim 7

Claim Language: "A transistor device, comprising: a substrate; a plurality of semiconductor layers on said substrate; a source; a drain; a gate structure electrically connected to said semiconductor layers, said gate comprising a contact portion and an overlay portion; a plurality of field plates disposed on said active region; a plurality of insulating spacer layers, a first of said spacer layers interposed between said overlay portion and said semiconductor layers, others of said spacer layers disposed on said overlay portion and interspersed between others of said field plates; wherein said contact portion of said gate is recessed in said first spacer layer such that said contact portion contacts said semiconductor layers, and wherein said overlay portion is on said first spacer layer opposite said plurality of semiconductor layers."

Differences from Prior Art: The core distinctions of Claim 7 are the gate structure comprising a "contact portion and an overlay portion", where the contact portion is "recessed in said first spacer layer such that said contact portion contacts said semiconductor layers", and the overlay portion resides on the first spacer layer.

Combination and Motivation: A PHOSITA would be motivated to combine the known technology of field-plated GaN HEMTs (e.g., from US Patent Application Publication Nos. 20050051796, 20050051800, or WO/2005/024909) with the teachings of recessed gates in nitride-based transistors, as explicitly described in US Patent Application Publication No. 20060019435 ("Methods of Fabricating Nitride-Based Transistors with a Cap Layer and a Recessed Gate"). The "overlay portion" on the first spacer layer is a characteristic feature of a T-gate structure, which was a known design choice in HEMT technology to reduce gate resistance and improve high-frequency performance. Integrating a recessed gate (for threshold voltage control and reduced leakage) into a field-plated HEMT (for enhanced breakdown voltage) would be an obvious design optimization for a PHOSITA seeking to improve overall transistor characteristics. The patent itself notes that a HEMT embodiment "may include a gate that is partially recessed in the barrier layer."

Claim 15

Claim Language: "A transistor device, comprising: a plurality of semiconductor layers including an active region; a source; a drain; a gate structure electrically connected to said active region; a plurality of field plates on said active region; a plurality of insulating spacer layers, a first of said spacer layers interposed between a first of said field plates and said active region, others of said spacer layers on said first field plate; wherein said first spacer layer comprises an epitaxial material, said first of said field plates is integral to said gate and extends on said first spacer layer toward said source."

Differences from Prior Art: The central distinguishing feature of Claim 15 is that the "first spacer layer comprises an epitaxial material."

Combination and Motivation: A PHOSITA would be motivated to combine the established architecture of field-plated GaN HEMTs with insulating spacer layers (e.g., from US Patent Application Publication Nos. 20050051796, 20050051800, or WO/2005/024909) with the fundamental knowledge and common practice of epitaxial growth for Group III nitride layers in HEMT fabrication (e.g., buffer and barrier layers as detailed in U.S. Pat. Nos. 5,210,051; 5,393,993; 5,523,589; and 5,592,501). The patent explicitly provides the motivation for this combination: "When the spacer layers are formed before device metallization, the layers can be an epitaxial material... After epitaxial growth of the barrier layer 16, the spacer layers 26 and 28 can be grown using the same epitaxial growth method." This indicates a clear engineering motivation to simplify the fabrication process, leverage existing epitaxial growth capabilities for nitride materials, and ensure material compatibility and quality, particularly when the spacer layers are formed prior to metallization.

Claim 25

Claim Language: "A transistor device, comprising: a substrate; a plurality of semiconductor layers on said substrate; a source; a drain; a gate structure electrically connected to said semiconductor layers, said gate comprising a contact portion and an overlay portion; a plurality of field plates disposed over said active region; a plurality of insulating spacer layers, a first of said spacer layers interposed between said overlay portion and said semiconductor layers, others of said spacer layers disposed over said overlay portion and interspersed between others of said field plates; wherein said contact portion of said gate is recessed in said first spacer layer such that said contact portion contacts said semiconductor layers, wherein said overlay portion is on said first spacer layer opposite said plurality of semiconductor layers, wherein said gate overlay portion extends a distance on said first spacer layer toward said source on one side and extends a distance on said first spacer layer toward said drain on the opposite side, wherein an outermost of said field plates at least partially overlaps said gate and extends a distance toward said drain, and wherein said gate overlay portion extends a greater distance toward said source than toward said drain."

Differences from Prior Art: This claim combines features from Claim 7 (recessed gate, overlay portion) and Claim 1 (multi-field-plate arrangement, including a source-connected outermost field plate) with specific dimensional optimizations. The key distinguishing feature is that the "gate overlay portion extends a greater distance toward said source than toward said drain."

Combination and Motivation: This claim represents a combination of the features found in Claim 7 (recessed gate, gate overlay portion, by combining US20060019435 with general field plate HEMTs) and the multi-field-plate arrangement described in the patent's own detailed description (e.g., field plate 30 connected to the gate extending toward the source, field plate 32 connected to the gate extending toward the drain, and the outermost field plate 36 connected to the source extending toward the drain). A PHOSITA designing multi-field-plate GaN HEMTs would routinely optimize the dimensions and placement of various field plates to achieve desired performance characteristics, such as high breakdown voltage, low on-resistance, and reduced Cgd. The patent explicitly aims for "high blocking voltages... while simultaneously exhibiting on resistances of 7.0 mΩ-cm 2 or lower." Given the motivation to reduce Cgd using source-connected field plates (as identified in the analysis of Claim 1), and the general goal of optimizing electric field distribution, a PHOSITA would be motivated to experiment with the relative lengths of the gate-connected field plate extensions. Determining that a greater extension towards the source for the gate-connected field plate(s) (i.e., the "gate overlay portion") yields a better balance of performance parameters (e.g., Cgd, breakdown, and resistance) would be a matter of routine optimization and not necessarily inventive. The placement of the outermost field plate to overlap the gate and extend towards the drain is also consistent with established principles for managing the drain-side electric field to enhance breakdown voltage.