US 8169005

US Patent 8169005, titled "High voltage GaN transistors," was issued to Cree Inc. (original assignee) and is currently assigned to Wolfspeed Inc.. The inventors listed are Yifeng Wu, Primit Parikh, and Umesh Mishra. The patent has a priority date of November 21, 2006, a filing date of January 26, 2011, and an issue date of May 1, 2012.

Abstract:
The patent describes a multiple field plate transistor featuring an active region, a source, a drain, and a gate. It includes a first spacer layer positioned over the active region between the source and the gate, and a second spacer layer over the active region between the drain and the gate. A first field plate, located on the first spacer layer, is connected to the gate, and a second field plate, on the second spacer layer, is also connected to the gate. A third insulating spacer layer covers the first and second spacer layers, the first and second field plates, and the gate, with a third field plate on this third spacer layer connected to the source. The disclosed transistor is designed to achieve high blocking voltages (at least 600 Volts or at least 900 Volts) while maintaining low on-resistances (e.g., no more than 5.0 mΩ-cm² for 2 Amps at 600V, or no more than 7.0 mΩ-cm² for 3 Amps at 900V).

Plain-Language Overview of Independent Claims:

• Claim 1: This claim describes a transistor device comprising an active region, a source, a drain, and a gate structure connected to the active region. It features multiple field plates over the active region and multiple insulating spacer layers. A key aspect is that a first field plate is integrated with the gate, extends over a first spacer layer towards the source, and is electrically connected to the gate. Additionally, at least one other field plate is connected to the source.
• Claim 7: This independent claim describes a transistor device that includes a substrate and several semiconductor layers on it. It specifies a gate structure with two parts: a contact portion recessed into a first spacer layer to make contact with the semiconductor layers, and an overlay portion situated on the first spacer layer above the semiconductor layers. The device also includes multiple field plates over the active region and several insulating spacer layers, with some layers located between the gate overlay portion and the semiconductor layers, and others interspersed between the field plates.
• Claim 15: This claim outlines a transistor device with semiconductor layers that form an active region, along with a source, a drain, and a gate structure connected to the active region. It includes multiple field plates over the active region and multiple insulating spacer layers. A distinctive feature is that the first insulating spacer layer is made of an epitaxial material, and a first field plate, integrated with the gate, extends over this epitaxial first spacer layer towards the source.
• Claim 25: This claim details a transistor device built on a substrate with semiconductor layers, a source, a drain, and a gate structure connected to the semiconductor layers. The gate has a contact portion recessed into a first spacer layer, contacting the semiconductor layers, and an overlay portion on the first spacer layer. This gate overlay portion extends towards both the source and the drain, but notably, it extends a greater distance towards the source. An outermost field plate partially overlaps the gate and extends towards the drain.

As of April 26, 2026, no specific information regarding US patent 8169005 was found in the provided CAFC 2026 docket search results. Comprehensive CAFC docket information for specific cases is typically available through PACER, which was not directly searched.