US 10998418

US Patent 10998418: Power Semiconductor Devices with Reflowed Inter-Metal Dielectric Layers

Title: Power semiconductor devices having reflowed inter-metal dielectric layers

Assignee:

• Current Assignee: Wolfspeed Inc.
• Original Assignee: Cree Inc

Inventors: Edward R. Van Brunt, Daniel J. Lichtenwalner, Shadi Sabri

Filing Date: May 16, 2019

Issue Date: May 4, 2021

Abstract:
The patent describes power semiconductor devices that incorporate multi-layer inter-metal dielectric patterns. These patterns include at least one reflowed dielectric material pattern and at least one non-reflowable dielectric material pattern. In other disclosed embodiments, the reflowed inter-metal dielectric patterns are created using sacrificial structures (referred to as "dams") during the reflow process to control the lateral spreading of the reflowable dielectric material. The goal of these innovations is to achieve improved shapes and performance for the inter-metal dielectric patterns.

---

Plain-Language Overview of Independent Claims:

US Patent 10998418 includes multiple independent claims detailing various aspects of the power semiconductor devices and their fabrication methods.

Independent Claim 1 (Device Structure):
This claim describes a semiconductor device comprising:

• A wide bandgap semiconductor layer structure.
• A gate electrode structure situated on the upper surface of the wide bandgap semiconductor layer structure.
• An inter-metal dielectric pattern positioned on the gate electrode structure. This pattern is distinguished by containing both a non-reflowable dielectric material pattern and a reflowed dielectric material pattern.
• A source metallization structure located on the inter-metal dielectric pattern.
  The claim specifies that the gate electrode structure is between the wide bandgap semiconductor layer structure and the inter-metal dielectric pattern, and the inter-metal dielectric pattern is between the gate electrode structure and the source metallization structure.

Independent Claim 13 (Device Structure with Vertical Sidewalls):
This claim outlines a semiconductor device similar to Claim 1, including a wide bandgap semiconductor layer structure, a gate electrode structure, an inter-metal dielectric pattern, and a source metallization structure. The key distinguishing feature here is that the inter-metal dielectric pattern comprises a reflowed dielectric material pattern, and a lower portion of this reflowed dielectric material pattern has substantially vertical sidewalls.

Independent Claim 20 (Fabrication Method - Multi-layer IMD):
This claim details a method for fabricating a semiconductor device, involving:

• Forming a wide bandgap semiconductor layer structure.
• Forming a conductive pattern on the upper surface of this structure.
• Forming a non-reflowable dielectric material pattern on the conductive pattern.
• Forming a reflowable dielectric material layer (containing reflowable dielectric material) on the conductive pattern.
• Reflowing the reflowable dielectric material.
• Forming a source metallization structure on an inter-metal dielectric pattern, where this inter-metal dielectric pattern includes the previously formed non-reflowable dielectric material pattern and a reflowed dielectric material pattern (derived from the reflowable material).

Independent Claim 33 (Fabrication Method - Sacrificial Structures):
This claim describes another fabrication method for a semiconductor device, comprising:

• Forming a wide bandgap semiconductor layer structure.
• Forming a plurality of spaced-apart gate fingers on its upper surface.
• Forming a reflowable dielectric material layer on the gate fingers.
• Forming sacrificial structures on the wide bandgap semiconductor layer structure within the gaps between the gate fingers.
• Reflowing the reflowable dielectric material.
• Forming a source metallization pattern on an inter-metal dielectric pattern, which includes the reflowed dielectric material pattern.

Independent Claim 40 (Device Structure - Two Silicon Oxide Patterns, Ratio Less Than 4-to-1):
This claim specifies a semiconductor device with:

• A wide bandgap semiconductor layer structure.
• A gate electrode structure on the upper surface of the wide bandgap semiconductor layer structure.
• An inter-metal dielectric pattern on the gate electrode structure, which includes at least a first silicon oxide pattern and a second silicon oxide pattern made of a different material than the first.
• A source metallization structure on the inter-metal dielectric pattern.
  Crucially, the gate electrode structure is between the wide bandgap semiconductor layer structure and the inter-metal dielectric pattern, and the inter-metal dielectric pattern is between the gate electrode structure and the source metallization structure. A defining characteristic is that the ratio of a maximum thickness of the inter-metal dielectric pattern to a minimum thickness of the inter-metal dielectric pattern is less than 4-to-1.

---

CAFC 2026 Dockets:

As of April 26, 2026, a direct search of CAFC 2026 dockets for the specific patent number 10998418 did not return a definitive docket entry. However, a news report dated July 7, 2026, indicates that Wolfspeed (the current assignee of US10998418) has filed a patent infringement lawsuit against Navitas Semiconductor, asserting that a broad range of Navitas products infringes multiple Wolfspeed patents, including U.S. Patent No. 10,998,418. This suggests ongoing litigation involving the patent, although the specific CAFC docket details for 2026 are not immediately available from the provided search results. The mention of this patent in a lawsuit initiated by Wolfspeed highlights its current relevance in intellectual property disputes.