US 8242551

I'll verify the patent details against live sources before summarizing.

No CAFC 2026 docket hits yet for this patent number. Let me run two more targeted searches.

Let me check specifically for any USPTO/PTAB or 2026 appellate activity tied to this patent number.

US 8,242,551 B2 — Verification Summary

Source of record: https://patents.google.com/patent/US8242551/en (fetched 2026-09-24). Note: this is a Google Patents mirror of the USPTO record, not a direct PatentCenter query — see the caveat at the end.

Bibliographic data

Family / related matters:

• Divisional: US 13/555,831, filed 2012-07-23, granted as US 8,987,086 B2, titled "MIM capacitor with lower electrode extending through a conductive layer to an STI." (This divisional title is itself a useful plain-language restatement of the inventive core.)
• Chinese counterpart: CN 101826560 B (priority date listed as 2009-09-24).
• Cited-by (front page): 3 items, including US 2013/0015558 A1 (Elpida Memory) and US 9,911,650 B2 (TSMC).

Abstract (as printed)

"The present disclosure provides a semiconductor device that includes a semiconductor substrate, an isolation structure formed in the semiconductor substrate, a conductive layer formed over the isolation structure, and a metal-insulator-metal (MIM) capacitor formed over the isolation structure. The MIM capacitor has a crown shape that includes a top electrode, a first bottom electrode, and a dielectric disposed between the top electrode and the first bottom electrode, the first bottom electrode extending at least to a top surface of the conductive layer."

Plain-language overview of the independent claims

The patent has three independent claims: 1, 13, and 19. All are apparatus claims; the specification describes a fabrication method (blocks 402–422 in FIG. 4 and 602–616 in FIG. 6) but no method claims were granted.

Claim 1 — the base device claim (narrowest-of-the-three as issued)
A chip containing a substrate, a shallow-trench-type isolation region in the substrate, a conductive layer (doped polysilicon/silicide per the spec) sitting on top of that isolation region, and a crown-shaped MIM capacitor above the isolation region. The capacitor has a top electrode, a first bottom electrode, and a dielectric between them. The key limitation: the first bottom electrode extends completely through the conductive layer and physically contacts a portion of the isolation structure — i.e., the capacitor's bottom plate is etched down into/onto the STI rather than stopping on the polysilicon. This is the "deeper is bigger" concept: pushing the electrode down through the poly layer lengthens the electrode sidewall, increasing electrode surface area (and thus capacitance) without enlarging the capacitor's footprint.

Claim 13 — the dual-region (SoC) claim
A substrate divided into a first region and a second region. In region one, a first crown-shaped MIM capacitor over the isolation structure. In region two, a memory cell containing a second crown-shaped MIM capacitor sharing the same dielectric layer. The distinguishing limitation is a relative-depth relationship: the first capacitor's bottom electrode is a smaller distance from the substrate than the second (memory-cell) capacitor's bottom electrode — in other words, the decoupling/SoC capacitor is sunk deeper than the DRAM-style capacitor. The claim closes by requiring the first bottom electrode to extend through the conductive layer at least to the top surface of the isolation structure. Dependent claims 14–18 add a CMOS logic region (claim 14), an embedded DRAM cell with a transistor and contact (claim 15), the conductive poly layer and silicide (16–17), and extension into a portion of the isolation structure (18).

Claim 19 — the "at least to the top surface" claim
Structurally similar to claim 1, but the bottom electrode is first recited as extending at least to a top surface of the conductive layer, and then further required to extend through the conductive layer at least to a top surface of the isolation structure. Claim 20 then adds the further-embodiment limitation of extending through a portion of the isolation structure. In substance, claims 19–20 read as a narrower, staged version of claim 1's "completely through" limitation, and track the pre-grant published claim 1 + claim 2 + claim 3 hierarchy.

Dependent claim highlights (claims 2–12, 20): high-k dielectric (claim 2/4); silicide layer over a doped polysilicon conductive layer with the bottom electrode coupled to the silicide (claim 3/5); a second bottom electrode coupled to the first via the conductive layer, giving two parallel capacitors sharing one top electrode (claim 4/6); rounded corner profile on the bottom electrode for increased capacitance and improved TDDB reliability (claim 5, 7, 9); STI as the isolation structure (claim 12); and an etch stop layer over the first ILD in the second region but absent from the second trench (claim 7).

Two textual points worth flagging (literal reading, not auto-correction)

1. Claim set changed between publication and grant. Pre-grant publication US 2010/0224925 A1 (per the Justia copy of the same text) presented claim 1 as ending "…the first bottom electrode extending at least to a top surface of the conductive layer." The granted claim 1 instead recites "extending completely through the conductive layer and physically contacting a portion of the isolation structure." The granted set therefore narrowed independent claim 1 relative to the published application, and re-cast the published concept as new independent claim 19.

2. Claim 13 appears to contain a typographical error. It recites "a dielectric disposed between the first top electrode and the first top electrode" (repeated "top," where "first bottom electrode" is evidently intended; compare the parallel second-capacitor clause, which correctly says "between the second top electrode and the second bottom electrode"). I am reporting this as it literally appears in the text; the USPTO certificate, not this mirror, would control. Relatedly, claim 13's final "wherein" clause refers to "the conductive layer," which has no antecedent basis earlier in claim 13 — a point I note as an observation only.

Litigation / 2026 CAFC check — null result

I ran targeted searches against Federal Circuit 2026 docket listings and PTAB/ITC materials for patent number 8,242,551 and found no record of this patent appearing in any 2026 CAFC docket, PTAB (IPR/PGR) proceeding, ITC Section 337 investigation, or district court complaint. The "551"-adjacent hits my searches surfaced are unrelated patents — e.g., U.S. Reissue Patent RE38,551 (UCB/lacosamide litigation), the Abbott/BD "551 patent" from the 2008–2010 appeals, and various unrelated '194/'609/'180 patents in the Marlin Semiconductor / Longitude Licensing v. TSMC ITC and IPR disputes. None of those involve US 8,242,551.

Uncertainty caveat: a search returning nothing is weaker evidence than a positive hit, and I could not query USPTO PatentCenter or CAFC's docket system directly (only indexed web results). So I cannot state with high confidence that this patent has never been litigated, only that I found no 2026 CAFC or USPTO post-grant activity referencing this specific number. For an authoritative litigation and status check, the primary sources would be USPTO PatentCenter / Assignment records and the CAFC and PTAB docket systems queried directly by patent number, plus an IPR/adverse-proceeding review — I did not have direct access to those in this session.

I'll search for litigation involving US patent 8242551 across patent litigation sources.

Let me search more targeted litigation databases.

Let me try more targeted searches on litigation databases.

Litigation Search Results: U.S. Patent No. 8,242,551

Bottom line: I found no evidence of any litigation involving U.S. Patent No. 8,242,551.

What I searched

I ran queries against general web and patent-litigation-focused sources (including searches designed to surface Unified Patents portal, RPX Insight, and CourtListener/PACER-type records), specifically for the literal string "8242551" / "8,242,551" tied to litigation terms (infringement, defendant, district court, lawsuit). I did not have reliable direct access to the Unified Patents litigation caselist or PACER in this session; results were drawn from indexed web content.

Findings

• No district court case, ITC action, CAFC appeal, or PTAB proceeding (IPR/PGR) naming U.S. 8,242,551 as a patent-in-suit was returned.
• The only hits for "8242551" in a patent context were:
  • The Google Patents page for US8242551B2 itself (TSMC, "Metal-insulator-metal structure for system-on-chip technology"), and
  • A Patent Leaderboard entry listing it among inventor Chun-Yao Chen's patents (a portfolio reference, not litigation).
• Several search hits that appeared relevant were false matches to different identifiers and should not be attributed to this patent:
  • Pantech/NPE complaints referencing a "′824 Patent" — that is a different patent number ending in 824, not 8,242,551.
  • TSMC v. Cohen (N.D. Cal.) — asserted patents were U.S. 6,518,668; 6,924,226; 7,199,052; 7,282,445 (not the '551).
  • Advanced Integrated Circuit Process LLC v. TSMC / UMC (E.D. Tex.) — asserted patents described as '751, '623, '572, '373, '779, '425 (not the '551).
  • "′551 Patent" hits (e.g., Johns Hopkins v. Datascope; Therasense) refer to unrelated patents/numbers.

Required fields for each case

Because no case was identified, there are no plaintiff(s), defendant(s), jurisdiction, case number, filing date, or outcome/status to report.

Caveats (please read)

1. This is a negative finding, not a certified clearance search. Absence from indexed web results does not prove no litigation exists. Litigation databases (PACER, Unified Patents Portal, RPX Insight, Docket Navigator, Lex Machina) are the authoritative sources and some are paywalled or not fully indexed by web search.
2. Legal-status caveat: U.S. 8,242,551 is shown on Google Patents as Active (adjusted expiration 2029-07-31), with a division/continuation child U.S. 8,987,086 (filed 2012-07-23, "MIM capacitor with lower electrode extending through a conductive layer to an STI"). Litigation could be asserted on the family member rather than this exact patent — worth checking separately.
3. Google Patents' "Cited By" and "Families Citing" lists for this patent show patent-to-patent citations only, not litigation.

Recommended next steps for a definitive answer

Search these authoritative sources directly by patent number:

• Unified Patents Portal: https://portal.unifiedpatents.com/litigation/caselist (filter by patent)
• RPX Insight (litigation): https://insight.rpxcorp.com
• PACER / CourtListener RECAP: https://www.courtlistener.com/?q=%228242551%22
• PTAB (IPR/PGR): https://developer.uspto.gov / PTAB Trial Tracker, and USPTO Patent Public Search "litigation" tab
• ITC EDIS: https://edis.usitc.gov

If you'd like, I can run additional targeted queries (e.g., against USPTO Patent Assignment/PTAB records or the family member 8,987,086) once search capacity is available.

I'll verify the structured data against live sources before writing anything.

Let me run more targeted queries, including the divisional patent.

PTAB Proceedings Report — U.S. Patent No. 8,242,551

Patent: Metal-insulator-metal structure for system-on-chip technology
Patent Owner / current assignee: Taiwan Semiconductor Manufacturing Company, Ltd. (TSMC)
App. No. 12/397,948 · Filed 2009-03-04 · Issued 2012-08-14 · Adjusted expiration 2029-07-31
Source of record: US8242551B2, Google Patents (fetched 2026-09-24; authoritative for this report)

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Proceedings overview

Total AIA trial proceedings on file: zero (0 active, 0 claims invalidated, 0 claims sustained, 0 settled, 0 institution denied). The USPTO Open Data Portal returns no AIA trial proceedings for this patent as of the most recent ingest, and my independent web searches surfaced no IPR, PGR, or CBM petition naming U.S. Patent No. 8,242,551. Bottom line for a defendant: there is no PTAB record to lean on — all 20 claims are UNTESTED and presumptively valid, no claim is canceled, and no petitioner has incurred § 315(e) estoppel; an IPR-based defense would be a first-instance fight, not a follow-on to someone else's win. Conversely, the patent is also unvalidated and un-hardened: no panel has ever construed its claims, so there is no adverse claim-construction or priority record to exploit.

Because there are zero proceedings, the per-proceeding template below is empty by construction; I have not fabricated proceeding numbers, panels, grounds, or dispositions. What follows is the verification record, the structural reason for the absence, and the strategic read.

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Per-proceeding detail

Not applicable — no proceeding exists to report. No IPR, PGR, or CBM number, filing date, panel, institution decision, Final Written Decision, settlement, or Federal Circuit appeal can be reported for U.S. 8,242,551 without inventing the data.

Verification performed (2026-09-30)

Caveat, stated plainly: ODP ingest can lag behind filings, and my searches were general web queries, not a direct PTAB E2E docket query. A recent or sealed-until-service petition could exist without appearing above. Confirm directly at PTAB E2E (PTAB Center) and USPTO Patent Center before relying on the zero count in a filing or client memo.

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Strategic summary

Claim status: all 20 claims UNTESTED; none CANCELED, none SUSTAINED. Claims 1, 13, and 19 are the independents (claim 1: MIM capacitor over an isolation structure, first bottom electrode extending completely through the conductive layer and physically contacting a portion of the isolation structure; claim 13: the SoC/memory-cell two-region variant; claim 19: the "at least to a top surface of the conductive layer" variant further requiring extension through the conductive layer to a top surface of the isolation structure). The dependent set is claims 2–12, 14–18, and 20. Every one of these claims stands with the full statutory presumption of validity under § 282 and zero prosecution-through-IPR narrowing — there is no PTAB-issued claim construction, no disclaimer, and no certificate canceling or confirming anything. Note also the § 112-family wrinkle visible on the face of claim 13 ("a dielectric disposed between the first top electrode and the first top electrode") — a typo in the printed claim, uncorrected, and never litigated anywhere. Also note the divisional U.S. 8,987,086 (granted 2015-03-24), which claims overlapping subject matter and would very likely be asserted alongside the '551 patent; it, too, has no PTAB history.

Estoppel landscape: nothing is barred. Because no petitioner has ever filed an IPR/PGR against this patent, § 315(e)(2) estoppel is empty. There is no "raised or reasonably could have been raised" bar running against any party, and no privity chain to worry about. A defendant today may seek IPR on any § 102/§ 103 ground, using any art, including art already of record, art cited in the Google/ODP citation tables (e.g., U.S. 7,275,751 (IBM, trench MIM integrated with middle-of-line contacts); U.S. 7,074,669; U.S. 7,125,424 (TSMC, improved bottom electrodes for MIM crown capacitors); U.S. 6,295,420 (TI); US 2004/0201053 A1 (TSMC, embedded DRAM for MIM capacitor structure)) — and including the patent owner's own earlier work, which is often the strongest art against a crown-electrode extension claim. The counterweight is § 325(d) and Advanced Bionics: art already applied or considered during prosecution is a discretionary-denial risk, so the highest-value art will be the references the examiner never saw.

Pattern signals: none. There is no repeat petitioner, no patent-owner appellate practice, and no defensive aggregator (no Unified Patents, RPX, or similar) anywhere in the record with respect to this patent. That is consistent with the patent's identity: it is a TSMC portfolio/defensive patent, not a monetization asset. It has never, so far as I can determine, been asserted in district court or at the ITC, and its citation neighbors are TSMC's own later filings (e.g., U.S. 9,911,650; US 2022/0115370 A1, "Semiconductor device with short-resistant capacitor plate") plus third-party crow/capacitor patents. Two structural consequences: (1) a defendant is most likely facing this patent defensively in a TSMC counterclaim/portfolio exchange or in a supplier indemnity dispute, not in a troll demand letter — so the "cancelled claim = troll has no case" framing does not apply here; and (2) because the patent has been in force since 2012 (well over six years), a new IPR petition faces meaningful discretionary-denial risk under current Director-level institution practice, which weighs patent age as "settled expectations" — see the Acting/Current Director's institution memoranda as reported in Willkie, "PTAB Announces New Institution Policy" (2025-10-16 memo) and the empirical discussion of the settled-expectations doctrine at Fed Circuit Blog.

Term math matters here. Adjusted expiration is 2029-07-31 — roughly three years of enforceable life remaining, and that assumes the 11.5/7.5-year maintenance fees are paid. Any IPR on a patent with under three years left has a poor cost/benefit profile (statutory FWD deadline is one year from institution, § 316(a)(11)), which is a further reason the absence of IPRs is unsurprising.

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Recommended next steps

1. If you are a defendant and you were counting on an IPR win: there isn't one. Do not cite any proceeding number for this patent — none exists. If a demand letter or counterclaim cites claims 1–20, all 20 are live, so prepare a § 282 invalidity and non-infringement case on the merits, or file first-instance.
2. Confirm the zero count before you rely on it. Run the patent number through PTAB E2E and Patent Center on the day of your filing. Also check the sibling U.S. 8,987,086 and the Chinese family member CN101826560B — the divisional shares the specification and is equally un-IPR'd, and it is the more likely vehicle for a parallel-crown/MIM assertion.
3. If you are contemplating a petition: act on the § 315(b) clock from the moment you are served (one year), and budget for a discretionary-denial fight on two fronts — patent age ("settled expectations") and § 325(d)/Advanced Bionics if your art overlaps the ~25 references already of record. Prefer art outside the citation tables.
4. If you are the patent owner: the absence of PTAB activity is a clean-slate asset — no estoppel, no narrowing, no adverse claim construction. Preserve it by avoiding any narrowing amendment or prosecution disclaimer, and note that the uncorrected claim-13 antecedent-basis error is a latent § 112 exposure if that claim is ever asserted; consider a certificate of correction now, before any litigation freezes the record (and before any IPR gives the Board exclusive jurisdiction over the patent under 37 C.F.R. § 42.3(a)).
5. Set a watch. Nothing about this patent suggests it will stay quiet forever; if it is ever asserted, an IPR is likely to follow within the § 315(b) window, and the first FWD will define its surviving scope. Track PTAB filings against U.S. 8,242,551 and U.S. 8,987,086.

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Prepared 2026-09-30. No AIA trial proceeding on U.S. 8,242,551 is reported in the USPTO ODP structured data or surfaced by the web searches described above. All claim-status statements are therefore statements of absence, not findings of validity. Nothing here is legal advice.

I'll verify the assignment record against live sources before writing anything.

Let me dig for the specific reel/frame of the original TSMC assignment and check for any later transfers.

Let me try to pin down the reel/frame for the original TSMC assignment and verify there are no downstream transfers.

I hit the session's tool-call limit before I could pull the raw Assignment Center cover sheet for this patent. Below is the record as reconstructed from the authoritative Google Patents legal-events block supplied in the patent text, plus the surrounding evidence I did obtain. Where I could not capture a reel/frame, I say so rather than inventing one.

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Inventors

Pattern check — "inventors departing within 12 months of filing": NOT PRESENT. This is the key negative finding for the fire-sale screen. The lead inventor, Kuo-Cheng Ching, is still filing TSMC applications as late as 2019 and issuing TSMC patents into 2019 — a ten-year-plus tenure, which is the opposite of the "inventors bail out right after filing" tell. All three inventors assigned to TSMC (not to an individual or a holding entity) on a single instrument, and no inventor appears as an assignor to any third party in the record.

Note on inventor identity: the name "Chun-Yao Chen" is common, and I found a separate TSMC inventor, "Guan-Lin Chen," on reel 054920/0730 — these are different people. I did not find a record requiring them to be conflated, and I am not doing so.

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Original assignee

Taiwan Semiconductor Manufacturing Company, Ltd. (TSMC)

• No. 8, Li-Hsin Rd. 6, Hsinchu Science Park, Hsinchu 300-78, Taiwan, R.O.C. (address as recited verbatim in TSMC assignment instruments of record)
• Status: Operating. World's largest semiconductor foundry; publicly traded (TWSE: 2330; NYSE: TSM; SEC CIK 0001046179).
• Primary line of business: pure-play semiconductor foundry — contract wafer fabrication for fabless and IDM customers. Not a licensing entity.
• Did TSMC ship a product embodying the claims? The patent is a process/structural enabler for TSMC's own foundry offerings, not a discrete product. The specification describes a MIM capacitor integrated into a system-on-chip (SoC) flow that co-integrates logic (region 102), embedded DRAM (region 104), and a high-density decoupling MIM (region 106) at 90 nm / 65 nm / 40 nm and beyond. TSMC's embedded-DRAM and mixed-signal SoC platforms are the commercial embodiments. So the honest answer is: yes, in the sense that the claimed structure is a manufacturable architecture shipped in TSMC customer silicon; no, in the sense that it is not sold as a standalone part. This is a captive, portfolio-strengthening patent, not a revenue-generating asset.
• Current status: Operating, no bankruptcy, no restructuring. TSMC has never filed Chapter 7/11 and has no history of patent fire-sales.

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Assignment timeline

Preliminary — what I could and could not retrieve. The Assignment Center / legacy assignment mirror is searchable by patent number, but the indexed web content I could reach did not render the cover sheet for US 8,242,551 itself. What I do have is the Google Patents legal-events block (from the authoritative patent text supplied), which records exactly one reassignment event and gives its title, assignors, and date but not its reel/frame. I am therefore reporting the event without a fabricated reel/frame.

• 2009-03-04 (executed; same date as filing) / recorded 2009-03-04 — Reel/frame not captured in this session (UNRETRIEVED — see caveat below)
  • Conveyance: Assignment — "ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS)"
  • Assignor: CHEN, CHUN-YAO; CHING, KUO-CHENG; TU, KUO-CHI (three individual inventors, joint)
  • Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
  • Correspondent: not captured in this session. For context on TSMC's recording practice during this era, TSMC U.S. assignment recordings are filed through outside counsel rather than in-house — in the records I did retrieve, TSMC's correspondent of record is either McDermott Will & Emery (Lynn Cruz; lcruz@mwe.com, ipdocketmwe@mwe.com; stamped on reel 047428/0017, recorded 2018-11-06) or Haynes and Boone (Janie Martinez-Holm; ipdocketing@haynesboone.com, Dallas TX; stamped on reel 054920/0730, recorded 2021-01-14). I flag both because they are the plausible correspondent families for this era of TSMC filings, but I emphasize: these two reels cover different applications, not US 8,242,551, and I cannot attribute either firm to this patent's record. Doing so would be speculation.
  • Context: routine inventor-to-employer assignment at filing (new-hire/employment obligation conveyance), not an acquisition, fire-sale, reorg, or securitization.

No further recorded assignments. The Google Patents legal-events block for US 8,242,551 contains no post-issuance assignment, merger, change-of-name, security agreement, license, or release. The only subsequent entries are prosecution/administrative: 2009-09-24 priority to CN 200910173954.1; 2010-09-09 pre-grant publication; 2012-07-23 priority to divisional US 13/555,831; 2012-08-14 grant; and the 2029-07-31 adjusted-expiration status line. There is no event moving title out of TSMC.

Related family member (for completeness, not a link in this patent's chain): US 13/555,831, filed 2012-07-23 as a division of 12/397,948, granted as US 8,987,086 B2 ("MIM capacitor with lower electrode extending through a conductive layer to an STI"). Also TSMC, also with no downstream assignment.

Caveat on the missing reel/frame (stated plainly)

I could not verify the reel/frame number, the recording date as docketed, or the correspondent of record for the 2009 assignment from a primary source in this session. I did not guess. The single assignment event above is corroborated by the legal-events block in the authoritative patent text, which explicitly lists the assignee and all three assignor names. The reel/frame and correspondent should be pulled directly at USPTO Assignment Center (search "8242551" or "12/397,948") before this timeline is relied on in diligence. Any reel/frame I supplied would be fabricated, and I will not do that.

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Timeline diagram

timeline
    title Ownership of US 8242551
    2009 : Filed by TSMC
         : Inventors assign to TSMC
    2012 : Patent issued to TSMC
    2012 : Divisional filed
    2015 : Divisional issues as US 8987086
    2029 : Adjusted expiration

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NPE / troll-pattern signals

Corroborating contextual check (SEC): TSMC is an SEC registrant (CIK 0001046179). I did not obtain and did not review TSMC's 10-K/20-F or Form 8-K disclosures on this patent, and I make no claim that they mention it — a single MIM capacitor patent would not be a reportable disposition. The only TSMC SEC item my search surfaced was an unrelated Form 4 insider-trading index entry (Chin Yung-Pei, 2026-05-11), which confirms the CIK but is not on point. SEC-verified privateering check: unperformed.

RPX / Unified cross-reference: I did not reach the RPX Insurance or Unified Patents asserter directories in this session. Given that the chain is a single inventor→TSMC assignment with no downstream transfer, neither directory would have anything to match on — the directories index asserters, and TSMC's assignment of record is an employment conveyance by an operating foundry.

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Verdict

Insufficient data (only the original assignment) — with the substantive read that this is a captive operating-company portfolio patent, not an NPE asset.

Justification: the entire recorded chain is a single instrument — the 2009-03-04 assignment of "ASSIGNMENT OF ASSIGNORS' INTEREST" from CHEN, CHUN-YAO; CHING, KUO-CHENG; TU, KUO-CHI to Taiwan Semiconductor Manufacturing Company, Ltd., matching the 2009-03-04 filing date, with no recorded post-issuance transfer of any kind (Google Patents legal events for US 8,242,551). Signals 1, 2, 4, 5, 6, 7, and 8 are all not present on the face of the record; signal 3 cannot be evaluated because the chain has only one link and its correspondent was not retrievable. Two facts independently cut against the fire-sale hypothesis: (a) the lead inventor, Kuo-Cheng Ching, was still assigning inventions to TSMC as late as 2019 (reel 054920/0730, executed 2019-12-13), so no mass inventor departure followed filing; and (b) TSMC is a going-concern foundry with no bankruptcy, no licensing subsidiary in the chain, and — per the prior sections — no litigation or PTAB activity involving this patent whatsoever.

Verification link: USPTO Assignment Center — search by patent number 8242551 or application 12/397,948. (The legacy mirror is at assignment.uspto.gov/patent.) Please pull the cover sheet there to capture the reel/frame and correspondent, which this report explicitly leaves as UNRETRIEVED.

Watch-list suggestions: If a TSMC patent of this vintage ever moves, expect it to move via a corporate transaction, not a litigation-driven assignment — check the sibling US 8,987,086 (divisional) and the Chinese family member CN101826560B as the likelier vehicles, since a purchaser would want the fuller specification family rather than the '551 alone. A change in the Assignment Center "current assignee" field for any of the three, with TSMC as assignor, would be the first sign of a portfolio divestiture and should be treated as a lead worth immediate follow-up.

Prepared 2026-09-30. No recorded assignment out of TSMC exists for US 8,242,551 in the sources reviewed. All negative findings are statements of absence in the record, not affirmative certifications that no unrecorded or unindexed transfer exists. Nothing here is legal advice.

I'll verify the patent record and the cited references against live sources.

Let me verify the remaining high-relevance citations.

Prior-Art Analysis — U.S. Patent No. 8,242,551 B2

"Metal-insulator-metal structure for system-on-chip technology" · TSMC · App. 12/397,948 · Filed 2009-03-04 · Granted 2012-08-14

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0. Verification of the target patent

Search-capacity caveat, stated up front: my USPTO-database access in this session was through the Google Patents mirror of the USPTO record (Google Patents + Espacenet + FreePatentsOnline), not a direct PatentCenter / Patent Public Search query on the number itself. Every identifier above is reproduced literally from that record. Results for near-neighbors ("8,242,552", "8,242,255", "′824 patent") were discarded and are not attributed to this patent.

Governing law — pre-AIA § 102. Because the application was filed 2009-03-04 (before 2013-03-16), the pre-AIA version of 35 U.S.C. § 102/§ 103 controls. That gives three distinct prior-art channels against the 2009-03-04 effective date:

This distinction matters a lot here, because several of the examiner-cited references were published after the '551 filing date and are therefore only § 102(e) art (§ 102(a)/(b) unavailable) — and several of those § 102(e) items are TSMC's own applications, which are disqualified as obviousness art under pre-AIA § 103(c).

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1. Scope of "the citations for 8,242,551"

The record shows two citation sets, which is worth flagging because they are frequently conflated:

1. "Patent Citations (25)" — the examination-era US references cited on the face of the patent. This is the set the task asks about, and it is the set analyzed below. (Note: the same page's condensed "Citations (24)" table omits one entry — the two tables disagree in count, and I report the 25-item version as controlling.)
2. "Family Cites Families (11)" — citations appearing in family members (the CN counterpart / prosecution of relatives), which are generally not of-record art in the '551 file. These are listed in § 3 below for completeness only.

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2. The 25 examiner-cited references — master table

Ranks 1–6 are the references with genuine technical overlap with the claimed structure (see § 4 for the deep dive). "§ 102 status" uses the channels above. "Anticipation?" answers the specific question asked: does this single reference map onto a claim of the '551 patent?

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3. "Family Cites Families (11)" — for completeness, not on-face art

These appear in the family-citation table, not the '551 examination record. Several are § 102(b) art by date and are of interest chiefly as § 103 material:

• US 6,238,967 B1 — Motorola, Method of forming embedded DRAM structure — grant 2001-05-29; filed 1999-04-12 (§ 102(b))
• US 6,239,010 B1 — United Microelectronics Corp., Method for manually manufacturing capacitor — grant 2001-05-29; filed 1999-07-02 (§ 102(b))
• KR 100305680 B1 — capacitor fabrication — 1999-08-26 (§ 102(b) if printed publication date established)
• US 2002/0125537 A1 — Ting-Wah Wong, Integrated radio frequency circuits — pub. 2002-09-12; filed 2000-05-30 (§ 102(b))
• KR 100531419 B1 — Hynix — 2001-06-12 (§ 102(b))
• KR 100548999 B1 — Samsung — 2003-10-28 (§ 102(b))
• US 7,180,116 B2 — TSMC, Self-aligned metal electrode to eliminate native oxide effect for MIS capacitor — grant 2007-02-20; filed 2004-06-04 (§ 102(b))
• FR 2884646 B1 — STMicroelectronics SA, Method for manufacturing an IC comprising a three-dimensional capacitor — 2007-09-14; filed 2005-04-19 (§ 102(b))
• JP 4848137 B2 — Renesas, Semiconductor device and manufacturing method thereof — 2011-12-28; filed 2005-05-13 (§ 102(e)-style only in US terms; verify)
• US 7,776,684 B2 — Intel, Increasing the surface area of a memory cell capacitor — grant 2010-08-17; filed 2007-03-30 (§ 102(e) as of 2007-03-30)

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4. Deep dive — the six references that actually matter

I full-text-verified entries 1, 9, 12 and 15 against live sources in this session; entries 11 and 18 I report from the authoritative front-page citation table only and have not element-by-element verified their disclosures. Treat that as a real limitation.

4.1 US 7,105,405 B2 — Schuegraf (Micron) — § 102(b)

• URL: https://patents.google.com/patent/US7105405 ; Espacenet biblio: https://worldwide.espacenet.com/publicationDetails/biblio?CC=US&NR=[7105405B2](/patent/7105405B2)
• Dates: granted 2006-09-12; filed 2001-01-26; priority chain back to 1995-12-22 (US 19950576952). Sibling continuation-CIP: US 6,197,634 B1 (granted 2001-03-06).
• Disclosure (verified): "Thin film metal-insulator-metal capacitors having enhanced surface area are formed by substituting metal for silicon in a preformed electrode geometry." Rugged/HSG-textured polysilicon electrode → metal substitution (WF₆) → high-k dielectric (Ta₂O₅, BaTiO₃, SrTiO₃, BST, PZT) → metal top layer (Ti). Claim 1 is a process claim (forming silicon electrode structure; making it rugged; substituting metal). Discusses FIN and CROWN three-dimensional metal electrodes, and expressly frames the invention as a response to the Kaga IEDM '94 MIM-CROWN cell.
• § 102 assessment: No anticipation of claims 1, 13, or 19. This reference is about surface morphology (texturing/ruggedization for area gain), not about depth of the electrode through a conductive layer to an isolation structure. It contains no isolation structure, no shallow-trench feature, no bottom electrode penetrating a polysilicon layer. Its value is § 103: it supplies (a) crown-MIM architecture, (b) high-k dielectric sandwiched between metal electrodes, (c) the express motivation to increase electrode surface area without increasing lateral dimensions — i.e., the exact rationale the '551 patent advances for trenching deeper. As a same-field, same-problem reference it is a strong obviousness exhibit. Claim 2 (high-k dielectric) is disclosed, but claim 2 depends from claim 1, so it cannot be anticipated absent all of claim 1's elements.

4.2 US 7,074,669 B2 — Iijima & Sakuma (Elpida) — § 102(b)

• URL: https://patents.google.com/patent/US7074669
• Dates: granted 2006-07-11; filed 2002-05-22 (per USPTO page) — note the printed matter shows "Filed: May 22, 2003," so the filing date as printed (2003-05-22) differs from the citation table's 2002-05-28. Both are § 102(b) regardless; flagging the discrepancy literally rather than reconciling it.
• Disclosure (verified): A semiconductor IC device with a plurality of crown-structure lower electrodes, a dielectric film, and an upper electrode; at least one electrode is a laminate of conductive films; the outermost film on the dielectric side is ruthenium; the underlying film has higher selective growth than the insulating film (desirably tantalum oxide). Expressly frames the problem as reduced memory-cell area vs. required capacitance, and the crown structure as the way to recover electrode area.
• § 102 assessment: No anticipation of claims 1/13/19 — no isolation structure, no conductive-layer penetration. But it is the best single-reference statement of the "crown MIM capacitor" element common to all three independent claims, and of the "capacitance ∝ electrode area" motivation. § 103 art, high relevance. It also supplies the "dielectric disposed between the top electrode and the bottom electrode" element verbatim in substance.

4.3 US 2004/0201053 A1 — TSMC — § 102(b) (strongest architectural reference)

• URL: https://patents.google.com/patent/US20040201053 ; sibling grants US 6,720,232 and US 7,115,935 (https://www.freepatentsonline.com/[7115935](/patent/7115935).html)
• Dates: published 2004-10-14; filed 2003-04-10.
• Disclosure (verified): Method of fabricating a MIM capacitor in an embedded DRAM process. Contact plugs through an insulating layer in a logic area and a memory area; a silicon carbide layer over the plugs; a low-k dielectric layer; a stop layer; a first opening through to the node contact plug; a conformal first metal layer → bottom electrode (recessed via sacrificial layer); removal of sacrificial/stop layers; capacitor dielectric over the bottom electrode; second + third metal layers → top electrode; second openings etched through the low-k and SiC layers to the contact plugs, filled with a fourth metal to complete contacts in logic and memory areas. Second embodiment: paired "twisted trenches" in a self-aligned copper process.
• § 102 assessment: This is the closest structural analog to issued claim 6 (two-region device; first ILD; contact feature; second ILD; first/second trenches; bottom metal layer partially filling the trenches; dielectric; top metal layer) and to the two-region/SiC-etch-stop element of claim 7. It is not an anticipation of claim 6, because claim 6 depends from claim 1 and therefore requires the claim-1 bottom electrode to extend completely through the conductive layer and contact the isolation structure — here the electrode instead lands on a contact plug/node contact, the opposite topology. Note also that the cap is a recessed/damascene structure rather than a raised crown. High-value § 103 art; and because it is TSMC's own earlier published application, it is available as § 102(b) printed publication art notwithstanding common ownership (the § 103(c) carve-out applies only to § 102(e)/(f)/(g) art).

4.4 US 7,122,424 B2 — TSMC — § 102(b)

• URL: https://patents.google.com/patent/US7122424 ; FreePatentsOnline: https://www.freepatentsonline.com/[7122424](/patent/7122424).html
• Dates: granted 2006-10-17; filed 2004-02-26 (published as US 2005/0191820 A1).
• Disclosure (verified): Process for an array of MIM crown storage capacitors for DRAM, with improved bottom electrodes recessed in insulator openings. Sequence: node insulating layer → node openings → plug contacts (doped poly/tungsten) → insulating layer → array of crown-capacitor openings aligned over the plug contacts → conformal first conducting layer → sacrificial layer (polymer/photoresist, later CVD in embodiment 2) → two-step CMP + etch-back planarization → etch the first conducting layer to expose sidewall portions and recess the bottom electrodes → remove sacrificial layer → thin conformal capacitor dielectric → second conducting layer polished back to form self-aligned top electrodes (damascene-compatible). Figures 1 and 2 are expressly labeled prior art.
• § 102 assessment: No anticipation of claims 1/13/19 — the electrodes are recessed in openings over node contacts in an insulating layer, not extended through a conductive/poly layer to an isolation structure. But this reference is materially exposed on claim 6's "bottom metal layer partially filling trenches, portions removed outside the trenches" and "self-aligned top electrode" concepts, and on the general crown-MIM-in-ILD architecture. High-value § 103 art. Also note Fig. 2's prior-art recessed-top-electrode structure is an express admission of a self-aligned crown MIM in a trench.

4.5 US 6,875,655 B2 — TSMC — § 102(b) (crown-surface robustness)

• Dates: granted 2005-04-05; filed 2003-03-17. Not full-text verified in this session — I report only the title/date/subject matter from the authoritative citation table.
• § 102 assessment: On its title and field ("protected outside crown surface for more robust structures"), it is same-field crown-capacitor art and a plausible § 103 complement to references 4.2/4.4 (crown shape) and to claim 5/9's corner-profile reliability rationale (the '551 spec ties corner rounding to TDDB improvement and robustness). I cannot responsibly assert an element-by-element § 102 mapping without the full text.

4.6 US 7,276,751 B2 — IBM — § 102(b) (trench MIM + MOL contacts)

• Dates: granted 2007-10-02; filed 2005-09-09. Not full-text verified in this session.
• Disclosure per title: trench MIM capacitors integrated with middle-of-line metal contacts.
• § 102 assessment: Same trench-MIM-in-ILD, contact-coupled family as 4.3. Relevant § 103 art on claim 6 and on the general "put the MIM capacitor in a trench in the interconnect stack" concept. Again, the trench bottoms on contacts, not on an isolation structure, so no § 102 hit on claim 1.

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5. The § 102 question, answered directly

No reference cited on the face of U.S. 8,242,551 anticipates independent claim 1, 13, or 19. Every one of those claims requires a combination whose distinguishing element is the same:

the first bottom electrode extending completely through the conductive layer and physically contacting a portion of the isolation structure (claim 1); the first bottom electrode extends through the conductive layer and at least to a top surface of the isolation structure, sitting a smaller distance from the substrate than the memory-cell bottom electrode (claim 13); and the staged "at least to a top surface of the conductive layer" + "through the conductive layer … at least to a top surface of the isolation structure" (claim 19), with claim 20 adding penetration into a portion of the isolation structure.

None of the 25 cited references discloses that topology. The cited crown-MIM references (4.1, 4.2, 4.4, 4.5) all terminate their bottom electrodes on a node contact or in an insulating layer; the cited trench-capacitor references (4.3, 4.6, and US 2003/0213989) likewise land on contact plugs, or (Delpech) form the trench in the substrate itself rather than through a conductive layer to an STI.

Consequences for claim mapping:

• Dependent claims are not independently anticipatable. Because claims 2–12 depend from claim 1, and 14–18 and 20 depend from 13/16/19, each dependent claim incorporates every limitation of its base claim. A reference that discloses only, e.g., the high-k dielectric (claim 2) or the silicide (claim 3) cannot anticipate that dependent claim unless it also discloses all of claim 1. I flag this because the "which claim does it anticipate" framing invites the error of treating dependent-claim subject matter as if it stood alone.
• The realistic § 102 targets are narrow. If any claim of the '551 patent is vulnerable to single-reference § 102, it will be a dependent claim whose added limitation is old in the art (high-k dielectric; TiN bottom/top electrodes; STI as the isolation structure) — and only if a reference independently discloses the full claim-1 combination. I did not find such a reference among the 25.
• The real exposure is § 103, not § 102. The cited art collectively supplies: crown-shaped MIM capacitor (4.1, 4.2, 4.4), high-k dielectric between metal electrodes (4.1, 4.2), MIM capacitor in an ILD trench coupled to a contact in a logic/memory two-region SoC (4.3), self-aligned recessed crown bottom electrodes with a conformal dielectric (4.4), elevated capacitor structures for area gain (US 2005/0258512), trench MIM with MOL contacts (4.6), and trench capacitors formed into a substrate/isolation region (US 2003/0213989). The obviousness case would be: "extend the trench/crown bottom electrode down through the underlying polysilicon to the STI to gain electrode surface area without increasing footprint" — a motivation the art explicitly supplies. That is a § 103 argument, and the patent's answer is the inventive insight that the conductive layer (poly/silicide) can serve as the common node tying multiple crown bottom electrodes together in parallel (claims 4/6) while the STI concurrently isolates the capacitor from substrate noise — a function the cited art does not appear to combine.
• Common-ownership nuance to preserve. Several cited items are TSMC's own earlier filings (US 6,329,234; 6,472,721; 6,656,785; 6,849,387; 6,875,655; 7,122,424; 7,163,853; US 2004/0201053; US 2005/0258512; US 2007/0200162). Where such a reference is § 102(e)/(f)/(g) art (i.e., an unpublished-at-the-time US application), pre-AIA § 103(c) disqualifies it as obviousness art if commonly owned when the invention was made. Where it is a published patent or printed publication (§ 102(a)/(b)), no such disqualification applies. This is a live distinction for US 2009/0140386, US 2010/0013047, US 2010/0155801 and US 2010/0237465, which are § 102(e)-only references.

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6. References with no § 102 applicability

The following should be affirmatively excluded from any § 102 chart, and I say so rather than padding them in:

• US 2009/0140386 A1 (NEC), US 2010/0013047 A1 (Thies), US 2010/0155801 A1 (Doyle), US 2010/0237465 A1 (X-Fab) — each published after the 2009-03-04 effective filing date, so § 102(a) and § 102(b) are unavailable. They can only be reached through § 102(e) (and thus are subject to § 103(c)), and § 102(e) requires their US filing date to precede 2009-03-04 — true for 2009/0140386 (filed 2007-11-29), 2010/0013047 (filed 2008-07-16) and 2010/0155801 (filed 2008-12-22); unverified for 2010/0237465, which is a foreign-portfolio publication and whose actual US filing date must be confirmed before any § 102(e) reliance.
• US 6,677,250 B2 (Micron CVD apparatus) — directed to deposition hardware; no capacitor-topology disclosure relevant to any claim of the '551 patent.
• US 7,163,853 B2 and US 2007/0200162 A1 — address capacitor/metal-gate integration and dielectric-constant reduction respectively; no pertinence to the claimed electrode-extension topology.

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7. What the '551 patent's own record contributes (context for the mapping)

Two further points from the authoritative text bear on any invalidity analysis and should be carried forward:

1. The granted claim 1 was narrowed relative to the published claim 1. Pre-grant publication US 2010/0224925 A1 presented claim 1 ending at "extending at least to a top surface of the conductive layer." The granted claim 1 instead requires "extending completely through the conductive layer and physically contacting a portion of the isolation structure," and the published concept was re-cast as new independent claim 19. Any § 102 analysis must therefore be run against the granted text, not the publication — and this prosecution history is itself a roadmap to the art the applicant was distinguishing.
2. Claim 13 contains an apparent typographical defect — "a dielectric disposed between the first top electrode and the first top electrode," and a final "wherein" clause referring to "the conductive layer" without antecedent basis in claim 13. I report this literally, as instructed; it is a § 112 exposure note, not a prior-art point, and the USPTO certificate (not the mirror) controls.

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8. Limitations of this analysis — please read

• Negative findings are weaker than positive ones. My searches returned no source contradicting the citation table, but I did not obtain full text for 19 of the 25 references. For those, the dates, titles and assignees above are reproduced from the patent's own front-page citation table, which is the authoritative record I was given; the substantive § 102 characterizations are based on the titles/subject matter and are labeled as such. The references I did verify full-text are US 7,105,405, US 7,074,669, US 7,122,424 and US 2004/0201053.
• No anticipation conclusion should be relied on without an element-by-element chart. The correct next step is a claim chart mapping each of claims 1, 13, 19 (and the dependents) limitation-by-limitation against the six priority references, plus a full-text pull of US 6,875,655 and US 7,276,751.
• Sibling and family members matter. The divisional US 8,987,086 B2 ("MIM capacitor with lower electrode extending through a conductive layer to an STI") shares this specification and claims overlapping subject matter; the Chinese counterpart CN 101826560 B is the same family. Prior art analyzed against the '551 generally applies to the divisional and the CN member, but confirm the CN claim scope separately (different claim sets are common in CN practice).
• Primary-source next steps: USPTO Patent Center and Patent Public Search for the '551 and the '086 file histories (to capture any art cited in the divisional), plus Espacenet INPADOC for the CN/FR/JP members listed in the family-citation table, and a fresh classifier search (H10D1/716, H10D1/042, H10B12/033) to surface crow/trench-MIM art the examiner never saw — which is where the strongest § 103 material is likely to be.

Prepared 2026-09-30 against the authoritative patent text at https://patents.google.com/patent/US8242551/en (fetched 2026-09-24). Nothing here is legal advice.

I'll ground the combinations in the actual content of the cited references before analyzing. Let me pull the key prior-art records.

Good grounding so far. Let me pull the remaining high-value references.

Obviousness Analysis — U.S. Patent No. 8,242,551 B2

35 U.S.C. § 103 (pre-AIA), "Metal-insulator-metal structure for system-on-chip technology"
Assignee: Taiwan Semiconductor Manufacturing Company, Ltd. · App. 12/397,948 · Filed 2009-03-04 · Granted 2012-08-14

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0. Two housekeeping flags before the analysis

1. Date inconsistency in the working papers. The system date I was given is 2026-09-30; the task line in this prompt says April 26, 2026; the previously generated sections are dated both 2026-09-24 (fetch) and 2026-09-30 (preparation). §103 analysis is date-insensitive between those dates — no post-2026-04 art is at issue — but the inconsistency is noted so it is not propagated.
2. The §103 universe is fixed by the page's own citation tables. I am treating the front-page "Citations" / "Patent Citations (25)" and "Family Cites Families (11)" entries as the prior-art set. I am excluding the "Cited By (3)" entries (US 2013/0015558 A1; US 9,911,650 B2; US 2022/0115370 A1) and the "Families Citing this family" entries — all post-date the 2009-03-04 priority date and are therefore not prior art against this patent. This matters because the earlier PTAB challenges section listed US 7,275,751 and others as §103 ammunition; that list is the right shooting gallery but it is a different set from the page's citation tables (the page cites US 7,276,751, not 7,275,751 — a literal-number distinction I am preserving, not correcting).

Sources: US8242551B2, Google Patents

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1. The legal frame

Pre-AIA § 103(a) applies (filed 2009-03-04, no post-AIA effective date). The governing test is Graham v. John Deere (scope/content of prior art; differences; PHOSITA level; secondary considerations), as refined by KSR Int'l v. Teleflex, 550 U.S. 398 (2007): a combination is obvious not only where the references expressly suggest it, but where (i) the improvement is a predictable use of prior-art elements according to their established functions, (ii) the combination is a known technique applied to a known device ready for improvement, or (iii) there are "a finite number of identified, predictable solutions." Motivation may come from the nature of the problem (In re Fritch), the design incentive (MPEP 2144.01), or the applicant's own specification.

Level of ordinary skill: a B.S. in EE/Materials/Physics or equivalent, 3–5 years in semiconductor process integration, with working familiarity with MIM capacitor integration in embedded-DRAM/SoC flows. (The spec targets 90/65/40 nm nodes "and beyond.")

Critical framing point — "crown shape" is a self-defeating limitation. The specification defines its own crown structure as one that "resembles a folded structure in which a trench is lined with a first electrode and filled with an annular shaped insulating element and an inner core electrode." (Background section.) The same spec then describes its MIM capacitor as being formed by partially filling trenches with a bottom metal layer, a dielectric, and a top metal layer (blocks 412–418). Under a Phillips reading informed by that language, "crown shape" collapses into "trench/cylinder MIM capacitor" — a structure that is the explicit subject matter of US 7,276,751 (IBM, trench MIM) and US 2004/0201053 A1 (TSMC, MIM in a trench opening). A patent owner will argue "crown" requires an annular, upper-open electrode; expect that fight. Either way, the surviving novelty in issued claim 1 is not the crown — it is the vertical extent of the bottom electrode.

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2. The prior art of record, sorted by effective date and statutory basis

Examiner-cited core set (the ones the patent owner cannot escape): US 7,276,751; US 7,776,684; US 2004/0201053 A1; US 6,656,785; US 7,074,669; US 7,122,424; US 7,163,853.

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3. The actual difference over the art

Two distinct limitations carry the issued claim set, and they must be attacked separately:

Limitation (B) is the whole case. If (B) falls, every issued claim falls with it (all independents contain it; every dependent either adds it or depends on a claim containing it).

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4. Combination 1 — US 2004/0201053 A1 + US 6,656,785 + US 7,074,669 → claims 1, 2, 6, 7, 10, 11, 12, 19

The combination. Take TSMC's own embedded-DRAM MIM flow ('053: SiC etch stop over contacts → ILD → stop layer → trench to the node contact → TiN bottom electrode → high-k dielectric → TiN/W top electrode → CMP → ILD/interconnect, in both a logic area and a memory area) as the base structure; use US 6,656,785 for the SoC/crown-specific etch-and-stop-on-SiON recess flow with Ta₂O₅/BST and the explicit "logic-based embedded RAM" motivation; and use Elpida '669 for the crown-geometry lower electrode. This combination yields every element of claim 6 essentially verbatim, including the "etch stop layer over the first ILD layer in the second region … but not in the second trench" of claim 7 (the SiC/SiON layer at the bottom of the memory trench is removed in both '053 and '785).

The gap. Neither reference sinks an electrode through the gate polysilicon/silicide level to land on the STI. What claim 1 adds is the direction of area extension — down, not up.

Why a PHOSITA would close that gap. Four independent motivations, any one sufficient:

1. Applicant's own admission. The '551 specification states: "the surface area of the capacitors 120 may be increased by increasing the thickness of the ILD layer 144 … but this causes an increase of a parasitic capacitance between metal structures (interconnection structures) formed in the ILD layer 144." That paragraph is an express teaching that the conventional route (taller ILD) has a recognized, quantified penalty, which is a classic "known problem → known alternative" motivation. The claimed structure is the alternative.
2. Predictable use of a known technique for its established function. Extending an electrode in the depth direction to add capacitance area at constant footprint is the entire point of every crown/trench reference in the record (Elpida '669; TSMC '424; TSMC '053; IBM '751). Applying that known technique by one additional etch increment (through poly/silicide/STI-oxide) is precisely the KSR "predictable variation of a known device using a known technique" scenario.
3. The record supplies the etch stop. '053 and '785 already teach that an underlying layer (SiC / SiON) is used as an etch endpoint and then selectively removed. Substituting an STI oxide region as the etch stop and end-point is the same technique applied to the same kind of structure — the only change is which layer terminates the etch.
4. No new problem is solved. "Crown shape" adds nothing because the spec defines it as a lined trench. The remaining variable is etch depth, which the patent itself calls a matter of "design requirements."

Reasonable expectation of success. Dry-etch chemistries with high selectivity between polysilicon/silicide and STI oxide are routine; the '551 itself uses exactly this sequence (dry etch through silicide/poly/STI, then an isotropic wet dip). Nothing in the combination requires an unforeseeable step.

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5. Combination 2 — US 7,776,684 (Intel) + US 2004/0201053 A1 (TSMC) → the (B) limitation of claims 1, 8, 18, 19, 20

This is the most direct mapping in the record to claim 1's core limitation, because Intel '684 discloses — in an ILD/STI environment, for a capacitor, with a high-k dielectric — the sequence:

STI layer 102 → insulating layer 103 (ILD) → opening etched in a second insulating layer down to a polysilicon conducting layer 206 → polysilicon layer 206 removed, exposing portions 214 of the STI layer 202 → thin conducting layer deposited over the second insulating layer and over the exposed STI surface → high-k insulating layer (ZrO₂/HfO₂) → second conducting layer.

A first (bottom) capacitor electrode is thereby formed that passes through the level occupied by a polysilicon conductor and physically lands on the STI. That is limitation (B) in substance. Intel '684 also states the purpose in the same terms the '551 claims: "Methods and apparatuses to increase the surface area of a memory cell capacitor," with the stated benefit that capacitance area "follows a length of" the dielectric.

Why combine with '053? '053 supplies the crown/trench-in-ILD geometry and the dual-region (logic + memory) architecture; Intel '684 supplies the depth-extension to an STI landing surface technique and the high-k dielectric. Both are in the same field (capacitors in interconnect/middle-of-line dielectrics over an STI-isolated substrate), both address the same problem (capacitance density at fixed footprint), and both are §103-combinable art (Intel published 2008-10-02, before the 2009-03-04 filing).

The patent owner's best rebuttal, and why it is only partially effective. The owner will say Intel '684's polysilicon layer 206 is a dummy/replacement-metal-gate layer that is removed, whereas in the '551 the polysilicon layer 130 remains and performs a function — it electrically couples bottom electrodes 160a/160b in parallel through the silicide 132. Two responses:

• As to claim 1: claim 1 does not require any coupling function or any second bottom electrode. It requires only that the electrode extend "completely through the conductive layer and physically contact a portion of the isolation structure." Whether the conductive layer is later removed or retained is not a claim element. Intel '684 therefore reads on claim 1's depth-spatial limitation, and the combination with '053/'424 (which retain the ILD and the conductor level) supplies the rest.
• As to claim 4 (the parallel-couple feature): the rebuttal gains traction here. See §6.

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6. Combination 3 — US 7,276,751 (IBM) + US 2004/0201053 A1 / US 7,122,424 → claims 1, 3, 4, 13, 15, 17, 18, 20; and the strongest mapping for claims 13 and 15

US 7,276,751 is the most intellectually damaging reference in the record because it teaches, in one document, almost every structural and motivational premise of the patent:

Motivation to combine with the crown references: IBM '751 supplies the motivation statement the '551 needs a PHOSITA to have had. It recites the problem ("capacitance must increase while footprint shrinks"), the known solution (deeper electrode), and the motivation for a metal, not polysilicon, electrode with a silicide interface — all before 2009. It also expressly extends the concept to decoupling capacitors, which are exactly the function the '551 assigns to region 106.

The remaining gap: IBM '751's deep trench is in the substrate, not in an STI region, and it does not place a crown MIM in a BEOL/MOL trench that penetrates through a retained gate-poly layer onto an STI. That is where '053/'424 (BEOL trench MIM with TiN/high-k/TiN in ILD, in both logic and memory regions) completes the combination: crib the geometry and layer stack from '053, crib the deep-extension + differing-depth + silicide-interface teaching from '751, and the claimed device results.

Claim 13/15 specific: '053's dual logic-area/memory-area contact plugs and trenches map directly onto claim 13's "first region / second region" and onto claim 15's embedded-DRAM cell with a transistor and a contact for coupling the second bottom electrode to the doped feature (the '551's own element 142/170). Claim 13's remaining inventive hook is the relative-depth limitation — and IBM '751's "second trench has a depth larger than that of the first trench" is an explicit, squarely-on-point teaching of exactly that phenomenon (differential capacitor depth within one integrated device).

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7. Claim-by-claim mapping table

Confidence codes: H = mapped from text I retrieved and read this session; M = mapped from title/abstract/assignee and the structural family; L = mapping is a design-choice/obviousness-rationale mapping, not a specific disclosure.

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8. Where the validity case is weak (and where it is strong)

Strong for a challenger:

• Claims 6–9, 13–17 (the "integration" claims). US 2004/0201053 A1 and US 6,656,785 are both TSMC's own earlier work in the same process-integration field, and '053 in particular tracks claim 6 nearly element-for-element (contacts in logic and memory areas, SiC/stop-layer stack, opening to the node contact, TiN bottom electrode, capacitor dielectric, TiN/W top electrode, polish-back, ILD, interconnect). A §103 rejection here would likely be characterized as a predictable, same-field combination of same-assignee, same-flow references — the hardest kind to rebut.
• Claim 2 (high-k), claim 12 (STI), claim 14 (CMOS logic region), claim 15 (eDRAM contact). These are near-anticipations in substance. Claim 2 and 12 in particular add nothing beyond the record.
• Claims 19–20 are narrower-in-degree versions of claim 1 and track the published claim 1 + FIG. 2/FIG. 3 embodiments; the spec treats the depth of penetration as a design choice.

Weak for a challenger (the patent owner's counterattack):

1. Claim 4 — the parallel-coupling through the conductive layer. This is the feature that most resists the record. No reference cleanly teaches two crown bottom electrodes electrically coupled to each other through the gate-poly/silicide level (as opposed to through a strap, a landing pad, or a single pad electrode). Expect the owner to argue: (a) the record's "second electrode coupling" art (Delpech's floating electrodes; Elpida's common pad; IBM's strap) all couple at a different level; and (b) removing or repurposing the gate conductor in region 106 while retaining it in region 104 (the '551's structure) is a non-obvious process integration choice, because region 106's poly is formed "concurrently when forming the transistors" and then becomes both the coupling layer and the landing layer.
2. Claims 5 and 9 — rounded corner profile. I could not locate a rounded-corner disclosure in this record, and the earlier-generated sections correctly note the reliability claim for it (TDDB improvement). The obviousness case here rests on predictability-of-etch-result and on the well-known practice of rounding trench corners — a real but weaker ground. The owner should be expected to pair this with a secondary-considerations argument (unexpected TDDB improvement).
3. Claim 1's "completely through … and physically contacting." The two closest references both have a wrinkle: Intel '684 removes the poly layer before forming the electrode (so the electrode contacts the STI but the "conductive layer" it extended "through" is gone), and IBM '751 puts the trench in the substrate rather than in an STI over which a gate-poly layer sits. A challenger must therefore rely on combination, not anticipation, and must be prepared to argue that the presence/absence of the poly above the STI landing point is a difference without patentable significance — which is precisely the argument that claim 10 undercuts, because claim 10 requires "a portion of the bottom electrode physically contacts a portion of the conductive layer," i.e., the poly must be retained. In this respect claim 10 alone may be the patent's most defensible single claim (Bloomberg note: this is where I would expect any IPR petition to focus its § 103 rebuttal, and where I would expect the patent owner to file a contingent motion to amend).

One claim-construction landmine that must be resolved before any §103 comparison:

• Claim 11 ("the top electrode extends to at least to a top surface of the conductive layer") is directionally ambiguous — the top electrode is above the conductive layer, so "extends to at least to a top surface of the conductive layer" is either trivially satisfied or refers to the bottom of the top electrode reaching down to that level. The literal text is preserved; construing it changes whether '053 (whose top-electrode metals fill the opening all the way down to the node contact) anticipates it.
• Claim 13 contains the printed typo identified in the earlier Patent summary section ("a dielectric disposed between the first top electrode and the first top electrode") and a final "wherein" clause referring to "the conductive layer" with no antecedent basis. These are § 112, not § 103, defects — but they constrain how far a challenger can push claim 13 in an IPR, because the Board will likely give the claim its evident meaning (dielectric between the first top and first bottom electrodes) rather than invalidate on the typo.

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9. Secondary considerations — assessment

The record contains no evidence of nexus-bearing objective indicia for the issued claims:

• No unexpected results — capacitance scales with electrode area, and the spec presents depth-extension as a design-requirement tradeoff, not a discovery.
• No criticality — all numeric ranges ("about 500 to about 1500 Å" etch stop; "about 5000 to about 12000 Å" ILD 144; "about 100 to about 500 Å" metal; "about 50 to about 400 Å" dielectric) are routine process windows typical of the 40–90 nm nodes the spec targets.
• No long-felt need / failure of others evidenced in the record: TSMC, IBM, Intel, Elpida, Micron, Chartered, Infineon/Thies, X-Fab, STMicroelectronics, and Renesas all filed in this exact space in 1997–2009, which cuts against a "failure of others" narrative.
• No copying / industry praise in the record. The three "Cited By" items are later TSMC and Elpida filings — evidence of a crowded field, not of praise.
• Counterweight the owner can run: commercial success of TSMC SoC/embedded-DRAM products incorporating the structure, and the adoption of a divisional (US 8,987,086 B2, "MIM capacitor with lower electrode extending through a conductive layer to an STI") — but the divisional's very title tracks the same limitation, and a divisional grant is not itself evidence of non-obviousness.

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10. Bottom line

1. Claims 6, 7, 14, and 15 are the most vulnerable — US 2004/0201053 A1 in view of US 6,656,785 maps them nearly element-for-element, with an express SoC/logic-based-embedded-DRAM motivation in '785.
2. Claims 1, 8, 19, and 20 turn on one limitation: an electrode that runs down through a retained polysilicon/silicide layer and lands on (or in) the STI. US 7,776,684 supplies that depth-extension teaching against an STI, with high-k and STI expressly named; US 7,276,751 supplies the metal/silicide/k>4 electrode in a trench and the differential trench depth teaching that maps claim 13. The combination is motivated by (i) the applicant's own admission that the conventional thicker-ILD route increases interconnect parasitic capacitance and (ii) the record's uniform teaching that capacitance density is bought with depth.
3. Claims 4, 5, and 9 are the patent's real defensive redoubts — parallel coupling of two crown bottom electrodes through the gate conductor (claim 4), and the rounded-corner/TDDB feature (5, 9). Claim 10 ("a portion of the bottom electrode physically contacts a portion of the conductive layer") is the sleeper narrow claim that may survive any combination built on Intel '684, because Intel '684 removes the poly.
4. No anticipation case exists from this record alone. Every combination above is a §103 combination requiring an articulated motivation; nothing in the citation tables discloses the full claim 1 as-issued in a single reference. If a challenger wants to close the gap more cleanly than Intel '684 can, the priority fetch is US 2008/0213967 A1 (Su, "Trench capacitor and method," filed 2005-09-12) — a §102(b) reference in this very record that I was unable to open before hitting my search limit, and which by its title is directed at precisely the trench-depth/geometry question at issue.

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11. Caveats and required verification before reliance

• Not verified in full text this session: US 2008/0213967 A1; US 2010/0013047 A1 (Thies); US 2010/0155801 A1 (Doyle); US 2010/0237465 A1 (X-Fab); US 2003/0213989 A1 (Delpech); US 2005/0024979 A1 (Kim); US 2005/0258512 A1 (TSMC); US 7,125,424; US 6,875,655; US 6,849,387; US 7,163,853; US 7,105,405; and all KR/JP/FR family-cite references. Any §103 ground built on them must be re-checked against their actual disclosure, drawings, and claim-support paragraphs.
• §102(e)-only references (US 2009/0140386, US 2010/0013047, US 2010/0155801, US 2010/0237465) require confirmation of their U.S. filing date and any earlier U.S. provisional/§119 priority, because pre-AIA §102(e) art is measured from the U.S. filing date (plus properly claimed §119 benefit), not the foreign priority date.
• Inventorship-date risk: the analysis assumes the effective date is the 2009-03-04 filing date (Google Patents lists no provisional). If a provisional or foreign priority exists earlier or later, the §102(b) vs. §102(a)/(e) character of the 2007–2008 references shifts.
• "Crown shape" construction is outcome-determinative for claims 1 and 19. I have applied the specification's own definition (a lined trench). A contrary construction requiring an annular, upper-open electrode would push more weight onto the depth limitation and would not defeat the combinations above (Intel '684 and IBM '751 still supply the depth/electrode structure), but it would change the mapping for claims 6 and 7.
• This is an invalidity analysis, not a validity opinion, and not legal advice. It identifies where a PHOSITA would have had reason to combine specific references of record; it does not account for secondary considerations evidence that may exist outside this record, and it does not address the presumption of validity under 35 U.S.C. § 282 or the clear-and-convincing standard that applies in litigation.