Invalidity dossier
US 8785286
Techniques for FinFET doping
Current assignee: Taiwan Semiconductor Manufacturing Co TSMC Ltd
Added 9/24/2026, 3:01:06 PM
Active provider: DeepSeek · deepseek-flash
Patent summary
Title, assignee, inventors, filing/issue dates, abstract, and a plain-language overview of the claims.
I'll search for litigation and docket information on this specific patent before summarizing.
Let me run additional targeted searches to check for litigation or PTAB proceedings involving this specific patent.
Search results note (docket check first)
I ran targeted searches for US 8,785,286 against Federal Circuit 2026 dockets and PTAB/litigation sources. I found no CAFC 2026 docket, no PTAB proceeding (IPR/PGR), and no district-court case naming US 8,785,286. Two important caveats:
- A recurring hit for a "'286 patent" is US 7,885,286 (NetSocket), involved in Cisco Systems, Inc. v. NetSocket, Inc., IPR2024‑00090. That is a different patent number (7,885,286, networking) and is not US 8,785,286. I flag this because it is the most likely source of a "8985286/885286" mix‑up.
- I could not query USPTO PatentCenter / PACER / CAFC docket systems directly from this session — only web search snippets. So my "no litigation found" statement reflects search coverage, not an authoritative docket clearance. Treat it as "no evidence found," not a certified negative.
Everything below is grounded in the authoritative full text of US 8,785,286 B2 (Google Patents, https://patents.google.com/patent/US8785286/en).
Bibliographic data — US 8,785,286 B2
| Field | Value |
|---|---|
| Title | Techniques for FinFET doping |
| Patent number | US 8,785,286 B2 |
| Application number | 12/702,803 |
| Filing date | 2010‑02‑09 |
| Priority date | 2010‑02‑09 (same day; no earlier priority claimed) |
| Issue (grant) date | 2014‑07‑22 |
| Pre‑grant publication | US 2011/0195555 A1, published 2011‑08‑11 |
| Inventors | Chun Hsiung Tsai; Chien‑Tai Chan; Mao‑Rong Yeh; Da‑Wen Lin |
| Assignee | Taiwan Semiconductor Manufacturing Company, Ltd. (TSMC) — original and current |
| Assignment recorded | 2010‑04‑27, Reel/Frame 024297/0211, effective 2010‑02‑11 |
| Claims | 18 total; independent claims 1, 11, 16 |
| Legal status | Active; adjusted expiration 2032‑07‑08 |
| Maintenance fees | Paid — 4th year (2018‑01‑11), 8th year (2022‑01‑05); reminder mailed 2026‑03‑09 |
| Related family | Divisional US 13/918,682 → US 8,703,593 B2 ("Techniques for FinFET doping"), filed 2013‑06‑14, now Expired‑Fee Related |
| CPC classifications | H10D30/0241 (FinFET vertical‑sidewall doping, tilted/multi‑angled implants); H10P30/214 (recoil‑implantation); H10P30/202, H10P30/22, H10P30/222; H10P32/14, H10P32/1408 |
Verbatim abstract: "A method of forming an integrated circuit includes providing a semiconductor wafer including a semiconductor fin dispatched on a surface of the semiconductor wafer; forming a dopant‑rich layer having an impurity on a top surface and sidewalls of the semiconductor fin, wherein the impurity is of n‑type or p‑type; performing a knock‑on implantation to drive the impurity into the semiconductor fin; and removing the dopant‑rich layer."
(Note: "dispatched" appears literally throughout the specification and claims; it is almost certainly a drafting error for "disposed." Per my operating rules I am quoting it as written and not auto‑correcting it.)
Technical context (specification)
The patent addresses a known problem in FinFET fabrication: forming lightly‑doped source/drain (LDD) regions by tilted ion implantation. When fins are closely spaced and one fin is masked by photoresist, the tall resist casts a shadow that blocks tilted ions from reaching the lower sidewalls of the adjacent fin. Reducing the tilt angle removes the shadow but makes the LDD region too shallow. The alternative — depositing boron‑silicate glass (BSG) or phospho‑silicate glass (PSG) and annealing to drive dopants in — requires anneal temperatures above ~500 °C, which photoresist cannot survive, making that route incompatible with resist masking.
The disclosed solution: (1) deposit a dopant‑rich layer (near‑pure B/In for p‑type; P/As for n‑type) on the top surface and sidewalls of the fin using plasma ion assisted deposition (PIAD) with a continuous or pulsed RF source at 50–1000 W and a very low or zero DC bias (0–1.5 kV) to avoid amorphization; then (2) perform a knock‑on implantation with non‑doping ions (carbon, germanium, argon, nitrogen) at a tilt angle α greater than 0° and less than ~45°, sized to avoid resist shadowing; then (3) strip the dopant‑rich layer (e.g., wet dip) and anneal (900–1100 °C, MSA or RTA). The patent reports that LDD depth is insensitive to knock‑on tilt angle, so a small, shadow‑free angle still yields adequate junction depth. An alternative embodiment omits the knock‑on implant and instead diffuses dopants in by a long, high‑temperature anneal (1–50 s, >900 °C), optionally using a nitride/oxynitride hard mask instead of resist.
Independent claims — plain language
Claim 1 (method of forming an integrated circuit) requires four steps:
- Provide a semiconductor wafer having a semiconductor fin on its surface.
- Form a dopant‑rich layer containing an impurity on the top surface and sidewalls of the fin, where the dopant‑rich layer is a substantially pure layer of substantially pure n‑type or p‑type impurity.
- Perform a knock‑on implantation to drive the impurity into the fin, where the knock‑on implantation uses carbon, germanium, argon, or nitrogen.
- Remove the dopant‑rich layer substantially completely.
Key limitation: the dopant layer must be a substantially pure impurity layer, and the knock‑on species is limited to that four‑element Markush group.
Claim 11 (method of forming an integrated circuit) is a second independent claim with the same general skeleton — provide wafer/fin; form a dopant‑rich layer containing an n‑type or p‑type impurity on the top surface and sidewalls; knock‑on implant using carbon, germanium, argon, or nitrogen; remove the dopant‑rich layer substantially completely. Its distinguishing requirement is functional/purpose language: the knock‑on implantation forms a lightly‑doped source/drain (LDD) region of a FinFET in the fin. Notably, claim 11 does not recite the "substantially pure" requirement in its body (that appears only in dependent claim 12).
Claim 16 (method of forming an integrated circuit) is the third independent claim and is the broadest in substance, tracking claim 11's structure — provide wafer/fin; form a dopant‑rich layer with an n‑ or p‑type impurity on the top surface and sidewalls; knock‑on implant using carbon, germanium, argon, or nitrogen; remove the dopant‑rich layer substantially completely — but without either the "substantially pure" limitation (claim 1) or the "forms an LDD region" limitation (claim 11). (The claim text contains the literal typo "foaming a dopant‑rich layer"; again quoted as‑is and not corrected.)
Dependent claims (brief)
- Claim 2 — dopant‑rich layer substantially free of elements other than the n/p impurity.
- Claim 3 — knock‑on implantation is a tilt implantation.
- Claim 4 — before forming the dopant‑rich layer, form a gate dielectric and gate electrode on the fin.
- Claim 5 — the knock‑on implantation forms an LDD region of a FinFET.
- Claim 6 — before deposition, form a photoresist covering part of the wafer (leaving the target fin exposed); remove the resist after knock‑on.
- Claim 7 — the dopant‑rich layer is formed by plasma ion assisted deposition (PIAD).
- Claim 8 — PIAD uses a DC bias below about 1.5 kV.
- Claim 9 — PIAD uses no DC bias voltage.
- Claim 10 — after removal, the entirety of the dopant‑rich layer is removed.
- Claims 12–15 — mirror claims 2, 4, 6, 7 for claim 11 (substantially pure dopant; gate stack; photoresist masking; PIAD).
- Claims 17–18 — dopant‑rich layer is a substantially pure n/p impurity layer with substantially no other elements; PIAD.
Uncertainty / limitations of this summary
- Docket confirmation is incomplete. My no‑litigation finding is based on web search only; I did not access PatentCenter, PACER, or the CAFC docket API. A district‑court or ITC action not surfaced by search could exist.
- The office‑action/prosecution history is not in the provided text. I cannot say which prior art (e.g., US 2007/0084564 to Varian, "Conformal doping apparatus and method," or US 8,071,451 to Axcelis) drove the "carbon, germanium, argon, or nitrogen" and "substantially pure" limitations into the independent claims — though those references' presence on the face of the patent makes them the likely candidates.
- Face‑of‑patent "Cited By / Families Citing" lists reflect Google Patents' data and include both examiner‑cited and third‑party citations; the "Active, expires 2032‑07‑08" status and the 2014/2018/2022 dates are legal‑status assumptions per the source, not legal conclusions.
Generated 9/30/2026, 4:42:00 AM
Cases on file (0)
Specific litigation cases in our database that name US patent 8785286. The free-form analysis below may also discuss cases beyond this list.
No cases on file mention this patent. Upload a CSV or add a case manually in Admin → Manage litigation cases.
Litigation summary
Past and pending lawsuits — plaintiffs, defendants, jurisdictions, outcomes, and notable rulings.
I'll search for litigation involving US 8,785,286 across patent litigation sources.
Initial results are not on point. Let me search litigation-specific databases directly.
Let me try more targeted litigation databases and specific case-list searches.
Litigation Search Results: US Patent No. 8,785,286
Bottom line
I found no known litigation involving U.S. Patent No. 8,785,286 (TSMC's "Techniques for FinFET doping," filed 2010-02-09, granted 2014-07-22, currently active with an adjusted expiration of 2032-07-08). No district court complaint, ITC investigation, or CAFC appeal asserting or challenging this specific patent surfaced in my searches.
What I searched and what I found
| Source / query approach | Result |
|---|---|
Unified Patents litigation portal (portal.unifiedpatents.com/litigation) |
No case list entry for 8,785,286 |
| RPX Insight litigation documents | No hit tied to 8,785,286 |
| Justia / CourtListener / Docket Alarm / PACER-adjacent aggregation | No case referencing 8,785,286 |
| Google Patents page for US8785286 ("Cited By" / litigation tabs) | No litigation section populated |
Queries: US8785286 litigation, "8,785,286" patent infringement complaint, "8785286" patent case docket, "8,785,286" FinFET TSMC patent asserted lawsuit |
Returned only unrelated matters (see caveats below) |
There is no case table to populate: no plaintiff, defendant, jurisdiction, case number, filing date, or outcome can be reported because no such case was located.
Important caution — do not conflate with similarly-numbered patents
My searches repeatedly surfaced other patents tagged with "878" or "528," none of which is US 8,785,286. In particular:
- The " '878 Patent" in the Roku / Samsung / Meta IPRs (IPR2022-01315 filed 2022-07-27 against claims 1–23; IPR2022-01505; IPR2023-01281) is a different patent. US 8,785,286 has 18 claims, not 23, and its subject matter is FinFET fabrication, not the Madhavan/Baum/Sitaraman prior-art combinations cited in those petitions. I interpret these identifiers literally and do not treat them as referring to US 8,785,286.
- Other unrelated "878"/"528" hits included Medtronic's U.S. 7,109,878 (Insulet), Rudolph Technologies' '528 patent (Camtek), and an ESW/Roku '782 patent — all distinct from US 8,785,286.
- A Japanese utility model, JPS62200098U, shares the digits "8785286" as a JP application number (JP8785286U). That is an unrelated 1986 refrigerator hatch-cover filing and is not the same patent.
Confidence and limitations (stated explicitly)
- Confidence that no reported litigation exists: moderate-to-high. Multiple dedicated litigation databases returned nothing.
- I cannot prove a universal negative. District court dockets are not fully free-text indexable across all venues; a recently filed, sealed, or low-visibility case could exist that these searches would not surface. I did not have direct PACER/CAFC docket access in this session.
- Practical context (not a factual finding of litigation): US 8,785,286 is owned by Taiwan Semiconductor Manufacturing Company, Ltd. (TSMC) and is a semiconductor process patent. Such manufacturing patents are frequently maintained defensively rather than asserted offensively, which is consistent with the absence of litigation I observed. I flag this as context, not as a verified reason.
- Related family activity worth noting: the patent has a divisional child, US 8,703,593 (application 13/918,682, filed 2013-06-14, now expired/fee-related). I found no litigation on the '593 either, but if you are tracking the family you should monitor both.
Recommended next steps for a definitive answer
- Run a docket-level search in PACER (all districts) and CourtListener's RECAP on the exact patent number 8,785,286 (not the family).
- Check USPTO PTAB (IPR/PGR/CBM) and Patent Trial and Appeal Board docket for the patent number — no AIA trial was found here, but confirm directly.
- Check the ITC EDIS for Section 337 complaints listing 8,785,286.
- Consider whether you actually mean the related TSMC FinFET-doping patents (e.g., US 8,987,019 "Methods for doping fin field-effect transistors"), which have appeared in broader FinFET patent discussions — but again, I found no assertion of 8,785,286 itself.
If you can tell me the specific litigation you believe exists (party names, court, or year), I can target that docket directly rather than relying on general searches.
Generated 9/30/2026, 4:42:10 AM
Proceedings on file (0)
All PTAB activity →AIA trial proceedings (IPR / PGR / CBM) filed at the USPTO Patent Trial and Appeal Board against this patent. Sourced from the USPTO Open Data Portal and refreshed every six hours; each proceeding number deep-links to the PTAB E2E docket.
No PTAB proceedings on file. This patent has not been challenged via IPR, PGR, or CBM. The absence is itself a signal — well-asserted patents eventually attract IPRs. The LLM analysis below may surface filings the ODP feed hasn’t indexed yet.
PTAB challenges
AIA trial proceedings at the USPTO Patent Trial and Appeal Board — IPR, PGR, and CBM. Petitioners, judge panels, claim-level invalidation outcomes from Final Written Decisions, and Federal Circuit appeals. The single most important defensive datapoint after litigation history.
I'll verify the "no PTAB activity" default against public sources before writing.
No hits so far. Let me run two more targeted checks with different phrasings before concluding.
Let me check two more angles: reexamination history and the TSMC v. GlobalFoundries campaign, which is the most plausible venue for this patent's assertion.
Proceedings overview
Total AIA trial proceedings on US 8,785,286: zero. The USPTO Open Data Portal-derived "PTAB proceedings on file" block is the canonical source for this analysis, and it returns no IPR, no PGR, and no CBM naming this patent; my independent web searches (run 2026-09-30) surfaced no petition, institution decision, Final Written Decision, or Board appeal referencing US 8,785,286 or application 12/702,803. Breakdown by status is therefore 0 active / 0 claims invalidated / 0 claims sustained / 0 settled / 0 institution denials. There are no per-proceeding subsections to write, because there are no proceedings — inventing one would be fabrication.
Defensive posture: this is not a "hardened by surviving IPRs" patent, and it is not a "claims already canceled" patent. It is an IPR-virgin patent — every claim (1–18) is untested before the Board, no § 315(e)(2) estoppel attaches to any party, and a defendant retains a completely clean slate to file. The more important signal is what the absence means: TSMC has never had to defend this patent at the PTAB because the record I can find shows it has never been asserted in a way that provoked a challenge.
Why the "no proceedings" finding is credible (and what it does not prove)
Confusable neighbors I checked and ruled out — these are the likely sources of any "'286" hit you get in a keyword search:
| Reference | Why it is not this patent |
|---|---|
| US 8,198,686 ("the '686 patent") | Asserted by Advanced Integrated Circuit Process LLC (AICP) against TSMC and UMC in E.D. Tex. (complaints filed 2024-08-01 and Sept. 2024); TSMC and UMC each filed IPRs on it (e.g., IPR2025-00682, IPR2025-01053, IPR2025-01090, and related joinder motions). Different patent number, different owner-turned-defendant posture (TSMC is the defendant there; TSMC owns 8,785,286). |
| US 7,885,286 (NetSocket) | Involved in Cisco Systems v. NetSocket, IPR2024-00090; networking, unrelated. Flagged in the earlier summary as the likeliest digit-transposition trap. |
| US 8,785,285 B2 (Tsai et al., TSMC, issued 2014-07-22) | A sibling patent to this one number-wise, cited as prior art on the face of DE 102018100114 A1 and US 9,716,090. One digit off from 8,785,286. If you are docket-searching, search both. |
Limitations on my negative finding, stated plainly:
- I could not query PTAB E2E or PatentCenter directly in this session; my corroboration is web-search coverage plus the ODP-derived structured block. Treat the result as "no evidence found," not a certified negative.
- I searched specifically for an ex parte or inter partes reexamination of 8,785,286 as well (a non-AIA channel that would not appear in the AIA-trial block) and found no evidence of one. Same caveat applies.
- The AICP/TSMC/UMC campaign is live and expanding (a second AICP complaint, 2:25-cv-00324, asserted four more patents). Because TSMC owns 8,785,286, TSMC's own patents are not the targets there — but if you are a TSMC competitor being sued on this patent, the AICP docket is the best available proxy for how TSMC-family semiconductor process patents get litigated in E.D. Tex. right now.
Strategic summary
Claim status — all untested. Claims 1–18 of US 8,785,286 stand exactly as issued on 2014-07-22. Nothing has been canceled by the Board, nothing has been confirmed over a prior-art challenge, and nothing has been narrowed by reexamination. Independent claims 1 (requiring a "substantially pure" n/p impurity dopant layer plus a carbon/Ge/Ar/N Markush knock-on species), 11 (adds the "forms an LDD region of a FinFET" purpose limitation), and 16 (the broadest — no purity limitation, no LDD limitation) are all live and all untested. The divisional US 8,703,593 B2 (from application 13/918,682) shares the same 2010-02-09 priority and, per the provided data, is Expired – Fee Related — so an attack on the '286 is not complicated by a live continuation issuing new claims.
Estoppel landscape — a clean slate for everyone. Because no IPR was ever instituted and no Final Written Decision ever issued, no one is under § 315(e)(2) estoppel with respect to this patent. A defendant facing assertion today may raise any prior-art ground under §§ 102/103 in an IPR — including the references already on the face of the patent (US 2007/0084564 to Varian, "Conformal doping apparatus and method"; US 8,071,451 to Axcelis) and the § 112 written-description/enablement angles that the "substantially pure" and Markush limitations invite. The corollary is also true: because TSMC has never obtained a Board decision construing these claims, TSMC has no favorable IPR claim constructions or prosecution-disclaimer admissions to lean on — but conversely, there is no Patent Owner Response or disclaimer on record narrowing "substantially pure" or "knock-on implantation," so claim-scope fights are wide open in district court.
Channel availability — this matters more than the estoppel point. The patent's effective filing date is 2010-02-09, before the 2013-03-16 AIA date, so PGR is categorically unavailable (§ 321 applies only to first-to-file patents) and the CBM transitional program has expired. That leaves IPR as the only AIA trial vehicle, and IPR under § 311(b) is limited to patents and printed publications — no product/system prior art, no § 112 grounds. Any remaining invalidity theory built on prior public use, on-sale activity, or an enablement/indefiniteness attack on "dispatched" / "foaming" / "substantially pure" must be litigated in district court, not at the Board.
Pattern signals. No repeat petitioner (there are none), no PTAB appeal history (there is none), and no defensive aggregator in the chain — Unified Patents, RPX, and similar entities have no proceeding on this patent. On the contrary, TSMC itself is an active IPR petitioner in 2025 against third-party semiconductor patents (the AICP campaign), which confirms TSMC uses the PTAB offensively where it is a defendant; it simply has never needed to defend 8,785,286 there.
Recommended next steps
If you are a defendant being asserted on US 8,785,286:
- Stop reading the demand letter as evidence of a hardened patent. There is no FWD to point to and no canceled claim to cite. Your opening position is the reverse of the usual one: the claims are untested and no estoppel constrains anyone.
- Confirm the negative yourself before you rely on it. Check (a) PTAB E2E → "Patent Trial Proceedings" → search by patent number 8,785,286 (and by 8,785,285 and 8,703,593, in case of capture of the family); (b) USPTO PatentCenter for the ex parte reexamination record; (c) CourtListener and Docket Navigator for district-court and ITC assertions. Do this before any § 315(b) or estoppel analysis is committed to paper.
- Watch the § 315(b) clock. No IPR is on file, so the one-year bar is running (or will run) from yourservice of a complaint alleging infringement. If you have already been served more than one year ago, IPR is time-barred for you and your privies — the analysis shifts entirely to district-court invalidity and to § 315(c) joinder, which requires an existing instituted proceeding that does not exist here.
- Watch the maintenance-fee status. The provided data shows a maintenance-fee reminder mailed 2026-03-09 for the 12th-year fee (grant date 2014-07-22). The 8th-year fee was paid 2022-01-05 and the patent is recorded Active with adjusted expiration 2032-07-08. If the 12th-year fee lapses (including the 6-month grace window), the patent expires early and the case can be mooted without any PTAB filing at all — verify current fee status on PatentCenter before investing in an IPR.
- Build the IPR around the Markush and purity limitations. Claim 1's "substantially pure layer comprising substantially pure n-type or p-type impurity" and the "carbon, germanium, argon, or nitrogen" knock-on species are the narrowest, most attackable features; claim 16 is the broadest and correspondingly the most vulnerable to the cited conformal-doping and ion-assisted deposition art on the face of the patent. Note that an IPR on claim 1 alone leaves claim 16 standing — challenge the independent claims together.
If no assertion has reached you: there is nothing to defend against yet, and the absence of PTAB activity is best read as evidence that this patent has not been a preferred assertion vehicle rather than as evidence of unusual strength. The practical trigger to revisit this file is TSMC (or a TSMC-linked plaintiff) asserting US 8,785,286 against anyone — at that point an IPR on independent claims 1, 11, and 16, filed within one year of service, is the natural first move.
Sources consulted (no proceeding-specific documents exist to link): the ODP-derived structured block in this prompt; Google Patents record for US 8,785,286 (https://patents.google.com/patent/US8785286/en); PTAB petition/decision documents surfaced in search for the AICP v. TSMC/UMC '686 campaign (https://ptacts.uspto.gov/ptacts/public-informations/petitions/[1557994](/patent/1557994), /1558120, /1557982, /1558431) — cited here only to explain why they are not this patent.
Generated 9/30/2026, 4:42:28 AM
Ownership chain (1)
Asserters network →Structured records extracted from the assignment-history narrative below. Each entity links to its full ownership-network profile.
2010-02-11 · recorded 2010-04-27 · reel 024297/0211 · Assignment
Tsai, Chun Hsiung; Chan, Chien‑Tai; Yeh, Mao‑Rong; Lin, Da‑WenTAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
employment assignment
Assignment history
Inventors, original assignee, and the chain of ownership recorded with the USPTO — including the correspondent attorney who recorded each assignment, since shell-LLC chains often share one repeat-player attorney even when the entity names look unrelated. Surfaces NPE / patent-troll patterns: shell-entity transfers, known asserters in the chain, repeat correspondent fingerprints, pre-litigation assignments, and bankruptcy fire-sales.
Inventors
| # | Inventor | Address of record (per TSMC assignment template practice) | Employer at filing |
|---|---|---|---|
| 1 | Chun Hsiung Tsai | Hsinchu County, Taiwan (R.O.C.) | TSMC (Hsinchu Science Park) |
| 2 | Chien‑Tai Chan | Taiwan (R.O.C.) | TSMC |
| 3 | Mao‑Rong Yeh | Taiwan (R.O.C.) | TSMC |
| 4 | Da‑Wen Lin | Hsinchu City, Taiwan (R.O.C.) | TSMC |
All four are named on the cover of US 8,785,286 and all four executed the inventor→employer assignment (the assigning instrument lists "TSAI, CHUN HSIUNG; CHAN, CHIEN‑TAI; YEH, MAO‑RONG; AND OTHERS" — the fourth being Da‑Wen Lin). Execution date on the paperwork: 2010‑02‑11, two days after the 2010‑02‑09 filing date, i.e. a standard file‑with‑the‑application employment assignment, not a later‑staged transfer.
Unusual patterns: None detectable, and the evidence runs against the "inventors depart → fire‑sale" tell. Lead inventor Chun Hsiung Tsai reappears as a named inventor on later TSMC filings in the same family/field, including US 9,209,280 ("Methods for doping fin field‑effect transistors," TSMC, issued 2015) and the 2018 TSMC application "FinFET fabrication methods" (docket P20171045US00, which also lists Da‑Wen Lin). Continued co‑inventorship years after 2010 is affirmative evidence of continued TSMC tenure, not attrition. Inventor addresses are all Hsinchu‑area, consistent with TSMC's Hsinchu Science Park campus. Confidence: moderate — I have not pulled the inventors' full patent portfolios to prove continuous employment.
Original assignee
Taiwan Semiconductor Manufacturing Company, Ltd. ("TSMC") — Hsinchu Science Park, Hsinchu, Taiwan 300‑78, R.O.C.
- Primary line of business: the world's largest dedicated semiconductor foundry (wafer fabrication for third‑party fabless and IDM customers).
- Product embodying the claims: Yes. US 8,785,286 is a process/doping patent reciting steps used to form FinFET lightly‑doped source/drain regions. The specification expressly frames the method as an alternative to BSG/PSG diffused LDDs and tilted‑beamline LDD implants — i.e., production FinFET flow. AICP's later complaint (RPX Insight doc 15789099) documents TSMC manufacturing FinFET nodes down to 5 nm; the present patent's techniques fall directly within that manufacturing practice. The claims are practiced in the fab, not sold as a discrete product, which is the normal posture for a foundry process patent.
- Current status: Operating; publicly listed (NYSE: TSM; TWSE: 2330). No bankruptcy, no dissolution, no acquisition. TSMC is the original AND current assignee — there is no post‑issuance change of owner of record.
Assignment timeline
I was working from the Google Patents legal‑events record (which reproduces the USPTO assignment data) and cross‑checked against USPTO/plainsite assignment artifacts accessible via web search. USPTO Assignment Center was not directly queryable in this session, so the reel/frame below is taken from the patent's legal‑events entry rather than a live Assignment Center screen. Search the number at https://assignment.uspto.gov/patent/index.html (query: 8785286) or https://assignmentcenter.uspto.gov/ to re‑verify.
One — and only one — recorded assignment exists:
- 2010‑02‑11 (executed) / recorded 2010‑04‑27 — Reel 024297/0211
- Conveyance: Assignment ("ASSIGNMENT OF ASSIGNORS' INTEREST")
- Assignor: Tsai, Chun Hsiung; Chan, Chien‑Tai; Yeh, Mao‑Rong; Lin, Da‑Wen
- Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
- Correspondent: Not recovered from the sources available this session. The legal‑events text gives only the REEL/FRAME and the assignor list; it does not expose the correspondent block. I will not guess. *(Cross‑reference for later‑era TSMC recordings: TSMC's recurring correspondent of record is Hauptman Ham, LLP, 2318 Mill Road, Suite 1400, Alexandria, VA 22314, email
tsmc@ipfirm.com, submitter Randy A. Noranbrock — see e.g. TSMC assignment 508040770 recorded 2023‑07‑31; Hauptman Ham is also the "attorney agent or firm" on TSMC's US 9,209,280, a sibling FinFET‑doping patent by the same lead inventor. This is a later‑era data point and is NOT confirmed for reel 024297/0211; treat it as a lead to verify, not a finding.)* - Context: Ordinary employment assignment — all named inventors conveying to their employer contemporaneously with application filing. Not a fire‑sale, not a reorg, not a securitization, not an asserter transfer.
No other recorded events. Specifically, there is no security agreement, no release, no merger, no change‑of‑name, no corrective assignment, and no transfer of the patent away from TSMC. The divisional child US 8,703,593 (app. 13/918,682, filed 2013‑06‑14) also records TSMC as owner and likewise shows no assignment away from TSMC in the family data.
Post‑issuance TSMC‑maintenance activity (from legal events) corroborates uninterrupted TSMC ownership: 4th‑year maintenance fee 2018‑01‑11, 8th‑year fee 2022‑01‑05, and a maintenance‑fee reminder mailed 2026‑03‑09.
Timeline diagram
timeline
title Ownership of US 8785286
2010 : Inventors execute assignment 11 Feb
: Application 12702803 filed 9 Feb
: Assignment recorded 27 Apr reel 024297 0211
2011 : Pre grant publication US 20110195555 A1
2013 : Divisional child 13918682 filed
2014 : US 8785286 granted 22 Jul to TSMC
2015 : Divisional issues as US 8703593
2018 : 4th year maintenance fee paid
2022 : 8th year maintenance fee paid
2032 : Adjusted expiration 8 Jul
NPE / troll‑pattern signals
| # | Signal | Call | Supporting evidence |
|---|---|---|---|
| 1 | Shell‑entity transfer | Not present | The sole recorded assignment (reel 024297/0211) runs inventor→TSMC, an operating foundry. No "IP/Patents/Holdings/Ventures" LLC ever appears. No registered‑agent address of record; assignee address is TSMC's Hsinchu Science Park campus. |
| 2 | Known asserter in the chain | Not present | Neither the original nor current assignee matches Acacia, Marathon, IV, IPNav, Wi‑LAN, Conversant/Mosaid, Vringo, Pendrell, Innovatio, Round Rock, or any Unified Patents / RPX high‑frequency plaintiff list. TSMC owns it directly, in its own name, to this day. |
| 3 | Repeat correspondent across the chain | Unclear / not applicable | There is only one link in the chain, so "recurrence" cannot arise. The correspondent block for reel 024297/0211 was not recoverable in this session; I explicitly decline to attribute Hauptman Ham (a TSMC correspondent in other recordings) to this reel without confirmation. |
| 4 | Cascading transfers (<24 months through chained LLCs) | Not present | A single assignment, executed 2010‑02‑11 and recorded 2010‑04‑27, with no downstream links whatsoever. |
| 5 | Pre‑litigation transfer | Not present | The only assignment dates to 2010, four years before grant and with no associated infringement suit on this patent (consistent with the prior Litigation section finding no case). No within‑6‑months‑of‑suit transfer exists to evaluate. |
| 6 | Bankruptcy fire‑sale | Not present | TSMC has not filed Chapter 7/11; it remains a going concern and the recorded owner. No receiver/trustee conveyance appears. |
| 7 | Privateering | Not present | No transfer — express or by recorded instrument — to any asserting entity; TSMC retains title and has not carved the patent out to an NPE. |
| 8 | Defensive aggregator (anti‑NPE) | Not present | The chain does not terminate at RPX, AST, LOT, Unified Patents, or OIN. Title stays with TSMC. (TSMC is separately a LOT Network member, but that is a licensee‑network membership, not an assignment of this patent — I flag it only so it is not mistaken for a reel/frame transfer.) |
Verdict
Insufficient data — in the rubric's precise sense of "only the original assignment." The complete recorded chain is a single inventor→employer assignment, executed 2010‑02‑11 and recorded 2010‑04‑27 at reel 024297/0211, naming TSMC as assignee, with no subsequent conveyance of any type. Because the chain contains no post‑issuance transfer, there is no NPE event to score; and because the prior Litigation section found no infringement suit on this patent, the "operating‑company assertion" category (which requires the owner to be suing actual competitors on these claims) is also not triggered.
Practical read (not a scored category): the absence of any assignment away from TSMC is itself the finding — US 8,785,286 has never left its original operating‑company owner, and every NPE/troll indicator above is either not present or not applicable. This is consistent with a defensively‑maintained foundry process patent. Verify the reel 024297/0211 correspondent block directly at the USPTO Assignment Center (https://assignmentcenter.uspto.gov/, search 8785286) to close the one remaining data gap.
Generated 9/30/2026, 4:42:40 AM
Prior art
Earlier patents, publications, and products that may anticipate or render the claims unpatentable.
I'll verify the key cited references before analyzing them. Let me run targeted searches.
Let me verify the remaining key references.
Prior-Art Analysis: US 8,785,286 B2 ("Techniques for FinFET doping")
Scope, method, and cross-reference to prior sections
This section builds on the bibliographic data, claim breakdown, and litigation findings already produced. I do not repeat them. Two scope notes before the analysis:
- Grounding: The citation universe below is taken verbatim from the authoritative full text of US 8,785,286 B2 as fetched from Google Patents (https://patents.google.com/patent/US8785286/en) — specifically the "Patent Citations (23)," "Citations (17)," and "Family Cites Families (1)" lists. I verified the substance of the four references most likely to matter (Varian, Kaufman & Robinson, Axcelis, and the Varian sibling
US7524743) by web search. I could not pull the USPTO PatentCenter "References Cited" / examiner's form PTO-892 directly in this session, and I could not retrieve the full text of several older cited documents before hitting search limits. Where I have not verified content, I say so rather than guess. - Legal standard applied: Because US 8,785,286 has a priority/filing date of 2010-02-09 (pre-AIA), a §102 anticipation analysis requires a single reference that discloses every element of a given claim, arranged as claimed. "Anticipation" is a claim-by-claim, element-by-element test. Most of the 23 citations are not anticipatory — they are background or basis for §103 obviousness. I flag this explicitly in every row rather than implying that "cited" = "anticipatory."
Full citation list (examiner-cited references are marked *; all others were listed by the applicant/on the face): *JPH04245643A, US5844278A, *US5648673A, US6238537B1, US6858478B2, US6706571B1, US2005/0153490A1, US2007/0122954A1, US2007/0132053A1, US7605449B2, US2009/0181477A1, US2007/0122953A1, US2007/0120156A1, US2007/0128782A1, US7190050B2, US7247887B2, US7265008B2, US2008/0290470A1, US7528465B2, US7508031B2, *US2007/0026615A1, *US2007/0084564A1, US2008/0296632A1, and the family-cited US8071451B2.
1. Master table — every citation with an anticipation assessment
| # | Reference | Filed / Priority | Published / Granted | Assignee | Brief description | Potential §102 anticipation of US 8,785,286 claims |
|---|---|---|---|---|---|---|
| 1 | JPH04245643A (Kawasaki Steel) * |
1991-01-31 | 1992-09-02 | Kawasaki Steel Corp. | JP application, "Manufacture of semiconductor device" — general impurity-layer/semiconductor fabrication process. Full text not retrievable this session. | None demonstrable. Older than the FinFET era; discloses no fin + dopant-rich-layer + knock-on combination. At most §103/background if it shows impurity drive-in techniques. |
| 2 | US5844278A |
1994-09-14 | 1998-12-01 | Kabushiki Kaisha Toshiba | "Semiconductor device having a projecting element region" — early 3-D/projecting (proto-fin) transistor structure. | None. Discloses a fin-like projecting region only — a subset of claim 1's preamble ("semiconductor fin"). No dopant-rich layer, no knock-on implant. |
| 3 | US5648673A (Nippon Steel) * |
1994-12-28 | 1997-07-15 | Nippon Steel Corp. | "Semiconductor device having metal silicide film on impurity diffused layer or conductive layer." | None. Concerned with silicide-on-diffusion-layer structures; no dopant-rich layer deposition on fin sidewalls, no knock-on implantation. |
| 4 | US6238537B1 |
1998-08-06 | 2001-05-29 | Kaufman & Robinson, Inc. | "Ion assisted deposition source" — apparatus that deposits a film while bombarding it with <200 eV/ion to densify it ("ion assisted deposition"). | None. Discloses the ion-assisted deposition apparatus concept relevant to claim 7's PIAD but no fin, no dopant layer on sidewalls, no knock-on implant. §103 support for the "PIAD" limitation. |
| 5 | US6858478B2 |
2002-08-23 | 2005-02-22 | Intel Corp. | "Tri-gate devices and methods of fabrication" — canonical fin/tri-gate FinFET fabrication. | None. Establishes the "semiconductor fin" preamble and gate-on-fin structure (claims 4/13). No dopant-rich layer + knock-on. §103 background only. |
| 6 | US6706571B1 |
2002-10-22 | 2004-03-16 | Advanced Micro Devices | "Method for forming multiple structures in a semiconductor device" — fin formation. | None. Fin-patterning background; no doping-by-knock-on teaching. |
| 7 | US2005/0153490A1 |
2003-12-16 | 2005-07-14 | Jae-Man Yoon | "Method of forming fin field effect transistor" — FinFET formation with source/drain implants. | None. Shows conventional FinFET source/drain implant practice; does not disclose a conformal dopant-rich layer or recoil/knock-on implant. |
| 8–20 | US2007/0122954A1; US2007/0132053A1; US7605449B2; US2009/0181477A1; US2007/0122953A1; US2007/0120156A1; US2007/0128782A1; US7190050B2; US7247887B2; US7265008B2; US2008/0290470A1; US7528465B2; US7508031B2 (Synopsys family, corrugated substrate / segmented-channel MOS) |
all 2005-07-01 | 2007-03-13 → 2009-10-20 | Synopsys, Inc. | A large family covering corrugated-substrate / segmented-channel MOS transistors, fin-like channels, selective epitaxial source/drain, stressors, and high-k isolation. | None individually. They supply the fin-channel and source/drain-region context, and several mention epitaxial stressor source/drains (relevant to the specification's SiC/SiGe alternative). None discloses a substantially-pure dopant-rich layer formed on fin sidewalls followed by knock-on implantation. §103 background only. |
| 21 | US2007/0026615A1 (Goktepeli) * |
2005-07-27 | 2007-02-01 | (individual applicant) | "Method of forming a FINFET structure" — FinFET structure formation. | None alone. Examiner-cited; likely used for the FinFET/fin-and-LDD structural environment. No conformal dopant layer, no knock-on. §103 candidate when combined. |
| 22 | US2007/0084564A1 (Varian) * |
2005-10-13 | 2007-04-19 | Varian Semiconductor Equipment Associates | "Conformal doping apparatus and method." Discloses depositing a dopant-containing layer on the planar and nonplanar (fin/trench) features of a substrate, then performing a "knock-on implant" — defined as recoil implantation where a non-dopant species drives the deposited dopant into the substrate — at non-normal (tilted) angles, using inert ions including argon, followed by photoresist strip and anneal. FIG. 7 simulates this with a pure boron layer and a 500 eV Argon knock-on on fin-like or trench structures. | The single most relevant §102 reference. Potentially anticipates claim 16 (broadest), claim 1 (if the FIG. 7 pure-B layer is treated as a "substantially pure" impurity layer and if residual-layer removal is read in), claim 3 (tilt), claims 7/18 (plasma-based deposition), and arguably claim 11 (FinFET/sidewall doping context; "LDD" not express). See element-by-element analysis below. |
| 23 | US2008/0296632A1 |
2007-05-30 | 2008-12-04 | Synopsys, Inc. | "Stress-enhanced performance of a FinFET using surface/channel orientations and strained capping layers." | None. Strain-engineering background; unrelated to dopant-layer/knock-on doping. |
| — | US8071451B2 (Axcelis) — family-cited, not on the §286 face |
2009-07-29 | 2011-12-06 (pub. US2011/0027957A1, 2011-02-03) |
Axcelis Technologies, Inc. | "Method of doping semiconductors" — orientation-independent conformal doping of 3-D / multi-gate (tri-gate, gate-all-around) devices by forming a reactive (H-terminated) layer and reacting a dopant with it. Notes line-of-sight limits of implant and problems with thermal-diffusion-from-glass routes. | No anticipation. Filed 2009-07-29 (before the '286 priority date) → qualifies only as pre-AIA §102(e) art. It discloses conformal sidewall doping of fins but no knock-on/recoil implantation and no "dopant-rich pure impurity layer." §103 candidate for the sidewall-conformal-doping concept. |
2. Tier 1 — the reference that could actually anticipate: US 2007/0084564 A1 (Varian)
Citation: US 2007/0084564 A1, "Conformal doping apparatus and method," Varian Semiconductor Equipment Associates, Inc.; filed 2005-10-13 (App. 11/163,303); published 2007-04-19. URL: https://patents.google.com/patent/US20070084564A1/en (verified; its grant sibling with method claims is US 7,524,743 B2, "Conformal doping apparatus and method," Gupta et al., granted 2009-04-28, https://uspto.report/patent/grant/[7524743](/patent/7524743)).
What it discloses (verified from the specification text):
- Deposition of a "layer of dopant containing material" on the planar and nonplanar features of a substrate, used with hydride/fluoride gases (B₂H₆, PH₃, AsH₃, BF₃, PF₃, PF₅, AsF₅).
- A "knock-on implant," expressly defined as "a recoil implantation where a non-dopant species is implanted through the surface layers of the substrate to drive the dopant material into the substrate."
- Knock-on species from inert feed gas "He, Ne, Ar, Kr and Xe" (Argon is expressly within this set; FIG. 7's simulation uses a 500 eV Argon beam through a pure boron surface layer).
- Non-normal / tilted impact angles (e.g., normal on planar features, ~85° on vertical sidewalls; or non-normal on all features).
- Process sequence including photoresist stripping after the knock-on step and a drive-in/activation anneal (RTA, laser, flash).
- Explicit application to FinFETs and fin-like or trench structures.
Element-by-element against the independent claims:
| Claim element | Disclosed by Varian '564? |
|---|---|
| Wafer with a semiconductor fin | Partly — discloses planar/nonplanar features and fin-like structures; "fin" per se is described generically, not as a FinFET process flow. |
| Dopant-rich layer on top surface and sidewalls of the fin | Yes — dopant-containing layer on planar and nonplanar features, including sidewalls. |
| Layer is a "substantially pure" n- or p-type impurity (claim 1) | Arguable — the FIG. 7 simulation uses a "layer of Boron" (pure B). The general disclosure uses dopant-containing hydride/fluoride films, which are not "substantially pure." This is the strongest distinction against claim 1. |
| Knock-on implantation using carbon, germanium, argon, or nitrogen | Yes as to argon (Ar is expressly listed; FIG. 7 uses Ar). C, Ge, N are not disclosed. |
| Removal of the dopant-rich layer substantially completely | Weak/absent — Varian strips photoresist but does not expressly recite removing the residual deposited dopant layer. |
| Knock-on forms an LDD region of a FinFET (claim 11) | Arguable — Varian discusses FinFET sidewall/fin-like doping but does not use the term "LDD region." |
Bottom line: Varian '564 (and its grant sibling US7524743) is the only cited reference that discloses the core inventive combination — deposit dopant on fin/sidewall features → knock-on (recoil) implant with inert ions at a tilt → strip mask → anneal. It is a strong §102 basis against the broadest independent claim 16, and a strong §103 basis (alone or with the FinFET-structure references) against claims 1 and 11, where the "substantially pure" and "LDD region" limitations supply the only daylight. That Varian's inert set (He/Ne/Ar/Kr/Xe) is broader than the '286 Markush ("carbon, germanium, argon, or nitrogen") is consistent with the Markush having been added to carve out novelty — an inference only, since I do not have the '286 prosecution history.
3. Tier 2 — §103-only references (disclose subsets, not the whole claim)
| Reference | Element(s) it supplies | Claim(s) it could combine against (§103) |
|---|---|---|
US6238537B1 (Kaufman & Robinson) |
Ion-assisted deposition of a film under concurrent ion bombardment — the PIAD concept | Claims 7, 8, 9, 15, 18 (PIAD / DC-bias limitations) |
US6858478B2 (Intel), US6706571B1 (AMD), US2005/0153490A1, the Synopsys family, US2007/0026615A1 (Goktepeli) |
Fin formation, gate-on-fin stack, LDD/source-drain implant environment | Preamble + claims 4, 5, 13 (gate dielectric/electrode on fin; LDD of a FinFET) |
US5844278A (Toshiba) |
Projecting/fin element region | Preamble (fin structure) |
US5648673A, JPH04245643A |
Impurity-diffused layers / general doping-process steps (content unverified) | Background; not mapped to a specific claim |
US8071451B2 (Axcelis) |
Orientation-independent conformal doping of 3-D/multi-gate device surfaces (sidewalls and top) | §102(e) art for the "sidewalls" requirement; §103 backdrop for the conformal-doping motivation |
None of these, taken alone, discloses a substantially pure impurity layer on fin sidewalls knocked into the fin by a carbon/Ge/argon/nitrogen implant with subsequent removal — so none anticipates any claim.
4. Claim → most-relevant-art map (summary)
| Claim | Closest cited art | Anticipation (§102) or obviousness (§103)? |
|---|---|---|
| 1 | US2007/0084564A1 (Varian) |
§102 possible only if the pure-B FIG. 7 embodiment counts as a "substantially pure" layer and layer-removal is read in; otherwise §103. |
| 2 | US2007/0084564A1 |
§103 (pure-dopant layer not expressly claimed). |
| 3 | US2007/0084564A1 |
§102 possible — Varian expressly teaches tilted/non-normal knock-on angles. |
| 4, 13 | US6858478B2; US2007/0026615A1 |
§103 (gate stack on fin is conventional). |
| 5, 11 | US2007/0084564A1 (+ Intel fin art) |
§103; §102 for claim 11 is arguable but "LDD region" is not express in Varian. |
| 6, 14 | US2007/0084564A1 |
§102/§103 — Varian teaches photoresist masking and stripping around conformal doping. |
| 7, 8, 9, 15, 18 | US6238537B1; US2007/0084564A1 |
§103 (PIAD and low/no DC bias are the point of joint). |
| 10 | — | Not anticipated by any cited reference (complete removal is a minor express limitation). |
| 16 (broadest) | US2007/0084564A1 |
Strongest §102 candidate — Varian discloses deposit-dopant / knock-on-with-Ar / tilt / strip. Weakness: express "substantial complete removal" of the dopant layer. |
| 17 | US2007/0084564A1 (pure-B FIG. 7) |
§103; §102 arguable. |
| 12 | US2007/0084564A1; US8071451B2 |
§103. |
5. Honest limitations of this analysis
- I am not rendering a legal conclusion. Anticipation must be assessed element-by-element against the issued claim language by a person of ordinary skill, and I have not read every cited document in full. Where I wrote "arguable," I mean the reference's disclosure is close but the specific claim term is not literally reproduced.
- Not all cited documents were verified. I could not retrieve the full text of
JPH04245643A,US5844278A,US5648673A,US6706571B1,US2005/0153490A1, the Synopsys family, orUS2007/0026615A1in this session (search limits reached). Their descriptions are based on titles/abstracts and field knowledge and should be re-verified against the primary documents (USPTO PatentCenter / Google Patents) before relying on them. - The single most important omission from the face of the patent is the grant sibling
US7524743B2(Varian; method claims to "depositing a layer of dopant material on nonplanar and planar features; generating inert ions … extracting the inert ions towards the substrate, the inert ions physically knocking the dopant material into both the planar and nonplanar features"). It is arguably more squarely anticipatory of the method claims than the published applicationUS2007/0084564A1that the '286 actually cites, and it is not listed among the 23 citations. This is a reference worth flagging to any examiner or litigator. - Prosecution history unavailable. Whether the "carbon, germanium, argon, or nitrogen" Markush and the "substantially pure" limitation were added to overcome Varian/Kaufman is an inference from the citation pattern, not a verified fact. Confirming it requires the file wrapper (PatentCenter) — the applicant's amendments and the examiner's §102/§103 rejections would show exactly which references were applied to which claims.
- Identifier discipline. Per the operating rules, I have interpreted every number literally:
US 7,885,286(NetSocket/Cisco IPR2024-00090) andUS 8,785,286are different patents and I have not conflated them; likewiseUS 8,703,593(the divisional child of US 8,785,286) is treated separately.
Priority recommendation: If only one reference can be relied upon, it is US 2007/0084564 A1 (Varian), with US 7,524,743 B2 as its stronger method-claim companion and US 6,238,537 B1 (Kaufman & Robinson) as secondary art directed at the PIAD limitation.
Generated 9/30/2026, 4:43:16 AM
Obviousness
Combinations of prior art that suggest the claimed invention would have been obvious under 35 U.S.C. § 103.
I'll analyze the prior art cited on the face of US 8,785,286 and build § 103 combinations. Let me first pull details on the key references so the analysis is grounded.
Obviousness Analysis of U.S. Patent No. 8,785,286 Under 35 U.S.C. § 103
Note on scope: As instructed, I built this analysis from the Prior Art section of the patent page — the face-of-patent citations (the "Patent Citations (23)" and "Citations (17)" lists, plus the "Family Cites Families (1)" entry) — supplemented by the text I retrieved for those references. I flag below which references are marked as examiner-cited (*) on the face, because that affects how a validity challenge would be framed. I do not treat the "Cited By / Families Citing" lists or "Similar Documents" as prior art.
0. Governing framework and an important date issue
US 8,785,286 was filed 2010-02-09, i.e., before the March 16, 2013 AIA first-inventor-to-file date. Therefore pre-AIA § 102/§ 103 govern, and the analysis uses the Graham v. John Deere factors as refined by KSR Int'l Co. v. Teleflex Inc., 550 U.S. 398 (2007).
Two date consequences that matter:
- Varian US 2007/0084564 A1 (published 2007-04-19) and Goktepeli US 2007/0026615 A1 (published 2007-02-01) both published more than one year before the 2010-02-09 filing → solid pre-AIA § 102(b) prior art for both § 102 and § 103.
- Axcelis US 8,071,451 B2 is different: its application (12/511,737) was filed 2009-07-29 but published 2011-02-03 — after the '286 filing. It therefore has no § 102(a)/(b) status; it can only be § 102(e) art as of its 2009-07-29 filing date, and is usable in § 103 subject to pre-AIA § 103(c). Treat it as secondary/supplemental, not a primary reference.
(Small housekeeping note: the system date in this session reads 2026-09-30 while the task text says April 26, 2026; nothing in the analysis turns on this, but I am flagging the inconsistency rather than silently picking one.)
1. The claims and the limitations that decide the analysis
Per the previously generated claim summary (not repeated here), the independent claims require:
| Limitation | Claim 1 | Claim 11 | Claim 16 |
|---|---|---|---|
| Fin on wafer surface | ✔ | ✔ | ✔ |
| Dopant-rich layer on top surface and sidewalls | ✔ | ✔ | ✔ |
| Layer is substantially pure n/p impurity | ✔ | — (only dep. 12) | — |
| Knock-on implantation using C, Ge, Ar, or N | ✔ | ✔ | ✔ |
| Knocks the impurity into the fin | ✔ | ✔ | ✔ |
| Forms an LDD region of a FinFET | — (dep. 5) | ✔ | — |
| Remove dopant-rich layer substantially completely | ✔ | ✔ | ✔ |
So the three limitations that actually do the work are: (a) conformal dopant layer on top + sidewalls of a fin; (b) a knock-on implant limited to a four-element Markush group; (c) "substantially pure" dopant layer (claim 1 only) and substantial complete removal (all three).
PHOSITA: a person with an M.S. in electrical engineering, materials science, or applied physics (or a B.S. plus ~3–5 years), with working knowledge of CMOS/FinFET front-end processing, plasma doping, and ion implantation. This is a routine, non-inventive-level artisan.
2. The prior art on the face of the patent, and what each reference teaches
| Ref. | Examiner-cited? | Disclosure relevant to the claims |
|---|---|---|
| US 2007/0084564 A1 — Varian, "Conformal doping apparatus and method" (pub. 2007-04-19) | Yes (*) | Conformal plasma doping of 3D structures expressly including FinFETs; depositing dopant material on nonplanar features; "knock-on conformal doping" (FIG. 6) using inert ions at various impact angles; stripping photoresist; annealing to diffuse/activate. |
| US 2007/0026615 A1 / US 7,323,389 B2 — Goktepeli (Freescale), "Method of forming a FINFET structure" (pub. 2007-02-01) | Yes (*) | Sacrificial doping layer formed on the sides of a fin, dopants driven into source/drain extensions by heat, then the layer is "substantially removed" / "removed substantially or completely." Frames the problem as exactly the '286's problem: high-dose implantation into thin, tall fins causes dose loss and amorphization, and tilted implants give vertical profile variation. |
| US 6,238,537 B1 — Kaufman & Robinson, "Ion assisted deposition source" | No | Ion-assisted deposition: bombarding the deposition surface with energetic ions before, during, or after deposition to modify film/property; example operation uses argon as the ionizable gas; ion energy kept < ~200 eV/ion. |
| US 6,858,478 B2 — Intel, "Tri-gate devices and methods of fabrication" | No | FinFET/tri-gate device integration (gate dielectric + gate electrode over fins); establishes the FinFET environment of claims 4/13. |
| US 2005/0153490 A1 — Yoon, "Method of forming fin field effect transistor" | No | FinFET fabrication; device isolation around fins. |
| US 5,844,278 — Toshiba | No | Semiconductor device having a projecting element region (fin-like). |
| US 8,071,451 B2 — Axcelis, "Method of doping semiconductors" | No (listed only under "Family Cites Families (1)") | Conformal doped layer whose thickness/doping is "substantially independent of the physical orientation" — i.e., same doping level at the top of a structure as on the sidewalls; lists dopants including boron, phosphorus, arsenic, and carbon. (§ 102(e)-only art — see § 0.) |
| Synopsys corrugated-substrate family (US 7,190,050; 7,247,887; 7,265,008; 7,528,465; 7,508,031; 7,605,449; and pubs. 2007/0122954 etc.) | No | Fin/corrugated-channel MOS structures. |
The single most important observation: the two references that the examiner actually cited against this application — Varian and Goktepeli — are also the two that disclose the heart of the independent claims. That is the classic posture for a strong § 103 attack.
3. Combination A (primary): Varian + Goktepeli, optionally + Kaufman & Robinson
3a. Why Varian is the closest prior art
Varian's own background states the motivation verbatim at [0004]: "Three dimensional device structures are now being developed… such as the FinFETs (Double or Triple gate)… Many of these three dimensional devices require conformal doping of different features." The reference then discloses a deposition-then-drive-in scheme in which dopant material is deposited on the nonplanar features and the wafer is annealed (Varian's published-application text: "The substrate is annealed to diffuse dopant material in the planar and the nonplanar features of the substrate"; and "Photoresist layers are then stripped").
Critically, Varian discloses at FIG. 6 a "process diagram of a method of knock-on conformal doping," and its specification describes the third step "with two different inert ion 612 impact angles." In other words, Varian already teaches using inert ions, at controlled (tilted) angles, to knock a deposited dopant layer into the underlying structure — which is the '286's core mechanism.
Source: https://patents.google.com/patent/US20070084564A1/en and https://patents.justia.com/patent/20070084564
3b. Why Goktepeli supplies the fin-specific "deposit-on-sidewalls / remove-layer" teachings
Goktepeli's abstract states: "a sacrificial doping layer (28, 30) is formed on the sides of the fin area. Dopants from the sacrificial doping layer are diffused into the source electrode and the drain electrode using heat. Subsequently a substantial portion, or all, of the sacrificial doping layer is removed from the fin." Claim 1 recites "removing at least a substantial portion of the first sacrificial doping layer." Its background explains that "the need to use angled and tilted implants for the source/drain extension and source/drain regions leads to vertical variation in the implant profile" — the same tilt/shadowing problem the '286 identifies in FIG. 1 and the Background.
Source: https://patents.google.com/patent/US20070026615 and https://patents.google.com/patent/US7323389
3c. Claim chart — Combination A (Varian + Goktepeli + Kaufman & Robinson)
Independent claim 1:
- Fin on a wafer surface → Varian [0004] (FinFETs) and Goktepeli Fig. 1 (fin 20).
- Dopant-rich layer on top surface and sidewalls → Varian's conformal doping on "planar and nonplanar features," expressly to dope tops and sidewalls of 3D features; Goktepeli forms the layer "on the sides of the fin."
- Layer is a substantially pure n- or p-type impurity → Varian's dopant deposition from dopant feed gases (the reference discusses dopant flux from AsH₃/B₂H₆-type chemistries). This is the weakest point of the challenge — see § 6.
- Knock-on implantation using C, Ge, Ar, or N → Varian FIG. 6 ("knock-on conformal doping") using inert ions; argon is the canonical inert knock-on species and is expressly the working gas in Kaufman & Robinson's example. The Markush is satisfied by any one of the four, and Argon is squarely taught/suggested.
- Remove the dopant-rich layer substantially completely → Goktepeli: removal of "a substantial portion, or all" of the sacrificial layer; plus Varian's photoresist-strip/clean sequence.
Independent claim 11 differs only by requiring that the knock-on form an LDD region of a FinFET — Goktepeli targets the source/drain extension regions (i.e., LDD) of a FinFET, and Varian names FinFETs.
Independent claim 16 is the same skeleton without "substantially pure" and without the LDD language — so Combination A meets it essentially entirely, with only the more routine elements remaining.
Dependents: claim 3 (tilt) ← Varian's "two different inert ion impact angles"; claim 4 (gate dielectric + gate electrode first) ← Intel US 6,858,478 / Goktepeli's gate feature 18 formed before the sacrificial layer; claims 7–9 (PIAD; DC bias < 1.5 kV / none) ← Varian's plasma doping tool with a DC/RF/pulsed platen bias supply plus Kaufman & Robinson's low-energy (< 200 eV/ion) ion-assist teaching, which is far below 1.5 kV; claim 10 (entire layer removed) ← Goktepeli "or all."
4. Combination B: Goktepeli as primary, Varian as the secondary "drive-in" reference
Goktepeli teaches the whole architecture — sacrificial dopant layer on the fin sides → heat → substantial removal — and expressly identifies the same problem the '286 solves (implant damage/low stopping power in thin tall fins). Goktepeli's drive-in is thermal diffusion; Varian supplies an alternative, known drive-in: knock-on with inert ions.
Motivation: Goktepeli's own text frames ion implantation into thin fins as problematic, and the artisan looking for a non-damaging way to drive the pre-placed dopants into the fin would look to Varian's knock-on conformal doping, which moves dopants using a low-dose, low-energy, non-doping ion flux rather than direct high-dose doping implantation. The substitution of one known drive-in mechanism (thermal) for another known drive-in mechanism (knock-on) to achieve the same result (doped fin sidewalls) is a textbook KSR "substitution of known elements to achieve a predictable result." This combination reaches at least claim 16 (and claim 11, since Goktepeli expressly treats source/drain extensions of a FinFET).
5. Combination C (supplemental): Axcelis '451 + Varian + FinFET art
Axcelis US 8,071,451 is a conformal-doping reference that states its doped layer is "substantially independent of the physical orientation of an underlying surface (e.g., that provides the same doping level at the top of a structure as on the sidewalls)" — i.e., it independently corroborates the "top surface and sidewalls" limitation, and even lists carbon among dopant species. Because it is only § 102(e) art (see § 0), it should be used to buttress rather than to carry the combination. It is most useful as evidence that "conformal doping of fin sidewalls" was a recognized, mainstream goal by mid-2009.
6. Motivation to combine (the KSR rationales)
- Same field, same problem. Varian [0004] and Goktepeli's background both address conformal doping of tall 3D/fin structures where beam-line tilt implantation suffers shadowing and dose loss. The '286's FIG. 1 and Background describe the identical problem.
- Same device. Varian expressly names FinFETs; Goktepeli is a FinFET method. Combining them requires no field-crossing.
- Design incentive / predictable result. Both references teach depositing a dopant source on the feature and then driving the dopant in. Selecting knock-on (Varian FIG. 6) as the drive-in mechanism is the use of a known technique for its known purpose (KSR rationales: "known technique, known result" and "obvious to try" — a finite number of identified, predictable drive-in options with reasonable expectation of success).
- Removal step is squarely suggested. Goktepeli's "substantial portion, or all" removal supplies the "remove substantially completely" limitation and gives an express reason (avoid leaving a foreign layer / complete the doping transfer).
- Bias/tilt parameters are routine optimization. Varian's plasma-doping platen bias and inert-ion impact angles, plus Kaufman & Robinson's sub-200 eV ion-assist teaching, make the DC-bias and tilt limitations (claims 3, 8, 9) matters of routine tuning.
- No teaching away. Goktepeli's criticism of high-dose implant damage does not disparage low-dose, non-doping knock-on; Varian's knock-on embodiment uses inert ions precisely to avoid that damage.
7. Weaknesses, counterarguments, and objective indicia
A. The "substantially pure" limitation (claim 1, and dependents 2, 12, 17) is the strongest non-obviousness argument.
Goktepeli's sacrificial layer is a doped semiconductor (in-situ-doped Si/SiGe), not a pure dopant layer. Varian's deposited dopant material is the better fit, but the retrieved text describes Varian also reacting the deposited material with an oxidizer plasma to render it "at least partially inert," which cuts against "substantially pure… with substantially no other elements." A validity challenge should therefore: (i) find a Varian passage describing deposition of a dopant film from a dopant-only chemistry (or (ii) rely on independent claims 11/16, which omit the purity requirement — this is the path of least resistance, since claim 16 is the broadest claim and requires neither purity nor LDD formation).
B. The C/Ge/Ar/N Markush. Varian says only "inert ions"; it does not, in the text I retrieved, name all four species. But because the Markush is disjunctive, argon alone suffices, and argon is (i) the archetypal inert knock-on species and (ii) the explicit working gas in Kaufman & Robinson's example. The other three species are a secondary point; a challenger would argue they are conventional knock-on/recoil species (note the patent's own CPC tag H10P30/214 "Recoil-implantation").
C. Prosecution history. Both Varian and Goktepeli carry the examiner-cited asterisk on the face of the patent, yet the claims issued. That means an obviousness challenge must explain what the examiner missed — most plausibly, that Varian's FIG. 6 knock-on embodiment was not fully applied, and/or that Varian and Goktepeli were never combined. I could not retrieve the office actions in this session, so I cannot confirm which limitations were argued; this is an explicit uncertainty.
D. Objective indicia. I found no litigation (consistent with the earlier section), no licensing evidence, and no record of industry praise or copying. The only potential "unexpected result" is the patent's own assertion that LDD depth is insensitive to knock-on tilt angle — but that is a simulation assertion about process latitude, which a fact-finder would likely treat as routine optimization rather than a surprising result, absent corroborating data.
E. One caution to keep literal: the earlier sections correctly note that the claim text contains "dispatched" (for "disposed") and "foaming" (for "forming"). I quote them as written above and do not rely on them as claim-construction issues.
8. Bottom line
- Claim 16 is the most vulnerable. Varian (conformal doping of FinFET sidewalls + knock-on with inert ions) in view of Goktepeli (sacrificial layer on fin sides, heat drive-in, substantial removal) discloses or suggests every element. Goktepeli's "substantial portion, or all" removal and Varian's FIG. 6 knock-on are the two linchpin disclosures, and both were already before the examiner.
- Claims 11 and 5 (LDD/extension of a FinFET) are also vulnerable via Goktepeli's source/drain extension treatment plus Varian's FinFET discussion.
- Claim 1 (and 2/12/17, "substantially pure") is the hardest to invalidate, because the cited fin-specific art teaches a doped-semiconductor sacrificial layer, not a pure dopant film; Varian is the only face-of-patent reference that plausibly deposits a near-pure dopant layer, and its oxidizer-plasma step muddies the "no other elements" requirement.
- Confidence: moderate-to-high on the general combination theory (Combinations A–B), moderate on claim 1. Limitations on confidence: (1) I did not retrieve the full specification text of Varian's FIG. 6 knock-on embodiment or the office actions; (2) Axcelis '451 is § 102(e)-only art and cannot carry a combination; (3) no litigation or IPR record exists to test these theories, and I could not access PTAB/PACER directly.
Sources cited: https://patents.google.com/patent/US8785286/en (authoritative full text); https://patents.google.com/patent/US20070084564A1/en and https://patents.justia.com/patent/20070084564 (Varian); https://patents.google.com/patent/US20070026615 and https://patents.google.com/patent/US7323389 (Goktepeli); https://patents.google.com/patent/US6238537 (Kaufman & Robinson); https://patents.google.com/patent/US8071451 (Axcelis); US 6,858,478 (Intel) — cited on the face of the patent; full text not retrieved this session, so treat its description as stated from the face-of-patent title/assignee only.
Generated 9/30/2026, 4:43:28 AM
Extensions
Patent term adjustments, term extensions, continuations, divisionals, family members, and expiration dates.
Derivative works
Defensive disclosure: derivative variations of each claim designed to render future incremental improvements obvious or non-novel.
Keep exploring
Other patents in Semiconductor (T)
- US 6412917I'll search for authoritative records on this patent number, including any 2026 CAFC docket activity. Let me refine with targeted searches on the litigation and any 2026 appellate activity. Search summary — US 6,412,917 (patent number…
- US 10475147Patent Overview — US 10,475,147 B2 Title: Multiple GPU graphics processing system Assignee: ARM Ltd (original assignee and current assignee, per the listing) Key dates: Priority date 2016-02-12; filed 2017-02-09; published as…
- US 5530467I'll search for this specific patent number, including any litigation or CAFC activity. Let me run more targeted searches for any litigation or administrative proceedings. Search scope and limitations I ran multiple queries against the…
- US 5640020I'll search for this specific patent number across patent databases and litigation dockets. Let me run a couple more targeted searches for litigation/CAFC activity and the patent family. US Patent 5,640,020 — Verified Summary Sourcing…
- US 8338929I'll search for information on this specific patent number. The CAFC/litigation search returned nothing. Let me try a couple more targeted checks. Let me do one more targeted check for any CAFC or litigation activity. Search scope and…
- US 7863717I'll search for authoritative information on this specific patent number, including any litigation activity. The CAFC search returned an unrelated patent (7,679,637). Let me verify litigation/docket activity specifically for 7,863,717. US…
- US 7906363I'll search for authoritative information on this patent, including any 2026 CAFC activity. Let me check for any 2026 litigation or CAFC docket activity specifically involving this patent. Let me verify the claim set and confirm no 2026…
- US 6954348I'll verify the patent's bibliographic data and check for any 2026 CAFC/USPTO activity. Let me pull the full claim set and check for any 2026 litigation/docket activity. US Patent 6,954,348 — verification summary Sourcing note: I searched…