Invalidity dossier
US 7535049
Multi bits flash memory device and method of operating the same
Current assignee: Samsung Electronics Co Ltd
Added 9/24/2026, 2:02:49 AM
Active provider: DeepSeek · deepseek-flash
Patent summary
Title, assignee, inventors, filing/issue dates, abstract, and a plain-language overview of the claims.
Patent Overview — US 7,535,049 B2
Title: Multi bits flash memory device and method of operating the same
Patent number: US 7,535,049 B2 (application US 11/249,393; pre-grant publication US 2006/0097306 A1)
Assignee: Samsung Electronics Co., Ltd. (original and current assignee per the source; no legal analysis of assignment accuracy is made)
Inventors: Won-joo Kim, Yoon-dong Park, Eun-hong Lee, Sun-Ae Seo, Sang-Min Shin, Jung-Hoon Lee, Seung-hyuk Chang
Key dates: Priority date 2004-11-09; filing date 2005-10-14; publication date 2009-05-19; adjusted expiration 2027-07-12. Legal status shown as "Expired – Fee Related" (the source describes legal status as an assumption, not a legal conclusion).
Purpose and plain-language scope: The source excerpt identifies the invention as a multi-bit flash memory device and a method of operating it — that is, a flash memory capable of storing more than two states per element ("multi bits"). Prior-art keywords in the source center on an "active layer," "layer," "active," "memory device," and "gate," indicating the disclosed structure involves an active layer and a gate. The source classifies the patent under G11C11/56 and G11C11/5621 (multi-state storage elements, including charge storage in a floating gate), G11C13/025 (elements using fullerenes or nanotubes), B82Y10/00 (nanotechnology for information processing/storage), and H10D30/691 (charge-trapping-gate IGFETs having more than two programming levels). These classifications indicate the claimed subject matter relates to multi-level, charge-storage memory devices, possibly involving nanoscale materials such as nanotubes or fullerenes. Beyond this, the supplied text does not set out the claims, the specific operating method steps, or the detailed device structure.
What the excerpt does not establish: The source text provided is heavily truncated (a classifications listing plus bibliographic data); it does not include the abstract, claims, detailed description, or any drawings. Accordingly, the precise claimed scope, the exact operating method, specific materials, and any prior-art references cited during prosecution cannot be determined from this excerpt. No litigation, ownership-transfer, validity, or prior-art conclusions are drawn.
Generated 10/1/2026, 9:30:56 PM
Cases on file (0)
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Litigation summary
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Proceedings on file (0)
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No PTAB proceedings on file. This patent has not been challenged via IPR, PGR, or CBM. The absence is itself a signal — well-asserted patents eventually attract IPRs. The LLM analysis below may surface filings the ODP feed hasn’t indexed yet.
PTAB challenges
AIA trial proceedings at the USPTO Patent Trial and Appeal Board — IPR, PGR, and CBM. Petitioners, judge panels, claim-level invalidation outcomes from Final Written Decisions, and Federal Circuit appeals. The single most important defensive datapoint after litigation history.
Assignment history
Inventors, original assignee, and the chain of ownership recorded with the USPTO — including the correspondent attorney who recorded each assignment, since shell-LLC chains often share one repeat-player attorney even when the entity names look unrelated. Surfaces NPE / patent-troll patterns: shell-entity transfers, known asserters in the chain, repeat correspondent fingerprints, pre-litigation assignments, and bankruptcy fire-sales.
Prior art
Earlier patents, publications, and products that may anticipate or render the claims unpatentable.
Obviousness
Combinations of prior art that suggest the claimed invention would have been obvious under 35 U.S.C. § 103.
Extensions
Patent term adjustments, term extensions, continuations, divisionals, family members, and expiration dates.
Derivative works
Defensive disclosure: derivative variations of each claim designed to render future incremental improvements obvious or non-novel.