US 8907425

US Patent 8907425, titled "Semiconductor device," was invented by Satoru Itou and Toshie Kutsunai. The patent was filed on June 20, 2012, and issued on December 9, 2014. The original assignee was Panasonic Corp, and the current assignee is Advanced Integrated Circuit Process LLC.

Abstract:
A semiconductor device is disclosed, featuring a first Metal-Insulator-Semiconductor (MIS) transistor. This transistor includes a first source/drain region of a first conductivity type, which incorporates a silicon compound layer. This silicon compound layer is designed to induce a first stress in the gate length direction of the channel region within a first active region. The device also comprises a stress insulating film covering the first gate electrode, a first sidewall, and the first source/drain region, which generates a second stress opposite to the first stress. A key feature is that the uppermost surface of the silicon compound layer is positioned higher than the surface of the semiconductor substrate directly beneath the first gate electrode. Additionally, a first stress-relief film is placed in the space located between the silicon compound layer and the first sidewall.

Plain-Language Overview of Independent Claims:

• Independent Claim 1: Semiconductor Device Structure
  This claim describes a semiconductor device that includes a specific type of transistor called a first MIS transistor. This transistor is built on a semiconductor substrate and has a gate structure (a gate insulating film and a gate electrode) with a sidewall next to it. A crucial part of this transistor is its source/drain region, which is formed within a trench in the substrate. This source/drain region contains a silicon compound layer that applies a specific mechanical stress (the "first stress") to the active part of the transistor (the channel region) to improve its performance. The top surface of this silicon compound layer is raised, sitting higher than the main surface of the substrate under the gate. In the gap between this raised silicon compound layer and the sidewall, a "first stress-relief film" is present. The entire transistor assembly is then covered by a "stress insulating film," which generates a "second stress" that is opposite in direction to the "first stress." The unique arrangement of the raised silicon compound layer and the stress-relief film works to reduce the undesirable effects of the "second stress" on the transistor's performance, while still allowing the beneficial "first stress" to enhance operation.

• Independent Claim 16: Method for Fabricating a Semiconductor Device
  This claim outlines a manufacturing process for a semiconductor device that includes a first MIS transistor. The method involves several distinct steps:
  (a) First, a gate electrode structure, consisting of a gate insulating film and a gate electrode, is created on a specific active region of the semiconductor substrate.
  (b) Next, a sidewall is formed along the side of this gate electrode structure.
  (c) After the sidewall is in place, a trench is created in the active region adjacent to the sidewall. A source/drain region, which includes a silicon compound layer designed to produce a "first stress" in the channel region, is then formed within this trench. A key step here is ensuring that the top surface of this silicon compound layer is higher than the surface of the semiconductor substrate directly under the gate electrode.
  (d) Subsequently, a "first stress-relief film" is formed in the gap between the silicon compound layer and the sidewall.
  (e) Finally, a "stress insulating film" is deposited over the first active region, covering the gate electrode, the sidewall, the source/drain region, and the stress-relief film. This stress insulating film is engineered to exert a "second stress" that counteracts the "first stress." This fabrication method is designed to effectively apply beneficial stress for transistor performance while mitigating unwanted stress from the overlying insulating layers.

Litigation Status:
As of April 26, 2026, the Google Patents entry for US8907425B2 indicates that the patent family has litigation. This includes multiple US cases filed in the Texas Eastern District Court in 2024, as well as two PTAB (Patent Trial and Appeal Board) cases, IPR2025-01090 and IPR2025-00683, both of which were filed but not instituted procedurally. There are no specific CAFC 2026 dockets found directly referencing US Patent 8907425 in the search results provided.