US 8329572

US Patent 8329572: Semiconductor device and method for fabricating the same

Title: Semiconductor device and method for fabricating the same

Assignee:

• Current: Advanced Integrated Circuit Process LLC
• Original: Panasonic Corp

Inventor: Shunsuke Isono

Filing Date: March 18, 2011

Issue Date: December 11, 2012

Abstract:
In a method for fabricating a semiconductor device, first, a first metal interconnect is formed in an interconnect formation region, and a second metal interconnect is formed in a seal ring region. Subsequently, by chemical mechanical polishing or etching, the upper portions of the first metal interconnect and the second metal interconnect are recessed to form recesses. A second insulating film filling the recesses is then formed above a substrate, and the upper portion of the second insulating film is planarized. Next, a hole and a trench are formed to extend halfway through the second insulating film, and ashing and polymer removal are performed. Subsequently to this, the hole and the trench are allowed to reach the first metal interconnect and the second metal interconnect.

Plain-language Overview of Independent Claims:

The provided patent text does not explicitly list the claims in an easily parsable, numbered format for independent claims. However, it describes "a first semiconductor device of the present invention," "a second semiconductor device of the present invention," "a first method for fabricating a semiconductor device," and "a second method for fabricating a semiconductor device" within the Summary of the Invention and Detailed Description sections, which effectively serve as the core independent claims.

First Semiconductor Device (Claim 1 equivalent):
This device includes a semiconductor substrate with a first insulating layer on it, and an interconnect layer within the upper part of the first insulating layer. A second insulating layer is on top of the first insulating layer and the interconnect layer, and a third insulating layer is on the second. At least one conductor contact passes through the second and third insulating layers to reach the interconnect layer. The key features are that the upper part of the interconnect layer has a recess, and the portion of the second insulating layer directly over this interconnect layer is thicker than the part of the second insulating layer over the first insulating layer. This design makes it harder to accidentally expose the interconnect layer during manufacturing processes that could cause corrosion, like ashing or polymer removal.

Second Semiconductor Device (Claim 13 equivalent):
This device also has a semiconductor substrate with a first insulating layer, and an interconnect layer in its upper part. However, this version features an oxidation-resistant conductor film covering the top of the interconnect layer. A second insulating film lies over the first insulating film and the oxidation-resistant conductor film, with a third insulating film on top of that. At least one conductor contact passes through the second and third insulating films to reach the oxidation-resistant conductor film. The presence of the oxidation-resistant conductor film protects the underlying interconnect layer from corrosion during manufacturing processes, even if it becomes exposed.

First Method for Fabricating a Semiconductor Device (Claim 25 equivalent):
This method involves several steps:
(a) forming a first insulating film on a semiconductor substrate;
(b) forming an interconnect layer within the upper part of the first insulating film;
(c) creating a recess in the upper portion of the interconnect layer;
(d) depositing a second insulating film that fills this recess and covers the first insulating film and the interconnect layer;
(e) planarizing the top surface of the second insulating film;
(f) forming a third insulating film on the planarized second insulating film;
(g) using a photoresist mask, partially removing the third and second insulating films above the interconnect layer, ensuring that some of the second insulating film remains on the interconnect layer (thus preventing exposure); and
(h) removing the photoresist.
This method ensures that the interconnect layer remains protected from corrosion during subsequent processing steps like ashing.

Second Method for Fabricating a Semiconductor Device (Claim 33 equivalent):
This method also involves several steps:
(a) forming a first insulating film on a semiconductor substrate;
(b) forming an interconnect layer within the upper part of the first insulating film;
(c) forming an oxidation-resistant conductor film directly on top of the interconnect layer;
(d) depositing a second insulating film over the first insulating film and the oxidation-resistant conductor film;
(e) forming a third insulating film on the second insulating film;
(f) using a photoresist mask, removing portions of the third and second insulating films above the interconnect layer (potentially exposing the oxidation-resistant conductor film); and
(g) removing the photoresist.
This method uses the oxidation-resistant conductor film to prevent corrosion of the underlying interconnect layer even if it is exposed during the photoresist removal and cleaning processes.