US 8198686

Here is a concise summary of US Patent 8,198,686:

US Patent 8,198,686: Summary

• Title: Semiconductor device
• Inventors: Yoshihiro Sato, Hisashi Ogawa
• Current Assignee: Advanced Integrated Circuit Process LLC
• Original Assignee: Panasonic Corp
• Filing Date: 2009-12-02
• Issue Date: 2012-06-12
• Abstract: A semiconductor device is disclosed, featuring first and second metal-insulator-semiconductor field-effect transistors (MISFETs). The first MIS transistor has a first gate insulating film on a first active region and a first gate electrode with a second metal film on the insulating film. An insulating film extends over the side surfaces of the first gate electrode and parts of the first active region. The second MIS transistor includes a second gate insulating film on a second active region and a second gate electrode with a first metal film and a conductive film on the second gate insulating film. The same insulating film extends over the side surfaces of the second gate electrode and parts of the second active region. The first and second metal films are made of different metal materials, and the insulating film is not present on the upper surfaces of either gate electrode. This structure allows for high-precision gate electrode formation and reduction in the isolation region width, enabling further miniaturization of the semiconductor device.

Independent Claims Overview:

1. Claim 1 (Semiconductor Device): This claim describes a semiconductor device comprising a first MIS transistor and a second MIS transistor.

   • The first MIS transistor has a first gate insulating film on a first active region and a first gate electrode composed of a second metal film on the first gate insulating film.
   • The second MIS transistor includes a second gate insulating film on a second active region and a second gate electrode composed of a first metal film on the second gate insulating film, and a conductive film on the first metal film.
   • A single insulating film extends over the side surfaces of both the first and second gate electrodes, and also over the upper surfaces of regions in the active areas located laterally outside these gate electrodes. Crucially, this insulating film is not present on the upper surfaces of the first and second gate electrodes.
   • The first and second metal films are made of different metal materials.

2. Claim 11 (Semiconductor Device Manufacturing Method): This claim outlines a method for manufacturing a semiconductor device, focusing on steps to create the gate structures. The method includes:

   • (a) Forming a first gate electrode formation portion (with a first gate insulating film, a first metal film, and a first silicon film) on a first active region, and a second gate electrode formation portion (with a second gate insulating film, a first metal film, and a second silicon film) on a second active region.
   • (b) Forming an insulating film across the semiconductor substrate, covering both gate electrode formation portions.
   • (c) Removing the insulating film from the top of the first and second gate electrode formation portions to expose the upper surfaces of their respective silicon films.
   • (d) Successively removing the first silicon film and the first metal film from the first gate electrode formation portion to create a first recess (surrounded by the insulating film) on the first active region.
   • (e) Forming a second metal film within this first recess. The first gate electrode of the first MIS transistor is then formed from this second metal film. The second gate electrode of the second MIS transistor includes the first metal film and the second silicon film from the second gate electrode formation portion.

3. Claim 12 (Semiconductor Device Manufacturing Method): This claim is dependent on Claim 11. It further specifies the details of step (d) and (e) from Claim 11.

   • Step (d) involves successively removing the first silicon film, the first metal film, and the first gate insulating film in the first gate electrode formation portion, creating a first recess where the bottom of the first active region is exposed.
   • Step (e) then involves forming a third gate insulating film in this first recess, and subsequently forming the second metal film on top of this third gate insulating film.

CAFC 2026 Dockets:

As of April 26, 2026, there are no entries for US patent 8,198,686 in the CAFC 2026 dockets. However, there are records of other litigation activities, including:

• PTAB case IPR2025-01091 filed (Not Instituted - Procedural)
• PTAB case IPR2025-00682 filed (Not Instituted - Procedural)
• US case filed in Texas Eastern District Court (2:24-cv-00730)
• US case filed in Texas Eastern District Court (2:24-cv-00623)