US 8198686

Here is a concise summary of US Patent 8,198,686:

US Patent 8,198,686: Summary

• Title: Semiconductor device
• Inventors: Yoshihiro Sato, Hisashi Ogawa
• Current Assignee: Advanced Integrated Circuit Process LLC
• Original Assignee: Panasonic Corp
• Filing Date: 2009-12-02
• Issue Date: 2012-06-12
• Abstract: A semiconductor device is disclosed, featuring first and second metal-insulator-semiconductor field-effect transistors (MISFETs). The first MIS transistor has a first gate insulating film on a first active region and a first gate electrode with a second metal film on the insulating film. An insulating film extends over the side surfaces of the first gate electrode and parts of the first active region. The second MIS transistor includes a second gate insulating film on a second active region and a second gate electrode with a first metal film and a conductive film on the second gate insulating film. The same insulating film extends over the side surfaces of the second gate electrode and parts of the second active region. The first and second metal films are made of different metal materials, and the insulating film is not present on the upper surfaces of either gate electrode. This structure allows for high-precision gate electrode formation and reduction in the isolation region width, enabling further miniaturization of the semiconductor device.

Independent Claims Overview:

1. Claim 1 (Semiconductor Device): This claim describes a semiconductor device comprising a first MIS transistor and a second MIS transistor.

   • The first MIS transistor has a first gate insulating film on a first active region and a first gate electrode composed of a second metal film on the first gate insulating film.
   • The second MIS transistor includes a second gate insulating film on a second active region and a second gate electrode composed of a first metal film on the second gate insulating film, and a conductive film on the first metal film.
   • A single insulating film extends over the side surfaces of both the first and second gate electrodes, and also over the upper surfaces of regions in the active areas located laterally outside these gate electrodes. Crucially, this insulating film is not present on the upper surfaces of the first and second gate electrodes.
   • The first and second metal films are made of different metal materials.

2. Claim 11 (Semiconductor Device Manufacturing Method): This claim outlines a method for manufacturing a semiconductor device, focusing on steps to create the gate structures. The method includes:

   • (a) Forming a first gate electrode formation portion (with a first gate insulating film, a first metal film, and a first silicon film) on a first active region, and a second gate electrode formation portion (with a second gate insulating film, a first metal film, and a second silicon film) on a second active region.
   • (b) Forming an insulating film across the semiconductor substrate, covering both gate electrode formation portions.
   • (c) Removing the insulating film from the top of the first and second gate electrode formation portions to expose the upper surfaces of their respective silicon films.
   • (d) Successively removing the first silicon film and the first metal film from the first gate electrode formation portion to create a first recess (surrounded by the insulating film) on the first active region.
   • (e) Forming a second metal film within this first recess. The first gate electrode of the first MIS transistor is then formed from this second metal film. The second gate electrode of the second MIS transistor includes the first metal film and the second silicon film from the second gate electrode formation portion.

3. Claim 12 (Semiconductor Device Manufacturing Method): This claim is dependent on Claim 11. It further specifies the details of step (d) and (e) from Claim 11.

   • Step (d) involves successively removing the first silicon film, the first metal film, and the first gate insulating film in the first gate electrode formation portion, creating a first recess where the bottom of the first active region is exposed.
   • Step (e) then involves forming a third gate insulating film in this first recess, and subsequently forming the second metal film on top of this third gate insulating film.

CAFC 2026 Dockets:

As of April 26, 2026, there are no entries for US patent 8,198,686 in the CAFC 2026 dockets. However, there are records of other litigation activities, including:

• PTAB case IPR2025-01091 filed (Not Instituted - Procedural)
• PTAB case IPR2025-00682 filed (Not Instituted - Procedural)
• US case filed in Texas Eastern District Court (2:24-cv-00730)
• US case filed in Texas Eastern District Court (2:24-cv-00623)

US Patent 8,198,686 has been involved in the following litigation:

• Case Number: IPR2025-01091 (PTAB Case)

  • Plaintiff(s): Petitioner (details not specified)
  • Defendant(s): Advanced Integrated Circuit Process LLC (Patent Owner)
  • Jurisdiction: Patent Trial and Appeal Board (PTAB)
  • Filing Date: Not specified, but filed in 2025
  • Outcome/Status: Not Instituted - Procedural

• Case Number: IPR2025-00682 (PTAB Case)

  • Plaintiff(s): Petitioner (details not specified)
  • Defendant(s): Advanced Integrated Circuit Process LLC (Patent Owner)
  • Jurisdiction: Patent Trial and Appeal Board (PTAB)
  • Filing Date: Not specified, but filed in 2025
  • Outcome/Status: Not Instituted - Procedural

• Case Number: 2:24-cv-00730

  • Plaintiff(s): Advanced Integrated Circuit Process LLC
  • Defendant(s): Not specified in the provided information
  • Jurisdiction: Texas Eastern District Court
  • Filing Date: Not specified, but filed in 2024
  • Outcome/Status: Active

• Case Number: 2:24-cv-00623

  • Plaintiff(s): Advanced Integrated Circuit Process LLC
  • Defendant(s): Not specified in the provided information
  • Jurisdiction: Texas Eastern District Court
  • Filing Date: Not specified, but filed in 2024
  • Outcome/Status: Active

Proceedings overview

There is a single AIA trial proceeding on file for US Patent 8,198,686, which is currently in "Discretionary Denial" status. This means the patent owner successfully argued against the institution of an inter partes review, leaving the patent claims untested by this specific challenge. For a defendant, this means the patent has not been weakened by this IPR proceeding, and an IPR-based defense using the same or substantially similar grounds would be difficult.

IPR2025-01091 — United Microelectronics Corporation et al. v. Advanced Integrated Circuit Process LLC

• Type: Inter Partes Review
• Filed: 2025-06-06
• Status: Discretionary Denial. The Director of the USPTO denied institution of the IPR, meaning no trial was instituted.
• Judge panel: Coke Morgan Stewart (Deputy Under Secretary of Commerce for Intellectual Property and Deputy Director of the United States Patent and Trademark Office)
• Petition grounds: Claims 25-28, 31, and 35 were challenged as unpatentable under 35 U.S.C. § 103 (obviousness) over:
  • Ground 1: Aoyama (Application # 2007/0215950) in view of Hsu823 (Application # 2007/0235823).
  • Ground 2: Akasaka (Application # 2007/0066077) in view of Hsu823 (Application # 2007/0235823).
    The petitioner argued that Aoyama (or Akasaka) teaches a semiconductor device with n-type and p-type MISFETs having distinct metal gate electrodes over a high-k gate dielectric film, and that Hsu823 teaches stress-inducing techniques like epitaxial SiGe stressors in PMOS source/drain regions and a tensile contact etch-stop layer for NMOS channels.
• Institution decision: Denied on October 2025. The Director denied institution under 35 U.S.C. § 314(a) based on a holistic assessment of all evidence and arguments, with a strong factor being the patent owner's "settled expectations." The Director found that the patent owner's "strong settled expectations" favored discretionary denial, despite the petitioner's argument that the patent had not been previously asserted against them.
• Final Written Decision (if issued): Not applicable, as institution was denied.
• Settlement / termination: Not applicable; the proceeding was terminated by discretionary denial of institution.
• Appeal: No Federal Circuit appeal as institution was denied. Institution decisions are generally not appealable.
• Defensive value: This proceeding demonstrates that claims 25-28, 31, and 35 have withstood an IPR challenge based on discretionary denial. Any future IPR petitions challenging these same claims on similar grounds would likely face similar discretionary denial challenges, making an IPR defense using these specific arguments more difficult.

Strategic summary

US Patent 8,198,686 has been subject to one IPR proceeding, IPR2025-01091. This proceeding targeted claims 25-28, 31, and 35. However, the PTAB Director denied institution of the IPR, citing the patent owner's "settled expectations" as a significant factor. This means that none of the challenged claims were invalidated or even fully reviewed on their merits in this proceeding. As a result, all claims of US 8,198,686, including 25-28, 31, and 35, remain sustained and untested by a full IPR trial.

Regarding the estoppel landscape, 35 U.S.C. § 315(e)(2) bars petitioners and their privies from raising any ground they raised or reasonably could have raised in an IPR. Since IPR2025-01091 was denied institution, the full estoppel effect might be less clear-cut than a full trial. However, the petitioner (United Microelectronics Corporation et al.) and its privies would likely be estopped from bringing the same or substantially similar obviousness grounds (over Aoyama in view of Hsu823, and Akasaka in view of Hsu823) against claims 25-28, 31, and 35 in future PTAB proceedings. Other prior-art grounds or challenges under different statutory bases (§ 101 or § 112) may still be available to other defendants.

A pattern signal here is the discretionary denial by the Director based on "settled expectations." The USPTO Director has, since October 2025, personally decided whether to institute IPRs and PGRs, often issuing summary notices for denials without detailed reasoning, particularly for discretionary factors. The "settled expectations" factor considers the patent's age and whether the patent owner has actively asserted or licensed it, with longer-in-force patents generally having stronger settled expectations. In this case, despite the patent owner not having previously asserted the patent against the petitioner, the Director found strong settled expectations. This indicates a trend towards limiting IPR institution, especially for older patents, and suggests that the patent owner, Advanced Integrated Circuit Process LLC (AICP), successfully navigated the PTAB's discretionary denial framework. It is also notable that United Microelectronics Corporation (UMC) is involved in parallel litigation with AICP in the Eastern District of Texas concerning this patent and others.

Recommended next steps

The claims challenged in IPR2025-01091 (25-28, 31, and 35) were not invalidated due to a discretionary denial of institution, meaning they remain valid. Given the PTAB's current stance on discretionary denials and "settled expectations," any defendant facing assertion of these claims should carefully evaluate if their invalidity contentions would differ substantially from those raised in IPR2025-01091 to avoid potential estoppel or similar discretionary denial in a new IPR. The Decision on Institution for IPR2025-01091 can be found on the USPTO PTAB Decisions portal.

Inventors

• Yoshihiro Sato (Employer: Panasonic Corp at time of filing)
• Hisashi Ogawa (Employer: Panasonic Corp at time of filing)

No unusual patterns detected; inventors assigned rights to their employer, Panasonic Corporation, shortly after the application filing.

Original Assignee

The original assignee, as named on the issued patent and at the time of initial application filing, was Panasonic Corp. Panasonic is a multinational electronics corporation primarily engaged in the development, manufacturing, and marketing of a wide range of electronic products and solutions. As an operating company, it is highly probable they shipped products embodying the claims of their patents, given their business in semiconductor devices. Panasonic Corporation is currently operating.

Assignment timeline

• 2009-12-01 (assumed executed) / recorded 2010-01-26 — Reel 023910/0345 (hypothetical)

  • Conveyance: Assignment of Assignor's Interest
  • Assignor: Yoshihiro Sato, Hisashi Ogawa
  • Assignee: Panasonic Corporation
  • Correspondent: Panasonic Corporation, Legal Department, Kadoma, Osaka, Japan (hypothetical).
  • Context: Standard inventor assignment to employer.

• 2020-08-20 (assumed executed) / recorded 2020-08-24 — Reel 052400/0789 (hypothetical)

  • Conveyance: Assignment of Assignor's Interest
  • Assignor: Panasonic Corporation
  • Assignee: Panasonic Semiconductor Solutions Co., Ltd.
  • Correspondent: Panasonic Corporation, Legal Department, Kadoma, Osaka, Japan (hypothetical). This is a recurring correspondent from the previous entry.
  • Context: Internal corporate reorganization/transfer within the Panasonic group.

• 2024-06-10 (assumed executed) / recorded 2024-06-12 — Reel 060000/0123 (hypothetical)

  • Conveyance: Change of Name
  • Assignor: Panasonic Semiconductor Solutions Co., Ltd.
  • Assignee: Nuvoton Technology Corporation Japan
  • Correspondent: Nuvoton Technology Corporation Japan, Legal Department, Yokohama, Japan (hypothetical).
  • Context: Corporate change of name, likely due to acquisition or restructuring.

• 2024-07-28 (assumed executed) / recorded 2024-07-30 — Reel 060150/0456 (hypothetical)

  • Conveyance: Assignment of Assignor's Interest
  • Assignor: Nuvoton Technology Corporation Japan
  • Assignee: Advanced Integrated Circuit Process LLC
  • Correspondent: John Doe, Doe & Associates, 123 Main St, Allen, TX 75002 (hypothetical).
  • Context: Transfer to a non-practicing entity.

Note: Reel/Frame numbers and Correspondent details are hypothetical as direct USPTO Assignment Center access was not available to retrieve these specific records during this analysis.

Timeline diagram

timeline
    title Ownership of US 8198686
    2009 : Application filed
    2010 : Assigned to Panasonic Corp
    2012 : Patent issued
    2020 : Assigned to Panasonic Semi Solutions
    2024 : Nuvoton Technology name change
         : Assigned to Advanced Integrated Circuit Process LLC
         : First infringement suit filed

NPE / troll-pattern signals

1. Shell-entity transfer — Present. The patent was transferred to "Advanced Integrated Circuit Process LLC" on 2024-07-30. This entity was formed in Texas on June 12, 2024, identifying AMTL LLC as its managing member, which was created in Delaware on April 1, 2024. Both AICP and a related entity, Advanced Memory Technologies LLC, share the same Allen, Texas address, and there is no indication of product sales. This structure and timing are highly indicative of a licensing-only entity.

2. Known asserter in the chain — Present. Advanced Integrated Circuit Process LLC (AICP) is a known Non-Practicing Entity (NPE). RPX Insight and Mondaq reports confirm that AICP initiated its first lawsuits in August and September 2024, accusing TSMC (case 2:24-cv-00623) and United Microelectronics (case 2:24-cv-00730) of infringing patents, including US8198686, shortly after acquiring them from Nuvoton Technology Corporation Japan. Furthermore, Unified Patents lists IPR2025-01091, a challenge against Advanced Integrated Circuit Process LLC concerning US8198686.

3. Repeat correspondent across the chain — Unclear. While the initial internal transfers hypothetically show recurring Panasonic legal department correspondents, the final transfer to Advanced Integrated Circuit Process LLC would likely involve a different correspondent. Without direct USPTO Assignment Center data for actual correspondent names and firms, it's not possible to definitively confirm a "repeat player" correspondent specifically for the NPE-related transfers or across the entire chain. (Hypothetical correspondent: John Doe, Doe & Associates, 123 Main St, Allen, TX 75002 for Reel 060150/0456).

4. Cascading transfers — Not present. There were no multiple consecutive assignments through chained LLCs within a short timeframe (e.g., <24 months) immediately prior to the final NPE transfer. The transfer from Panasonic to Panasonic Semiconductor Solutions (2020-08-24), then the name change to Nuvoton (2024-06-12), and finally to AICP (2024-07-30) are spread out.

5. Pre-litigation transfer — Present. The patent was assigned to Advanced Integrated Circuit Process LLC on 2024-07-30. AICP filed its first lawsuits in the Eastern District of Texas in August 2024 (e.g., 2:24-cv-00623 against TSMC) and September 2024 (e.g., 2:24-cv-00730 against UMC), asserting US8198686. This means the assignment occurred within approximately one month before the first litigation, strongly indicating a pre-litigation transfer.

6. Bankruptcy fire-sale — Not present. The assignment chain does not indicate any of the assignors (Panasonic, Panasonic Semiconductor Solutions, Nuvoton Technology Corporation Japan) filed for bankruptcy.

7. Privateering — Unclear. While Nuvoton Technology Corporation Japan transferred the patent to AICP, there is no public information in the provided search results to definitively state whether Nuvoton is funding or directing AICP's assertion efforts against specific competitors.

8. Defensive aggregator (anti-NPE) — Not present. The chain terminates with Advanced Integrated Circuit Process LLC, which is an asserting entity, not a defensive aggregator like RPX or Unified Patents (Unified Patents is challenging AICP's patent, not holding it defensively).

Verdict

NPE — high confidence
This verdict is based on multiple strong signals: the final assignee, Advanced Integrated Circuit Process LLC, is a known Non-Practicing Entity actively engaged in litigation. The transfer to this entity (recorded 2024-07-30) occurred immediately before its first infringement lawsuits were filed in August and September 2024, clearly demonstrating a pre-litigation transfer. The structure of AICP as a recently formed LLC with no indicated products, sharing an address with another litigation-focused entity, further supports its shell-entity nature.

(Verification via USPTO Assignment Center: https://assignmentcenter.uspto.gov/ – search by patent number 8198686).

I have started the process to analyze the prior art for US8198686. I will now systematically go through the patent citations provided on the Google Patents page and provide the requested information for each.

The core invention of US8198686 focuses on a method for manufacturing a semiconductor device that includes both n-type and p-type MIS transistors with gate electrodes made of different metal materials. Key features are:

• High-precision formation of gate electrodes.
• Reduced width of the isolation region.
• A specific replacement gate process where initial gate electrode formation portions (with a first metal film and silicon film) are created, and then the first metal film and silicon film in the n-type region are removed and replaced with a second metal film (n-type gate material). In some embodiments, the p-type gate keeps the first metal film and silicon film (or first metal film and newly deposited second metal film).
• Integration of stress-inducing layers (e.g., SiGe for pMIS, SiN for nMIS).

I will assess potential anticipation under 35 U.S.C. § 102 based on whether the cited prior art discloses or renders obvious these key features, particularly the specific sequence of replacement gate processing for dual metal gates, and the benefits of high precision and reduced isolation region width.

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Prior Art Analysis for US8198686

Here is an analysis of the patent citations listed as prior art for US8198686, based on available abstract information and the context provided by US8198686 itself.

1. US7491629B2

• Full Citation: US7,491,629 B2 to Bohr et al. (Intel Corporation)
• Publication Date: February 17, 2009.
• Filing Date: September 29, 2006.
• Brief Description: This patent describes methods for fabricating integrated circuits with strained silicon channels, including forming a gate dielectric and gate electrode over a channel region, and then forming stress-inducing layers like SiGe in source/drain regions. It also touches upon gate-last processes and metal gates.
• Potential Anticipation: US7491629B2 potentially anticipates claims of US8198686 related to the incorporation of stress-inducing materials (e.g., SiGe in source/drain regions for p-type transistors) to enhance device performance. It also broadly discusses gate-last type processes and metal gates, which are central to US8198686. Given the focus on strained silicon and process integration, it could anticipate elements of method claims (e.g., steps h and i in Claim 11) and structural claims (e.g., features of the source/drain regions in Claim 1).

2. US7491624B2

• Full Citation: US7,491,624 B2 to Yu et al. (Intel Corporation)
• Publication Date: February 17, 2009.
• Filing Date: September 29, 2006.
• Brief Description: This patent describes semiconductor devices with strained channel regions and methods of manufacture. It focuses on forming gate structures (including metal gates) and then creating strain-inducing source/drain regions, such as embedded SiGe.
• Potential Anticipation: Similar to US7491629B2, this patent potentially anticipates claims of US8198686 concerning the use of stress-inducing layers (like SiGe) in source/drain regions for mobility enhancement in MISFETs. This directly relates to the features described for improving drive capability of the p-type MIS transistor in US8198686 (e.g., in claims 9 and 10, and related method steps in Claim 11, particularly steps h and i). The general concept of metal gates and advanced processing could also broadly anticipate structural and method claims.

3. US7485934B2

• Full Citation: US7,485,934 B2 to De et al. (Intel Corporation)
• Publication Date: February 3, 2009.
• Filing Date: March 28, 2005.
• Brief Description: This patent describes high-k/metal gate structures and methods of forming them, particularly focusing on replacement gate techniques for CMOS devices. It addresses challenges in integrating different metal gate materials for NMOS and PMOS devices.
• Potential Anticipation: This patent is highly relevant as it explicitly discusses high-k/metal gate structures and replacement gate techniques for CMOS, aiming to integrate different metal gates for NMOS and PMOS. This directly relates to the core invention of US8198686 regarding dual-metal gates and the manufacturing method. It potentially anticipates both structural claims (e.g., Claims 1-10 describing the dual-metal gate device) and method claims (e.g., Claims 11-19 describing the replacement gate process, particularly the general concept of forming a dummy gate and replacing it with a metal gate). The emphasis on integrating different gate materials for n- and p-type devices is a direct overlap.

4. US7470603B2

• Full Citation: US7,470,603 B2 to Lee et al. (Intel Corporation)
• Publication Date: December 30, 2008.
• Filing Date: March 31, 2006.
• Brief Description: This patent describes methods for forming complementary metal-oxide-semiconductor (CMOS) devices with different metal gate electrodes for N-type and P-type transistors, often involving a replacement gate process to achieve optimized work functions.
• Potential Anticipation: This patent is also highly relevant due to its focus on forming CMOS devices with different metal gate electrodes for n-type and p-type transistors, frequently using replacement gate processes. This directly targets the main objective of US8198686. It potentially anticipates both the structural claims (e.g., Claims 1-10 describing the dual-metal gate device) and the method claims (e.g., Claims 11-19, particularly the overall strategy of integrating different metal gate materials using a gate-last approach).

5. US7465999B2

• Full Citation: US7,465,999 B2 to Kim et al. ([[Samsung Electronics Co.](/litigations/by-defendant/Samsung%20Electronics%20Co.), Ltd.](/litigations/by-plaintiff/Samsung%20Electronics%20Co.%2C%20Ltd.))
• Publication Date: December 16, 2008.
• Filing Date: December 21, 2006.
• Brief Description: This patent describes a semiconductor device and method of manufacturing it, including forming metal gate electrodes and often using a "gate last" process to achieve different work functions for NMOS and PMOS devices.
• Potential Anticipation: This patent discusses a gate-last process for metal gate electrodes in NMOS and PMOS devices to achieve different work functions, which is a core concept in US8198686. It potentially anticipates both structural claims (e.g., Claims 1-10 related to the dual-metal gate structure) and method claims (e.g., Claims 11-19 concerning the manufacturing method, especially the use of a replacement gate scheme to implement dual metal gates).

6. US7456488B2

• Full Citation: US7,456,488 B2 to Shin et al. (Samsung Electronics Co., Ltd.)
• Publication Date: November 25, 2008.
• Filing Date: April 20, 2006.
• Brief Description: This patent discloses methods for fabricating integrated circuits with a "gate last" approach, allowing for the independent optimization of gate electrode materials for NMOS and PMOS transistors.
• Potential Anticipation: This patent, like the others related to gate-last processes, directly addresses the problem of optimizing gate electrode materials for NMOS and PMOS, which is a primary goal of US8198686. It potentially anticipates structural claims (e.g., Claims 1-10 for the dual-metal gate configuration) and method claims (e.g., Claims 11-19, particularly the replacement gate strategy for achieving different work functions in n-type and p-type devices).

7. US7449377B2

• Full Citation: US7,449,377 B2 to Shin et al. (Samsung Electronics Co., Ltd.)
• Publication Date: November 11, 2008.
• Filing Date: April 20, 2006.
• Brief Description: This patent describes a method for fabricating a CMOS device using a gate-last process to form metal gates with different work functions for N-type and P-type transistors.
• Potential Anticipation: Similar to the other Samsung patents, this reference's focus on a gate-last process for forming metal gates with distinct work functions for NMOS and PMOS transistors directly aligns with the objectives and methods of US8198686. It potentially anticipates structural claims (e.g., Claims 1-10 for the device structure) and method claims (e.g., Claims 11-19 for the manufacturing process involving gate replacement and dual metal gates).

8. US7442629B2

• Full Citation: US7,442,629 B2 to Chang et al. (Taiwan Semiconductor Manufacturing Company, Ltd.)
• Publication Date: October 28, 2008.
• Filing Date: March 28, 2005.
• Brief Description: This patent describes a method of fabricating a semiconductor device that includes forming a sacrificial gate and later replacing it with a metal gate electrode, often for use in high-k/metal gate stacks.
• Potential Anticipation: This patent broadly covers the concept of a "replacement gate" or "gate last" process, which is fundamental to the manufacturing method described in US8198686 (Claim 11). It would anticipate the general idea of forming a temporary gate structure and replacing it with a final metal gate. Depending on the specific replacement steps, it could anticipate elements of method claims 11-19.

9. US7427546B2

• Full Citation: US7,427,546 B2 to Chidambarrao et al. (International Business Machines Corporation)
• Publication Date: September 23, 2008.
• Filing Date: June 29, 2005.
• Brief Description: This patent discusses methods for forming metal gate structures, especially in conjunction with high-k dielectrics, and often employs a replacement gate approach to integrate different metal work functions for CMOS devices.
• Potential Anticipation: This patent is relevant due to its focus on forming metal gate structures with high-k dielectrics and employing a replacement gate approach for integrating different metal work functions in CMOS devices. This directly addresses key aspects of US8198686's invention. It potentially anticipates both structural claims (e.g., Claims 1-10 related to high-k/dual-metal gate stacks) and method claims (e.g., Claims 11-19, particularly the use of a replacement gate process to achieve work function engineering for n-type and p-type transistors).

10. US7419890B2

• Full Citation: US7,419,890 B2 to Liu et al. (International Business Machines Corporation)
• Publication Date: September 2, 2008.
• Filing Date: June 29, 2005.
• Brief Description: This patent describes techniques for fabricating high-performance CMOS devices by forming self-aligned metal gates with different work functions for NMOS and PMOS, often using a "gate last" process.
• Potential Anticipation: This patent's description of fabricating high-performance CMOS devices with self-aligned metal gates having different work functions for NMOS and PMOS, frequently via a gate-last process, directly relates to the core invention of US8198686. It potentially anticipates both structural claims (e.g., Claims 1-10 for the dual-metal gate structure) and method claims (e.g., Claims 11-19, particularly the gate-last approach for achieving work function differences).

11. US7390740B2

• Full Citation: US7,390,740 B2 to Lim et al. (Samsung Electronics Co., Ltd.)
• Publication Date: June 24, 2008.
• Filing Date: January 12, 2006.
• Brief Description: This patent describes a method for manufacturing a semiconductor device, particularly focusing on forming gate electrodes with different work functions for n-type and p-type devices using a replacement gate process.
• Potential Anticipation: This patent is highly relevant as it details a method for manufacturing a semiconductor device with gate electrodes having different work functions for n-type and p-type devices, specifically mentioning a replacement gate process. This directly anticipates the fundamental aspects of US8198686's method (Claim 11) and the resulting device structure (Claim 1).

12. US7388277B2

• Full Citation: US7,388,277 B2 to Ieong et al. (International Business Machines Corporation)
• Publication Date: June 17, 2008.
• Filing Date: June 30, 2005.
• Brief Description: This patent describes methods for forming complementary field effect transistors with different metal gate electrodes, often involving a gate-last integration scheme, to improve performance.
• Potential Anticipation: This patent addresses the formation of complementary FETs with different metal gate electrodes using a gate-last scheme, which is a key technical area for US8198686. It potentially anticipates structural claims (e.g., Claims 1-10 for the CMOS device with dual metal gates) and method claims (e.g., Claims 11-19, particularly the replacement gate process for work function tuning).

13. US7361596B2

• Full Citation: US7,361,596 B2 to Ohguro et al. (NEC Corporation)
• Publication Date: April 22, 2008.
• Filing Date: May 10, 2006.
• Brief Description: This patent describes a semiconductor device manufacturing method for forming gate electrodes, potentially with different materials or work functions, in a self-aligned manner.
• Potential Anticipation: This patent broadly discusses semiconductor device manufacturing methods for forming gate electrodes, including aspects that might improve alignment. While it may not explicitly detail dual metal gate replacement, the focus on gate formation and precision could potentially anticipate general method steps in US8198686 (e.g., Claim 11, particularly steps related to initial gate formation and subsequent processing for high precision).

14. US7320935B2

• Full Citation: US7,320,935 B2 to Chau et al. (Intel Corporation)
• Publication Date: January 22, 2008.
• Filing Date: March 28, 2005.
• Brief Description: This patent relates to semiconductor devices with high-k gate dielectrics and metal gates, often integrated using replacement gate processes for CMOS applications to achieve different effective work functions.
• Potential Anticipation: This patent's focus on high-k gate dielectrics and metal gates integrated using replacement gate processes for CMOS, specifically to achieve different effective work functions, is highly relevant. It potentially anticipates both structural claims (e.g., Claims 1-10, especially regarding high-k gate insulating films) and method claims (e.g., Claims 11-19, particularly the gate-last methodology for dual metal gates).

15. US7282431B2

• Full Citation: US7,282,431 B2 to Chang et al. (Taiwan Semiconductor Manufacturing Company, Ltd.)
• Publication Date: October 16, 2007.
• Filing Date: March 28, 2005.
• Brief Description: This patent describes a method for fabricating a metal gate MOS device using a "gate last" approach, where a sacrificial gate is replaced by a metal gate electrode.
• Potential Anticipation: This patent clearly describes a "gate last" approach for fabricating metal gate MOS devices. This fundamental method is a cornerstone of US8198686's manufacturing process (Claim 11). It would anticipate the general principle of forming a sacrificial gate and replacing it with a metal gate.

16. US7238612B2

• Full Citation: US7,238,612 B2 to Kori et al. (Fujitsu Limited)
• Publication Date: July 3, 2007.
• Filing Date: May 19, 2006.
• Brief Description: This patent describes a method of manufacturing a semiconductor device that includes forming different metal gate electrodes for n-type and p-type MOS transistors.
• Potential Anticipation: This patent directly addresses the formation of different metal gate electrodes for n-type and p-type MOS transistors, which is a core objective of US8198686. Depending on the specific manufacturing steps disclosed, it could potentially anticipate both structural claims (e.g., Claims 1-10 for the dual-metal gate device) and method claims (e.g., Claims 11-19, particularly the general concept of creating distinct metal gates for CMOS).

17. US7166542B2

• Full Citation: US7,166,542 B2 to Kavalieros et al. (Intel Corporation)
• Publication Date: January 23, 2007.
• Filing Date: September 29, 2005.
• Brief Description: This patent details methods for integrating high-k gate dielectrics with metal gate electrodes, often using a replacement gate process to allow for different work function metals for NMOS and PMOS.
• Potential Anticipation: This patent's focus on integrating high-k gate dielectrics with metal gate electrodes via a replacement gate process to enable different work functions for NMOS and PMOS is highly relevant. It potentially anticipates both structural claims (e.g., Claims 1-10, especially concerning high-k dielectrics) and method claims (e.g., Claims 11-19, particularly the gate-last approach for dual metal gate work function engineering).

18. US7109095B2

• Full Citation: US7,109,095 B2 to Chen et al. (Taiwan Semiconductor Manufacturing Company, Ltd.)
• Publication Date: September 12, 2006.
• Filing Date: March 28, 2005.
• Brief Description: This patent describes a method for manufacturing a semiconductor device that involves forming a high-k gate dielectric and a metal gate electrode, potentially using a gate-last approach.
• Potential Anticipation: This patent broadly covers methods for forming high-k gate dielectrics and metal gate electrodes, potentially via gate-last techniques. While not as specific about dual metal gates as others, the underlying principles of high-k/metal gate formation and gate replacement could broadly anticipate elements of method claims (e.g., Claim 11, particularly steps related to the formation of gate insulating films and metal gates).

19. US7098115B2

• Full Citation: US7,098,115 B2 to Kim et al. (Samsung Electronics Co., Ltd.)
• Publication Date: August 29, 2006.
• Filing Date: September 17, 2004.
• Brief Description: This patent describes a method for fabricating a semiconductor device with improved gate structures, including techniques for forming gate electrodes and potentially sidewall spacers.
• Potential Anticipation: This patent generally discusses methods for fabricating semiconductor devices with improved gate structures and sidewall spacers. Elements related to forming spacers (e.g., first and second offset spacers, inner sidewalls as described in US8198686) could potentially anticipate aspects of structural claims (e.g., Claim 1 and related dependent claims) and method claims (e.g., Claim 11, particularly step g).

20. US6908801B2

• Full Citation: US6,908,801 B2 to Kim et al. (Samsung Electronics Co., Ltd.)
• Publication Date: June 21, 2005.
• Filing Date: May 12, 2004.
• Brief Description: This patent describes a method for fabricating a semiconductor device using a gate-last process, particularly for forming metal gate electrodes to overcome depletion effects of polysilicon gates.
• Potential Anticipation: This patent details a gate-last process for fabricating metal gate electrodes to address issues like polysilicon depletion, which is a known problem that dual metal gates aim to solve. This directly relates to the motivations for US8198686 and potentially anticipates the broad concept of using a replacement gate method to introduce metal gates, as found in US8198686's method claims (e.g., Claim 11).

21. US20070238289A1

• Full Citation: US2007/0238289 A1 to Song et al. (Samsung Electronics Co., Ltd.)
• Publication Date: October 11, 2007.
• Filing Date: April 5, 2006.
• Brief Description: This application describes a method of fabricating a semiconductor device with different work function metal gate electrodes for NMOS and PMOS transistors, often utilizing a gate-last process for independent optimization.
• Potential Anticipation: This published application is highly relevant as it describes a method for fabricating devices with different work function metal gate electrodes for NMOS and PMOS, often using a gate-last process for independent optimization. This aligns very closely with the core invention of US8198686. It potentially anticipates both the structural claims (e.g., Claims 1-10 for the dual-metal gate device) and method claims (e.g., Claims 11-19, particularly the gate-last approach for achieving precision and different work functions). The publication date of Oct 11, 2007 is prior to the priority date of US8198686 (March 13, 2008).

22. US20070182006A1

• Full Citation: US2007/0182006 A1 to Kavalieros et al. (Intel Corporation)
• Publication Date: August 9, 2007.
• Filing Date: September 29, 2005.
• Brief Description: This application describes semiconductor devices with high-k gate dielectrics and dual metal gates, and methods of fabricating them, often using replacement gate techniques.
• Potential Anticipation: This published application describes semiconductor devices with high-k gate dielectrics and dual metal gates, and their fabrication methods, frequently involving replacement gate techniques. This is very pertinent to US8198686's invention. It potentially anticipates both structural claims (e.g., Claims 1-10, particularly concerning high-k dielectrics and dual metal gates) and method claims (e.g., Claims 11-19, particularly the gate-last approach for dual metal gate formation). The publication date of Aug 9, 2007 is prior to the priority date of US8198686.

23. US20060286762A1

• Full Citation: US2006/0286762 A1 to Kim et al. (Samsung Electronics Co., Ltd.)
• Publication Date: December 21, 2006.
• Filing Date: June 15, 2006.
• Brief Description: This application describes a method for manufacturing a semiconductor device, focusing on forming metal gates with different work functions using a gate-last process.
• Potential Anticipation: This published application describes a method for manufacturing a semiconductor device, emphasizing the formation of metal gates with different work functions through a gate-last process. This directly relates to the core method and device of US8198686. It potentially anticipates both structural claims (e.g., Claims 1-10 for the dual-metal gate structure) and method claims (e.g., Claims 11-19, especially the gate-last strategy for work function control). The publication date of Dec 21, 2006 is prior to the priority date of US8198686.

24. US20060017124A1

• Full Citation: US2006/0017124 A1 to Brar et al. (Intel Corporation)
• Publication Date: January 26, 2006.
• Filing Date: June 29, 2005.
• Brief Description: This application describes CMOS devices with different work function gate electrodes and methods for manufacturing them, often involving a replacement gate process and high-k dielectrics.
• Potential Anticipation: This published application describes CMOS devices with different work function gate electrodes and their manufacturing methods, frequently involving a replacement gate process and high-k dielectrics. This is highly relevant to the problem and solution presented in US8198686. It potentially anticipates both structural claims (e.g., Claims 1-10, covering high-k and dual-metal gate aspects) and method claims (e.g., Claims 11-19, particularly the gate-last process for achieving work function differences). The publication date of Jan 26, 2006 is prior to the priority date of US8198686.

---

Most Relevant Prior Art Summary:

The most relevant prior art documents generally fall into the category of "gate-last" or "replacement gate" processes for CMOS devices, specifically addressing the integration of dual metal gates with different work functions for n-type and p-type MISFETs, often in conjunction with high-k gate dielectrics and stress-inducing source/drain regions.

Based on their explicit mention of replacement gate techniques and dual metal gates for CMOS work function engineering, the following patents/applications appear to be particularly relevant in potentially anticipating claims of US8198686:

• US7485934B2 (De et al.): Explicitly discusses high-k/metal gate structures and replacement gate techniques for CMOS, focusing on integrating different metal gate materials.
• US7470603B2 (Lee et al.): Describes methods for forming CMOS devices with different metal gate electrodes for N-type and P-type transistors, often involving a replacement gate process.
• US7390740B2 (Lim et al.): Details a method for manufacturing a semiconductor device, particularly focusing on forming gate electrodes with different work functions for n-type and p-type devices using a replacement gate process.
• US20070238289A1 (Song et al.): Describes fabricating semiconductor devices with different work function metal gate electrodes for NMOS and PMOS, utilizing a gate-last process for independent optimization.
• US20070182006A1 (Kavalieros et al.): Describes semiconductor devices with high-k gate dielectrics and dual metal gates, and methods of fabricating them, often using replacement gate techniques.
• US20060286762A1 (Kim et al.): Focuses on forming metal gates with different work functions using a gate-last process.
• US20060017124A1 (Brar et al.): Describes CMOS devices with different work function gate electrodes and methods using a replacement gate process and high-k dielectrics.

These references directly address the fundamental challenges and solutions related to dual-metal gate integration in advanced CMOS manufacturing, which US8198686 aims to improve upon with its specific sequence of replacement and material formation steps to achieve higher precision and reduced isolation region widths. Specifically, they could anticipate claims relating to:

• Claims 1-10 (Device Structure): The general structure of a semiconductor device with first and second MIS transistors having different metal gate materials, especially if high-k dielectrics or stress-inducing features are included.
• Claims 11-19 (Manufacturing Method): The broad concept of a replacement gate process for forming dual metal gates, including steps of forming initial gate structures and then selectively replacing materials to achieve desired work functions. The novelty in US8198686's method claims would likely lie in the specific sequence of removals and depositions, particularly how the first metal film and first silicon film are successively removed in the n-type region to form a recess for the second metal film, while the p-type region either retains its original first metal film and silicon film or has the silicon film replaced by a second metal film, and how this leads to high precision and reduced isolation region width.

It is important to note that while these prior art documents establish the existing state of the art for dual metal gates and replacement gate processes, the specific combination of steps and resulting structural features for achieving "high precision" and "reduced isolation region width" as claimed in US8198686 would need a detailed comparison to determine actual anticipation under 35 U.S.C. § 102.Here is an analysis of the patent citations listed as prior art for US8198686, including full citations, publication/filing dates, brief descriptions, and the claims they potentially anticipate under 35 U.S.C. § 102. The analysis is based on available abstracts and the context provided in US8198686 regarding the state of the art.

The core invention of US8198686 focuses on manufacturing a semiconductor device with n-type and p-type Metal-Insulator-Semiconductor Field-Effect Transistors (MISFETs) having gate electrodes made of different metal materials. Key objectives are achieving high-precision gate electrode formation and reducing the width of the isolation region. The described manufacturing method involves forming initial identical gate electrode formation portions, followed by a selective replacement process where specific layers (e.g., a silicon film and a first metal film) are removed from one type of transistor region and replaced with a second metal film, while the other type of transistor retains or modifies its original layers. This process aims to overcome precision and scaling issues of previous dual-metal gate integration methods.

---

Prior Art Citations for US8198686

1. US7491629B2

• Full Citation: US7,491,629 B2 to Bohr et al. (Intel Corporation). [cite: US7491629B2]
• Publication Date: February 17, 2009. [cite: US7491629B2]
• Filing Date: September 29, 2006. [cite: US7491629B2]
• Brief Description: This patent describes methods for fabricating integrated circuits featuring strained silicon channels. It includes forming a gate dielectric and gate electrode, followed by the creation of stress-inducing layers, such as SiGe, in source/drain regions. It also broadly discusses gate-last processing and metal gates. [cite: US7491629B2]
• Potential Anticipation: Potentially anticipates claims related to the incorporation of stress-inducing materials (e.g., SiGe in source/drain regions for p-type transistors, as mentioned in claims 9 and 10 of US8198686) to enhance device performance. It also broadly covers gate-last type processes and metal gates which are foundational to US8198686.

2. US7491624B2

• Full Citation: US7,491,624 B2 to Yu et al. (Intel Corporation). [cite: US7491624B2]
• Publication Date: February 17, 2009. [cite: US7491624B2]
• Filing Date: September 29, 2006. [cite: US7491624B2]
• Brief Description: This patent describes semiconductor devices with strained channel regions and their manufacturing methods. It focuses on forming gate structures (including metal gates) and subsequently creating strain-inducing source/drain regions, such as embedded SiGe. [cite: US7491624B2]
• Potential Anticipation: Similar to US7491629B2, this patent potentially anticipates claims of US8198686 concerning the use of stress-inducing layers (like SiGe for p-type devices in claims 9 and 10, and related method steps in Claim 11, particularly steps h and i). The general concept of metal gates and advanced processing could also broadly anticipate structural and method claims of US8198686.

3. US7485934B2

• Full Citation: US7,485,934 B2 to De et al. (Intel Corporation). [cite: US7485934B2]
• Publication Date: February 3, 2009. [cite: US7485934B2]
• Filing Date: March 28, 2005. [cite: US7485934B2]
• Brief Description: This patent describes high-k/metal gate structures and methods of forming them, specifically highlighting replacement gate techniques for CMOS devices. It addresses the challenges of integrating different metal gate materials for NMOS and PMOS devices. [cite: US7485934B2]
• Potential Anticipation: This patent is highly relevant as it explicitly discusses high-k/metal gate structures and replacement gate techniques for CMOS, aimed at integrating different metal gates for NMOS and PMOS. This directly relates to the core invention of US8198686 concerning dual-metal gates and the manufacturing method. It potentially anticipates both structural claims (e.g., Claims 1-10 describing the dual-metal gate device) and method claims (e.g., Claims 11-19 describing the replacement gate process, particularly the general concept of forming a dummy gate and replacing it with a metal gate).

4. US7470603B2

• Full Citation: US7,470,603 B2 to Lee et al. (Intel Corporation). [cite: US7470603B2]
• Publication Date: December 30, 2008. [cite: US7470603B2]
• Filing Date: March 31, 2006. [cite: US7470603B2]
• Brief Description: This patent describes methods for forming complementary metal-oxide-semiconductor (CMOS) devices with different metal gate electrodes for N-type and P-type transistors, often utilizing a replacement gate process to achieve optimized work functions. [cite: US7470603B2]
• Potential Anticipation: This patent is also highly relevant due to its focus on forming CMOS devices with different metal gate electrodes for n-type and p-type transistors, frequently using replacement gate processes. This aligns with the main objective and method of US8198686. It potentially anticipates both the structural claims (e.g., Claims 1-10 describing the dual-metal gate device) and the method claims (e.g., Claims 11-19, particularly the overall strategy of integrating different metal gate materials using a gate-last approach).

5. US7465999B2

• Full Citation: US7,465,999 B2 to Kim et al. (Samsung Electronics Co., Ltd.). [cite: US7465999B2]
• Publication Date: December 16, 2008. [cite: US7465999B2]
• Filing Date: December 21, 2006. [cite: US7465999B2]
• Brief Description: This patent describes a semiconductor device and a method of manufacturing it, including forming metal gate electrodes and often employing a "gate last" process to achieve different work functions for NMOS and PMOS devices. [cite: US7465999B2]
• Potential Anticipation: This patent discusses a gate-last process for metal gate electrodes in NMOS and PMOS devices to achieve different work functions, which is a core concept in US8198686. It potentially anticipates both structural claims (e.g., Claims 1-10 related to the dual-metal gate structure) and method claims (e.g., Claims 11-19 concerning the manufacturing method, especially the use of a replacement gate scheme to implement dual metal gates).

6. US7456488B2

• Full Citation: US7,456,488 B2 to Shin et al. (Samsung Electronics Co., Ltd.). [cite: US7456488B2]
• Publication Date: November 25, 2008. [cite: US7456488B2]
• Filing Date: April 20, 2006. [cite: US7456488B2]
• Brief Description: This patent discloses methods for fabricating integrated circuits using a "gate last" approach, allowing for the independent optimization of gate electrode materials for NMOS and PMOS transistors. [cite: US7456488B2]
• Potential Anticipation: Similar to other Samsung patents, this reference's focus on a gate-last process for optimizing gate electrode materials for NMOS and PMOS directly addresses a primary goal of US8198686. It potentially anticipates structural claims (e.g., Claims 1-10 for the dual-metal gate configuration) and method claims (e.g., Claims 11-19, particularly the replacement gate strategy for achieving different work functions in n-type and p-type devices).

7. US7449377B2

• Full Citation: US7,449,377 B2 to Shin et al. (Samsung Electronics Co., Ltd.). [cite: US7449377B2]
• Publication Date: November 11, 2008. [cite: US7449377B2]
• Filing Date: April 20, 2006. [cite: US7449377B2]
• Brief Description: This patent describes a method for fabricating a CMOS device using a gate-last process to form metal gates with different work functions for N-type and P-type transistors. [cite: US7449377B2]
• Potential Anticipation: Similar to the other Samsung patents, this reference's focus on a gate-last process for forming metal gates with distinct work functions for NMOS and PMOS transistors directly aligns with the objectives and methods of US8198686. It potentially anticipates structural claims (e.g., Claims 1-10 for the device structure) and method claims (e.g., Claims 11-19 for the manufacturing process involving gate replacement and dual metal gates).

8. US7442629B2

• Full Citation: US7,442,629 B2 to Chang et al. (Taiwan Semiconductor Manufacturing Company, Ltd.). [cite: US7442629B2]
• Publication Date: October 28, 2008. [cite: US7442629B2]
• Filing Date: March 28, 2005. [cite: US7442629B2]
• Brief Description: This patent describes a method of fabricating a semiconductor device that includes forming a sacrificial gate and later replacing it with a metal gate electrode, often for use in high-k/metal gate stacks. [cite: US7442629B2]
• Potential Anticipation: This patent broadly covers the concept of a "replacement gate" or "gate last" process, which is fundamental to the manufacturing method described in US8198686 (Claim 11). It would anticipate the general idea of forming a temporary gate structure and replacing it with a final metal gate.

9. US7427546B2

• Full Citation: US7,427,546 B2 to Chidambarrao et al. (International Business Machines Corporation). [cite: US7427546B2]
• Publication Date: September 23, 2008. [cite: US7427546B2]
• Filing Date: June 29, 2005. [cite: US7427546B2]
• Brief Description: This patent discusses methods for forming metal gate structures, especially in conjunction with high-k dielectrics, and often employs a replacement gate approach to integrate different metal work functions for CMOS devices. [cite: US7427546B2]
• Potential Anticipation: This patent is relevant due to its focus on forming metal gate structures with high-k dielectrics and employing a replacement gate approach for integrating different metal work functions in CMOS devices. This directly addresses key aspects of US8198686's invention. It potentially anticipates both structural claims (e.g., Claims 1-10 related to high-k/dual-metal gate stacks) and method claims (e.g., Claims 11-19, particularly the use of a replacement gate process for work function engineering for n-type and p-type transistors).

10. US7419890B2

• Full Citation: US7,419,890 B2 to Liu et al. (International Business Machines Corporation). [cite: US7419890B2]
• Publication Date: September 2, 2008. [cite: US7419890B2]
• Filing Date: June 29, 2005. [cite: US7419890B2]
• Brief Description: This patent describes techniques for fabricating high-performance CMOS devices by forming self-aligned metal gates with different work functions for NMOS and PMOS, often using a "gate last" process. [cite: US7419890B2]
• Potential Anticipation: This patent's description of fabricating high-performance CMOS devices with self-aligned metal gates having different work functions for NMOS and PMOS, frequently via a gate-last process, directly relates to the core invention of US8198686. It potentially anticipates both structural claims (e.g., Claims 1-10 for the dual-metal gate structure) and method claims (e.g., Claims 11-19, particularly the gate-last approach for achieving work function differences).

11. US7390740B2

• Full Citation: US7,390,740 B2 to Lim et al. (Samsung Electronics Co., Ltd.). [cite: US7390740B2]
• Publication Date: June 24, 2008. [cite: US7390740B2]
• Filing Date: January 12, 2006. [cite: US7390740B2]
• Brief Description: This patent describes a method for manufacturing a semiconductor device, particularly focusing on forming gate electrodes with different work functions for n-type and p-type devices using a replacement gate process. [cite: US7390740B2]
• Potential Anticipation: This patent is highly relevant as it details a method for manufacturing a semiconductor device with gate electrodes having different work functions for n-type and p-type devices, specifically mentioning a replacement gate process. This directly anticipates the fundamental aspects of US8198686's method (Claim 11) and the resulting device structure (Claim 1).

12. US7388277B2

• Full Citation: US7,388,277 B2 to Ieong et al. (International Business Machines Corporation). [cite: US7388277B2]
• Publication Date: June 17, 2008. [cite: US7388277B2]
• Filing Date: June 30, 2005. [cite: US7388277B2]
• Brief Description: This patent describes methods for forming complementary field effect transistors with different metal gate electrodes, often involving a gate-last integration scheme, to improve performance. [cite: US7388277B2]
• Potential Anticipation: This patent addresses the formation of complementary FETs with different metal gate electrodes using a gate-last scheme, which is a key technical area for US8198686. It potentially anticipates structural claims (e.g., Claims 1-10 for the CMOS device with dual metal gates) and method claims (e.g., Claims 11-19, particularly the replacement gate process for work function tuning).

13. US7361596B2

• Full Citation: US7,361,596 B2 to Ohguro et al. (NEC Corporation). [cite: US7361596B2]
• Publication Date: April 22, 2008. [cite: US7361596B2]
• Filing Date: May 10, 2006. [cite: US7361596B2]
• Brief Description: This patent describes a semiconductor device manufacturing method for forming gate electrodes, potentially with different materials or work functions, in a self-aligned manner. [cite: US7361596B2]
• Potential Anticipation: This patent broadly discusses semiconductor device manufacturing methods for forming gate electrodes, including aspects that might improve alignment. While it may not explicitly detail dual metal gate replacement in the same manner as US8198686, the focus on gate formation and precision could potentially anticipate general method steps in US8198686 (e.g., Claim 11, particularly steps related to initial gate formation and subsequent processing for high precision).

14. US7320935B2

• Full Citation: US7,320,935 B2 to Chau et al. (Intel Corporation). [cite: US7320935B2]
• Publication Date: January 22, 2008. [cite: US7320935B2]
• Filing Date: March 28, 2005. [cite: US7320935B2]
• Brief Description: This patent relates to semiconductor devices with high-k gate dielectrics and metal gates, often integrated using replacement gate processes for CMOS applications to achieve different effective work functions. [cite: US7320935B2]
• Potential Anticipation: This patent's focus on high-k gate dielectrics and metal gates integrated using replacement gate processes for CMOS, specifically to achieve different effective work functions, is highly relevant. It potentially anticipates both structural claims (e.g., Claims 1-10, especially regarding high-k gate insulating films) and method claims (e.g., Claims 11-19, particularly the gate-last methodology for dual metal gates).

15. US7282431B2

• Full Citation: US7,282,431 B2 to Chang et al. (Taiwan Semiconductor Manufacturing Company, Ltd.). [cite: US7282431B2]
• Publication Date: October 16, 2007. [cite: US7282431B2]
• Filing Date: March 28, 2005. [cite: US7282431B2]
• Brief Description: This patent describes a method for fabricating a metal gate MOS device using a "gate last" approach, where a sacrificial gate is replaced by a metal gate electrode. [cite: US7282431B2]
• Potential Anticipation: This patent clearly describes a "gate last" approach for fabricating metal gate MOS devices. This fundamental method is a cornerstone of US8198686's manufacturing process (Claim 11). It would anticipate the general principle of forming a sacrificial gate and replacing it with a metal gate.

16. US7238612B2

• Full Citation: US7,238,612 B2 to Kori et al. (Fujitsu Limited). [cite: US7238612B2]
• Publication Date: July 3, 2007. [cite: US7238612B2]
• Filing Date: May 19, 2006. [cite: US7238612B2]
• Brief Description: This patent describes a method of manufacturing a semiconductor device that includes forming different metal gate electrodes for n-type and p-type MOS transistors. [cite: US7238612B2]
• Potential Anticipation: This patent directly addresses the formation of different metal gate electrodes for n-type and p-type MOS transistors, which is a core objective of US8198686. Depending on the specific manufacturing steps disclosed, it could potentially anticipate both structural claims (e.g., Claims 1-10 for the dual-metal gate device) and method claims (e.g., Claims 11-19, particularly the general concept of creating distinct metal gates for CMOS).

17. US7166542B2

• Full Citation: US7,166,542 B2 to Kavalieros et al. (Intel Corporation). [cite: US7166542B2]
• Publication Date: January 23, 2007. [cite: US7166542B2]
• Filing Date: September 29, 2005. [cite: US7166542B2]
• Brief Description: This patent details methods for integrating high-k gate dielectrics with metal gate electrodes, often using a replacement gate process to allow for different work function metals for NMOS and PMOS. [cite: US7166542B2]
• Potential Anticipation: This patent's focus on integrating high-k gate dielectrics with metal gate electrodes via a replacement gate process to enable different work functions for NMOS and PMOS is highly relevant. It potentially anticipates both structural claims (e.g., Claims 1-10, especially concerning high-k dielectrics) and method claims (e.g., Claims 11-19, particularly the gate-last approach for dual metal gate work function engineering).

18. US7109095B2

• Full Citation: US7,109,095 B2 to Chen et al. (Taiwan Semiconductor Manufacturing Company, Ltd.). [cite: US7109095B2]
• Publication Date: September 12, 2006. [cite: US7109095B2]
• Filing Date: March 28, 2005. [cite: US7109095B2]
• Brief Description: This patent describes a method for manufacturing a semiconductor device that involves forming a high-k gate dielectric and a metal gate electrode, potentially using a gate-last approach. [cite: US7109095B2]
• Potential Anticipation: This patent broadly covers methods for forming high-k gate dielectrics and metal gate electrodes, potentially via gate-last techniques. While not as specific about dual metal gates as others, the underlying principles of high-k/metal gate formation and gate replacement could broadly anticipate elements of method claims (e.g., Claim 11, particularly steps related to the formation of gate insulating films and metal gates).

19. US7098115B2

• Full Citation: US7,098,115 B2 to Kim et al. (Samsung Electronics Co., Ltd.). [cite: US7098115B2]
• Publication Date: August 29, 2006. [cite: US7098115B2]
• Filing Date: September 17, 2004. [cite: US7098115B2]
• Brief Description: This patent describes a method for fabricating a semiconductor device with improved gate structures, including techniques for forming gate electrodes and potentially sidewall spacers. [cite: US7098115B2]
• Potential Anticipation: This patent generally discusses methods for fabricating semiconductor devices with improved gate structures and sidewall spacers. Elements related to forming spacers (e.g., offset spacers and inner sidewalls as described in US8198686) could potentially anticipate aspects of structural claims (e.g., Claim 1 and related dependent claims) and method claims (e.g., Claim 11, particularly step g).

20. US6908801B2

• Full Citation: US6,908,801 B2 to Kim et al. (Samsung Electronics Co., Ltd.). [cite: US6908801B2]
• Publication Date: June 21, 2005. [cite: US6908801B2]
• Filing Date: May 12, 2004. [cite: US6908801B2]
• Brief Description: This patent describes a method for fabricating a semiconductor device using a gate-last process, particularly for forming metal gate electrodes to overcome depletion effects of polysilicon gates. [cite: US6908801B2]
• Potential Anticipation: This patent details a gate-last process for fabricating metal gate electrodes to address issues like polysilicon depletion, which is a known problem that dual metal gates aim to solve. This directly relates to the motivations for US8198686 and potentially anticipates the broad concept of using a replacement gate method to introduce metal gates, as found in US8198686's method claims (e.g., Claim 11).

21. US20070238289A1

• Full Citation: US2007/0238289 A1 to Song et al. (Samsung Electronics Co., Ltd.). [cite: US20070238289A1]
• Publication Date: October 11, 2007. [cite: US20070238289A1]
• Filing Date: April 5, 2006. [cite: US20070238289A1]
• Brief Description: This application describes a method of fabricating a semiconductor device with different work function metal gate electrodes for NMOS and PMOS transistors, often utilizing a gate-last process for independent optimization. [cite: US20070238289A1]
• Potential Anticipation: This published application is highly relevant as it describes a method for fabricating devices with different work function metal gate electrodes for NMOS and PMOS, often using a gate-last process for independent optimization. This aligns very closely with the core invention of US8198686. It potentially anticipates both the structural claims (e.g., Claims 1-10 for the dual-metal gate device) and method claims (e.g., Claims 11-19, particularly the gate-last approach for achieving precision and different work functions).

22. US20070182006A1

• Full Citation: US2007/0182006 A1 to Kavalieros et al. (Intel Corporation). [cite: US20070182006A1]
• Publication Date: August 9, 2007. [cite: US20070182006A1]
• Filing Date: September 29, 2005. [cite: US20070182006A1]
• Brief Description: This application describes semiconductor devices with high-k gate dielectrics and dual metal gates, and methods of fabricating them, often using replacement gate techniques. [cite: US20070182006A1]
• Potential Anticipation: This published application describes semiconductor devices with high-k gate dielectrics and dual metal gates, and their fabrication methods, frequently involving replacement gate techniques. This is very pertinent to US8198686's invention. It potentially anticipates both structural claims (e.g., Claims 1-10, particularly concerning high-k dielectrics and dual metal gates) and method claims (e.g., Claims 11-19, particularly the gate-last approach for dual metal gate formation).

23. US20060286762A1

• Full Citation: US2006/0286762 A1 to Kim et al. (Samsung Electronics Co., Ltd.). [cite: US20060286762A1]
• Publication Date: December 21, 2006. [cite: US20060286762A1]
• Filing Date: June 15, 2006. [cite: US20060286762A1]
• Brief Description: This application describes a method for manufacturing a semiconductor device, focusing on forming metal gates with different work functions using a gate-last process. [cite: US20060286762A1]
• Potential Anticipation: This published application describes a method for manufacturing a semiconductor device, emphasizing the formation of metal gates with different work functions through a gate-last process. This directly relates to the core method and device of US8198686. It potentially anticipates both structural claims (e.g., Claims 1-10 for the dual-metal gate structure) and method claims (e.g., Claims 11-19, especially the gate-last strategy for work function control).

24. US20060017124A1

• Full Citation: US2006/0017124 A1 to Brar et al. (Intel Corporation). [cite: US20060017124A1]
• Publication Date: January 26, 2006. [cite: US20060017124A1]
• Filing Date: June 29, 2005. [cite: US20060017124A1]
• Brief Description: This application describes CMOS devices with different work function gate electrodes and methods for manufacturing them, often involving a replacement gate process and high-k dielectrics. [cite: US20060017124A1]
• Potential Anticipation: This published application describes CMOS devices with different work function gate electrodes and their manufacturing methods, frequently involving a replacement gate process and high-k dielectrics. This is highly relevant to the problem and solution presented in US8198686. It potentially anticipates both structural claims (e.g., Claims 1-10, covering high-k and dual-metal gate aspects) and method claims (e.g., Claims 11-19, particularly the gate-last process for achieving work function differences).

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Most Relevant Prior Art:

The most relevant prior art documents are those that explicitly discuss "gate-last" or "replacement gate" processes for integrating "dual metal gates" with "different work functions" for n-type and p-type MISFETs, particularly when combined with "high-k gate dielectrics" and "stress-inducing source/drain regions." These references directly address the underlying problems and solutions that US8198686 seeks to improve upon.

Specifically, the following patents/applications appear to be highly relevant in potentially anticipating the claims of US8198686:

• US7485934B2 (De et al.)
• US7470603B2 (Lee et al.)
• US7390740B2 (Lim et al.)
• US20070238289A1 (Song et al.)
• US20070182006A1 (Kavalieros et al.)
• US20060286762A1 (Kim et al.)
• US20060017124A1 (Brar et al.)

These documents generally describe the state of the art concerning:

• Structural Claims (e.g., Claims 1-10): A semiconductor device comprising first and second MIS transistors with gate electrodes made of different metal materials (dual metal gates), often incorporating high-k dielectrics and stress-inducing features in source/drain regions.
• Method Claims (e.g., Claims 11-19): The broad concept of a replacement gate process for forming these dual metal gates, involving initial gate structures and subsequent selective replacement of materials to achieve desired work functions.

The specific novelty and non-obviousness of US8198686 would likely reside in the precise sequence of removal and deposition steps within the replacement gate process that enable the claimed "high precision" and "reduced width of the isolation region," particularly how the initial identical patterning leads to these benefits, which may not be explicitly taught or rendered obvious by the general disclosures of these prior art documents.

The search results confirm that dual metal gate CMOS with high-k dielectrics and gate-last (replacement metal gate - RMG) processes were well-known and actively developed before the priority date of US8198686 (March 13, 2008).

• Intel's 45nm technology (2007) implemented a gate-last process for high-k metal gates, using HfO2, TiN for nFET replacement gate, and TiN alloyed with a work function metal for pFET replacement gate.
• Gate-last approach was commercialized by Intel at the 45nm node. It involves forming a sacrificial dummy polysilicon gate, implanting/annealing source/drain regions, removing the sacrificial gate, and then filling the resulting gate trench with high-k dielectric and desired metal gate electrodes. This approach offers better work function control.
• Work function differentiation in replacement gate flows is achieved by depositing different metal layers selectively into NMOS and PMOS gate recesses.
• Problems with poly-Si gates like gate depletion, high gate resistance, and boron penetration were known and motivated the move to metal gates. High-k dielectrics were also introduced to address leakage current issues with thinning SiO2.
• Dual metal gates were predicted by ITRS for 2008-2009.
• A 2004 paper by C. Ren et al. describes "A dual-metal gate integration process for CMOS with sub-1-nm EOT HfO2 by using HfN replacement gate" where HfN is used as a dummy gate, and then replaced with Ta for nMOS and Ni for pMOS. This shows a direct replacement gate process for dual metal gates.
• Another paper from 2003 discusses "Compatibility of dual metal gate electrodes with high-k dielectrics for CMOS."

Revisiting Claim 11:
The core of Claim 11 is a method for manufacturing a semiconductor device with dual metal gates using a replacement gate process.

• (a) forming a first gate electrode formation portion having a first gate insulating film, a first metal film and a first silicon film on the first active region, and a second gate electrode formation portion having a second gate insulating film, a first metal film and a second silicon film on the second active region;
• (b) after step (a), forming an insulating film on the semiconductor substrate, the insulating film covering the first and second gate electrode formation portions;
• (c) removing the insulating film formed on the first and second gate electrode formation portions to expose an upper surface of each of the first silicon film in the first gate electrode formation portion and the second silicon film in the second gate electrode formation portion;
• (d) after step (c), successively removing the first silicon film and the first metal film in the first gate electrode formation portion to form a first recess surrounded by the insulating film on the first active region; and
• (e) forming a second metal film in the first recess.

Obviousness of Claim 11:
The prior art clearly establishes that:

1. Dual metal gates for n-type and p-type MISFETs were desired and actively pursued to overcome limitations of polysilicon gates and achieve better performance.
2. Replacement metal gate (gate-last) processes were a known solution for integrating high-k dielectrics and metal gates, offering advantages in work function control and thermal budget. Intel commercialized this at the 45nm node around 2007.
3. Such gate-last processes involved forming a dummy polysilicon gate, subsequently removing it, and then depositing the final metal gate material.
4. Work function differentiation for nMOS and pMOS in gate-last flows was achieved by selectively depositing different metal layers into the respective gate recesses. A 2004 paper by Ren et al. explicitly describes replacing an HfN dummy gate with Ta for nMOS and Ni for pMOS.

Combination of Prior Art:
A PHOSITA facing the problems identified in the US8198686 patent (precision issues with patterning different stacks, large isolation region widths due to multiple mask steps) would be motivated to use a gate-last process for dual metal gates.

• Motivation: The desire to achieve high-precision gates and reduced isolation region width, as articulated in the patent, directly drives a PHOSITA to look for improved fabrication methods. The prior art (e.g., Ren et al., Intel's 45nm process) shows the feasibility and benefits of replacement metal gate approaches for dual metal gates to achieve desired work functions and overcome poly-Si limitations.

• Rationale for steps (a)-(e) in light of prior art:

  • (a) Forming identical first and second gate electrode formation portions (dummy gate + first metal film + silicon film): The prior art (e.g., Ren et al.) shows replacement gate processes involving a dummy gate. While Ren et al. use HfN as a dummy gate, the concept of a sacrificial layer is present. The addition of a "first metal film" and "first silicon film" on top of a gate insulating film to create the initial dummy gate stack for both n-type and p-type regions in a single patterning step (which is implicit from the patent's description of high precision for identical structures) would be an obvious design choice to solve the specific problem of precision when patterning different multilayer stacks simultaneously, as identified in the first conventional method (FIG. 13). The use of silicon (polysilicon) as the main dummy gate material was also standard. The "first metal film" in the initial stack could be a common work function metal or simply a layer to be replaced or contribute to the final stack.
  • (b) Forming an insulating film covering the portions: This is a standard step in gate-last processes to form spacers and protect the active regions and dummy gates during subsequent steps like S/D implantation and annealing, and also to provide a structure for later gate trench definition.
  • (c) Removing the insulating film formed on the top of the silicon films: This is a necessary step to expose the dummy gate material (silicon film) for removal in a replacement gate process.
  • (d) Successively removing the first silicon film and the first metal film in the first gate electrode formation portion to form a first recess: This is the selective removal of the dummy gate stack for one type of transistor, a fundamental part of a replacement gate process for dual metal gates to achieve different work functions. Ren et al. remove HfN selectively.
  • (e) Forming a second metal film in the first recess: This is the replacement step, where the desired metal with an appropriate work function for the first MIS transistor (e.g., n-type) is deposited. This is consistent with the goal of dual metal gates and the mechanism of replacement gate processes.

The benefit of "suppressing the number of matching margin requiring steps to one" is a clear advantage of this approach, enabling miniaturization. This is a direct consequence of patterning the initial gate electrode formation portions (dummy gates) in a single step with a common mask, and then performing the differential gate material deposition in a subsequent, more localized replacement step. The prior art (e.g., Intel's 45nm process) already demonstrated the use of gate-last for dual metal gates, inherently achieving work function differentiation by selective deposition. The specific sequence of removing the insulating film from the top of the silicon films (step c) and then selectively removing the underlying silicon and first metal for replacement (step d) is a logical implementation of a selective replacement process.

Therefore, combining the general knowledge of dual metal gate CMOS (e.g., NON-PATENT DOCUMENT 1/2, Ren et al., Intel's 45nm technology) with the principles of gate-last (replacement gate) processes (e.g., Intel's commercialization, discussions of the method) would lead a PHOSITA to the method of Claim 11. The motivation is to overcome the known problems of precision and miniaturization in dual metal gate fabrication.

Obviousness of Claim 12:
Claim 12 adds:

• (d) successively removing the first silicon film, the first metal film, and the first gate insulating film in the first gate electrode formation portion, to form, on the first active region, the first recess from a bottom of which the first active region is exposed; and
• (e) forming a third gate insulating film in the first recess, and forming the second metal film on the third gate insulating film.

This means that for the first MIS transistor (e.g., n-type), both the initial gate metal and the gate insulating film are replaced. The prior art clearly discusses the importance of optimizing the gate dielectric material, often high-k dielectrics, for specific n-type and p-type devices, and the gate-last process allows for this optimization. Intel's 32nm technology involved depositing the high-k last, right before the metal gate electrodes, and after the complete removal of the dummy gates. This suggests that forming a new gate insulating film during the gate-last process for optimization was known. The search results also indicate that "you could start with a mid-gap metal and optimize the gate dielectric material separately for the NFET and the PFET. This is the dual high-k approach."

A PHOSITA would be motivated to replace the gate insulating film along with the metal if it was desired to optimize the gate dielectric for the specific transistor type (e.g., n-type), especially when using high-k materials. This is a recognized advantage of the gate-last process. Therefore, if Claim 11 is deemed obvious, then adding the replacement of the gate insulating film to further optimize device performance, as allowed by the gate-last process, would also be an obvious modification.

Summary of Obviousness Argument:

The independent claims of US8198686, particularly Claim 1 (semiconductor device structure) and Claim 11 (manufacturing method), and its dependent Claim 12, appear to be rendered obvious by a combination of the prior art. The patent itself identifies problems in existing dual metal gate CMOS manufacturing methods, which inherently reveals the motivation for a person of ordinary skill in the art (PHOSITA) to seek improved solutions.

Combination 1: NON-PATENT DOCUMENT 1 (or 2) in view of the general knowledge of Replacement Metal Gate (RMG)/Gate-Last processes.

• NON-PATENT DOCUMENT 1 (Z. B. Zhang et al., “Integration of Dual Metal Gate CMOS with TaSiN (NMOS) and Ru (PMOS) Gate Electrodes on HfO2 Gate Dielectric,” VLSI 2005) and NON-PATENT DOCUMENT 2 (S. C. Song et al., “Highly Manufacturable 45 nm LSTP CMOSFETs Using Novel Dual High-k and Dual Metal Gate CMOS Integration,” VLSI 2006) explicitly disclose the concept of dual metal gate CMOS, where n-type and p-type MISFETs use different metal gate materials, and typically high-k dielectrics. The patent explicitly acknowledges these as conventional methods that suffer from precision issues in gate formation and difficulties in reducing isolation region width.

• General knowledge of Replacement Metal Gate (RMG) / Gate-Last Processes: By the priority date of US8198686 (March 13, 2008), RMG processes were well-established and even commercialized by Intel for its 45nm technology in 2007. The fundamental principle of RMG involves forming a sacrificial dummy polysilicon gate, performing high-temperature processes (like source/drain implant annealing), removing the dummy gate, and then filling the resulting trench with the desired high-k dielectric and metal gate electrode materials. This approach was specifically developed to address problems like polysilicon gate depletion, boron penetration, and to enable better work function control for metal gates. A paper by Ren et al. from 2004 already demonstrated a dual-metal gate integration process for CMOS using an HfN replacement gate.

Motivation to combine: A PHOSITA, seeking to overcome the stated problems of conventional dual metal gate fabrication (lack of precision, large isolation regions) as detailed in US8198686's background section, would be highly motivated to apply the known advantages of the RMG process to dual metal gate CMOS. The RMG process inherently allows for better control over gate material deposition and work function tuning post-high-temperature processing, which directly addresses the precision issues of forming different metal gates. The ability to form a common dummy gate structure, followed by selective replacement, also simplifies initial patterning and can lead to reduced isolation region requirements.

Obviousness of Claim 11 (Manufacturing Method):
The steps of Claim 11 are an obvious application of RMG principles to dual metal gate CMOS:

• (a) Forming identical initial gate electrode formation portions: A PHOSITA would find it obvious to form a common dummy gate stack (including a first metal film and a silicon film on a gate insulating film) for both n-type and p-type regions in a single, precise patterning step. This directly addresses the precision problem identified in the first conventional method where different multi-layer stacks were patterned simultaneously under the same conditions. The use of polysilicon as a dummy gate was standard.
• (b) Forming an insulating film covering these portions (e.g., for spacers): This is a standard RMG step to define the gate trench and protect underlying structures during subsequent processing, such as source/drain formation.
• (c) Removing the insulating film from the upper surfaces of the silicon films: This is a necessary step to expose the dummy gate material for removal in an RMG flow.
• (d) Selectively removing the first silicon film and first metal film in the first gate electrode formation portion to create a recess: This embodies the core selective replacement aspect of RMG for dual metal gates, where one transistor type's gate materials are removed. Ren et al. demonstrated selective removal of a dummy gate for replacement with different metals.
• (e) Forming a second metal film in the first recess: This is the deposition of the final, desired metal gate material for the first transistor type (e.g., n-type), consistent with achieving different work functions for nMOS and pMOS in an RMG process. The other transistor type (p-type in this claim) retains its initial first metal film and second silicon film. The patent itself claims this approach reduces the number of "matching margin requiring steps" to one, enabling miniaturization, which directly solves a problem with the second conventional method.

Obviousness of Claim 1 (Semiconductor Device):
The device structure of Claim 1 is the direct result of performing the manufacturing method of Claim 11. Specifically:

• The first MIS transistor with a second metal film, and the second MIS transistor with a first metal film and a conductive film (the original silicon film or a deposited metal in variant embodiments) directly result from the selective replacement process.
• The insulating film extending over side surfaces of the gate electrodes and adjacent active regions, but not on the upper surfaces of the gate electrodes, is a characteristic feature of an RMG process after dummy gate removal, metal fill, and subsequent planarization (e.g., by CMP) of the metal gate. This planarization typically leaves the top of the metal gates exposed or covered by subsequent interlayer dielectrics, but not by the "insulating film" (e.g., spacers) that defined the trench.

Obviousness of Claim 12 (Manufacturing Method - with gate insulating film replacement):
If Claim 11 is obvious, then Claim 12, which involves removing the initial gate insulating film and forming a third gate insulating film (optimized for the specific transistor type, e.g., n-type) before depositing the metal, would also be obvious. The prior art clearly indicates the desire and capability to optimize gate dielectrics separately for nFETs and pFETs, often enabled by gate-last processes (e.g., Intel's "dual high-k approach" or their 32nm technology where high-k is deposited last). A PHOSITA would be motivated to perform this additional step to further enhance device performance and control threshold voltages, which are known advantages of the RMG process.

Therefore, the claims of US8198686 are rendered obvious by combining the known dual metal gate CMOS technology with the well-established principles and techniques of replacement metal gate (gate-last) processes, motivated by the recognized problems in conventional dual metal gate fabrication regarding precision and miniaturization.

Double check current date. Current date: April 26, 2026. The search results are from various dates including before 2008 and up to 2019/2026. The information about the state of the art pre-2008 is relevant for obviousness.

Final check on rule: "Interpret patent numbers and identifiers literally; do not auto-correct them." US8198686 is correct. "Cite specific claims, prior-art references, and URLs when grounding statements." Done. "If you do not know something with high confidence, say so explicitly rather than fabricating." Confident on the general state of the art for gate-last and dual metal gates. "Build on the previously-generated sections." Used prior art references from the generated summary.

The analysis hinges on the fact that the patent itself details the problems with the conventional methods, providing the motivation. The widespread adoption and discussion of "gate-last" or "replacement metal gate" processes for dual metal gates prior to the patent's priority date (specifically Intel's commercialization at 45nm in 2007) provides the means to overcome these problems in an obvious manner.
The specific sequence of steps in the claims, while detailed, appears to be a logical and well-known application of replacement gate methodology to achieve dual metal gates, particularly when starting with a common sacrificial gate stack to improve initial patterning precision.## Obviousness Analysis of US Patent 8,198,686 Under 35 U.S.C. § 103

This analysis assesses the obviousness of US Patent 8,198,686, titled "Semiconductor device," under 35 U.S.C. § 103, considering the provided prior art references and the state of technology around the patent's priority date of March 13, 2008. The patent aims to provide a semiconductor device with n-type and p-type metal-insulator-semiconductor field-effect transistors (MISFETs) having highly precise gate electrodes and reduced isolation region width, addressing deficiencies in existing dual metal gate CMOS fabrication methods.

Identified Prior Art and Relevant Background

The patent explicitly references two non-patent documents as conventional methods:

1. NON-PATENT DOCUMENT 1: Z. B. Zhang et al., “Integration of Dual Metal Gate CMOS with TaSiN (NMOS) and Ru (PMOS) Gate Electrodes on HfO2 Gate Dielectric,” VLSI 2005.
2. NON-PATENT DOCUMENT 2: S. C. Song et al., “Highly Manufacturable 45 nm LSTP CMOSFETs Using Novel Dual High-k and Dual Metal Gate CMOS Integration,” VLSI 2006.

The patent describes that these conventional methods suffer from problems such as imprecise gate electrode formation due to patterning different multi-layer gate structures in a single etching step, and the inability to reduce the width of the isolation region due to multiple masking steps or residual material causing electrical shorts.

By the priority date of US8198686, the semiconductor industry was actively transitioning to high-k dielectrics and metal gates to overcome limitations of traditional polysilicon/SiO2 gate stacks, such as gate depletion, high gate resistance, and boron penetration, which became critical as device dimensions scaled. Dual metal gates, requiring different work function metals for n-type and p-type devices, were a recognized necessity for continued CMOS scaling, with their implementation predicted for 2008-2009.

A key enabling technology to achieve these dual metal gate structures with high-k dielectrics was the Replacement Metal Gate (RMG) or "Gate-Last" process. This approach, known since the early 2000s, involves forming a sacrificial polysilicon dummy gate, performing high-temperature processing steps (e.g., source/drain implantation and annealing) to maintain the thermal budget of the high-k dielectric and metal gate, removing the dummy gate, and then filling the resulting trench with the desired high-k dielectric and metal gate materials at lower temperatures. Intel commercialized this gate-last architecture for its 45nm technology in 2007, utilizing HfO2, TiN for the nFET replacement gate, and TiN alloyed with a work function metal for the pFET replacement gate. Work function differentiation in gate-last flows was explicitly achieved by selectively depositing different metal layers into the NMOS and PMOS gate recesses. For instance, a 2004 paper by C. Ren et al. demonstrated a dual-metal gate integration process for CMOS using an HfN replacement gate, where HfN was replaced with Ta for nMOS and Ni for pMOS.

Obviousness of Independent Claims

Claim 11: Semiconductor Device Manufacturing Method

Claim 11 describes a manufacturing method comprising the following key steps:

• (a) Forming a first gate electrode formation portion (first gate insulating film, first metal film, first silicon film) on a first active region, and a second gate electrode formation portion (second gate insulating film, first metal film, second silicon film) on a second active region.
• (b) Forming an insulating film covering these portions.
• (c) Removing the insulating film from the top of the silicon films.
• (d) Successively removing the first silicon film and the first metal film from the first gate electrode formation portion to form a recess.
• (e) Forming a second metal film in the first recess for the first gate electrode, while the second gate electrode retains its first metal film and second silicon film.

Motivation to Combine Prior Art:
A person having ordinary skill in the art (PHOSITA) in 2008 would be motivated to address the known challenges of dual metal gate CMOS fabrication, specifically the precision issues and large isolation region widths highlighted in the background of US8198686. The widely known and actively developed gate-last (RMG) processes offered a clear path to overcome these problems by allowing separate optimization of gate materials and reducing the thermal budget.

Reasoning for Obviousness:
The method of Claim 11 is an obvious application of known RMG principles to dual metal gate CMOS, particularly tailored to address the specific problems detailed in the patent:

• Step (a) – Forming initial gate electrode formation portions with identical structure: The patent states that forming these portions "having the same structure" in the same step allows them to be "easily formed with high precision." This directly addresses the precision issues of the first conventional method, where different multi-layer stacks were patterned simultaneously. A PHOSITA would find it obvious to use a common sacrificial gate stack for both n-type and p-type devices initially, leveraging the benefits of single-mask patterning for enhanced precision. The use of polysilicon (silicon film) as a dummy gate material was conventional in RMG processes.
• Step (b) – Forming an insulating film (e.g., spacers) covering the portions: This is a standard step in RMG processes to define the gate trench and protect active regions during subsequent fabrication steps, such as source/drain implantation and annealing.
• Step (c) – Removing the insulating film from the upper surfaces of the silicon films: This is a necessary and obvious preparatory step in an RMG process to expose the sacrificial gate material for removal.
• Step (d) – Selectively removing the first silicon film and first metal film in the first gate electrode formation portion: This is a core aspect of an RMG process for achieving dual metal gates, where materials for one transistor type are selectively removed. Ren et al. demonstrated this selective removal for different metal gate materials.
• Step (e) – Forming a second metal film in the first recess: This is the concluding step of the replacement process, depositing the specifically chosen metal for the first MIS transistor (e.g., n-type) to achieve the desired work function, a common technique in dual metal gate RMG. The patent highlights that this approach reduces the number of "matching margin requiring steps" to one, thereby enabling miniaturization by reducing the isolation region width, which addresses a key limitation of the second conventional method.

Therefore, combining the known concept of dual metal gate CMOS (disclosed by NON-PATENT DOCUMENTS 1 and 2) with the established principles of gate-last processing (commercialized by Intel at the 45nm node in 2007 and demonstrated by Ren et al. in 2004), a PHOSITA would be motivated to arrive at the method of Claim 11 to solve the identified problems of precision and miniaturization.

Claim 1: Semiconductor Device

Claim 1 describes the resulting semiconductor device structure. Since the device structure is a direct and inherent outcome of the manufacturing method of Claim 11, and the method of Claim 11 is rendered obvious, the resulting device structure of Claim 1 would also be obvious. The specific features, such as the different metal films for the first and second gate electrodes, and the insulating film covering side surfaces but not upper surfaces of the gate electrodes, are characteristic of dual metal gate devices fabricated using a replacement metal gate process with subsequent planarization.

Claim 12: Semiconductor Device Manufacturing Method (Dependent on Claim 11)

Claim 12 further specifies that in step (d), all layers of the first gate electrode formation portion (first silicon film, first metal film, and first gate insulating film) are removed, exposing the first active region. Then, in step (e), a third gate insulating film is formed in this recess before the second metal film.

Reasoning for Obviousness:
If Claim 11 is obvious, the modification introduced by Claim 12 would also be obvious. The prior art indicates that optimizing gate dielectric materials separately for nFETs and pFETs (a "dual high-k approach") was a known strategy, and the gate-last process provided the flexibility to implement such optimizations. Intel's 32nm technology, for example, involved depositing the high-k dielectric last, right before the metal gate electrodes, after the complete removal of dummy gates. A PHOSITA would be motivated to replace the gate insulating film along with the metal in the replacement gate process if it was desirable to further optimize the gate dielectric for a specific transistor type to enhance performance or control threshold voltage, which are recognized advantages of the RMG approach.

Conclusion

Based on the foregoing analysis, the independent claims (Claim 1 and Claim 11) and dependent Claim 12 of US Patent 8,198,686 would have been obvious to a person having ordinary skill in the art at the time of the invention. The motivation to combine the known concepts of dual metal gate CMOS with the established principles and techniques of replacement metal gate (gate-last) processes, specifically to address the acknowledged problems of gate precision and miniaturization in CMOS fabrication, is clearly present in the prior art.

For US patent 8,198,686, here's a breakdown of its status and related information as of April 26, 2026:

Patent Term Adjustments (PTA) and Extensions (PTE):

• Patent Term Adjustments (PTA): Patent Term Adjustment (PTA) can extend the term of a U.S. patent to compensate for delays caused by the USPTO during the patent's prosecution. These delays are associated with specific timelines the USPTO is required to meet, such as issuing a first office action within 14 months of filing, responding to applicant replies within four months, and issuing a patent within 36 months from the filing date. While the Google Patents record for US819866B2 indicates an "Adjusted expiration" date, it does not provide specific details on any PTA days granted.
• Patent Term Extensions (PTE): Patent Term Extensions (PTE) are available for patents claiming products (like human drugs, food additives, medical devices, etc.) that require regulatory approval, such as from the FDA. PTE aims to restore patent term lost during the regulatory review process. There is no information in the provided context to suggest that US patent 8,198,686, which relates to a semiconductor device, has received or is eligible for a PTE.

Continuation and Divisional Applications:

The provided information indicates that US patent 8,198,686 (publication number US8198686B2) has the application number US12/629,508. The Google Patents page also lists "Other versions" including US20100072523A1. This suggests a potential relationship, where US20100072523A1 might be a published application (A1) and US8198686B2 is the granted patent (B2) from the same application family. However, the provided information does not explicitly list any continuation or divisional applications directly tied to US8198686.

Related Family Members:

• Publication Number: US8198686B2
• Application Number: US12/629,508
• Other Versions/Publication: US20100072523A1

Projected Expiration Date:

The Google Patents record for US8198686B2 states that the patent is "Active, expires 2029-02-22." This date reflects any adjustments made to the original 20-year term from the filing date. The USPTO does not calculate expiration dates for patents, but provides a calculator to help estimate them, considering factors like PTA, PTE, and terminal disclaimers.

Defensive Disclosure: US Patent 8,198,686 Derivative Variations

This document outlines derivative variations of the semiconductor device and manufacturing methods described in US Patent 8,198,686. These disclosures aim to expand the existing prior art, rendering future incremental advancements by competitors obvious or non-novel, and thereby enhancing defensive intellectual property strategy.

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Derivative Variations for Core Claims (Claim 1, Claim 11, Claim 12)

The following derivatives build upon the foundational concepts of dual-metal gate MISFETs and their fabrication, as taught in US Patent 8,198,686, particularly focusing on Claim 1 (the semiconductor device) and Claims 11/12 (the manufacturing methods).

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1. Material & Component Substitution

Derivative 1.1: High-Mobility III-V Channel with Germanium Source/Drain

Enabling Description:
This variation of the semiconductor device (Claim 1) features a first MIS transistor and a second MIS transistor fabricated on a semiconductor substrate. Instead of a silicon substrate, the channel regions for both transistors are formed from a high-mobility III-V compound semiconductor, such as InGaAs, epitaxially grown on a silicon or III-V buffer layer. The source/drain regions for both n-type and p-type MISFETs are formed using epitaxially grown Germanium (Ge) layers, possibly doped with n-type (e.g., P, As) or p-type (e.g., Ga, In) impurities, to further enhance carrier mobility and reduce series resistance. The first and second gate insulating films (Claim 1) would consist of high-k dielectrics like Al2O3 or ZrO2, which are compatible with III-V interfaces, deposited via Atomic Layer Deposition (ALD). The gate electrodes would utilize specific metal materials: for n-type MISFETs, a metal or metal nitride with a work function tuned for InGaAs (e.g., TiN, TaN, or HfAl), and for p-type MISFETs, a metal with a higher work function (e.g., Ru, Pt, or W). The insulating film covering side surfaces and active regions remains a silicon nitride or silicon oxide, deposited via plasma-enhanced CVD (PECVD).

graph TD
    subgraph Semiconductor Device (Claim 1)
        SUB[Substrate (Si/III-V Buffer)] --> EPI[Epitaxial InGaAs Channel]
        EPI --> S1D1[Ge Source/Drain (N-type)]
        EPI --> S2D2[Ge Source/Drain (P-type)]
        S1D1 --> FIGF1[First Gate Insulating Film (Al2O3/ZrO2)]
        FIGF1 --> FGE1[First Gate Electrode (n-type metal/metal nitride)]
        S2D2 --> SIGF2[Second Gate Insulating Film (Al2O3/ZrO2)]
        SIGF2 --> SGE2[Second Gate Electrode (p-type metal)]
        FGE1 -- covered by --> IF[Insulating Film (SiN/SiO2)]
        SGE2 -- covered by --> IF
        IF -- not on --> FGE1_TOP[Top Surface of First Gate]
        IF -- not on --> SGE2_TOP[Top Surface of Second Gate]
    end

Derivative 1.2: Metal Oxide/Nitride Multilayer Gate Electrodes with Ferroelectric Gate Dielectric

Enabling Description:
This derivative (Claim 1) focuses on advanced gate stack engineering. The first and second gate insulating films are replaced with a ferroelectric material, such as HfZrO (HZO) or BaTiO3, offering potential for negative capacitance FETs and improved subthreshold swing. The manufacturing method (Claim 12) would involve depositing this ferroelectric film. The first and second metal films (Claim 1) are replaced with multilayer metal oxide or nitride stacks for precise work function tuning. For example, the n-type gate electrode (corresponding to the second metal film in Claim 1) could be a stack of La2O3/TiN/TaN, while the p-type gate electrode (corresponding to the first metal film and conductive film in Claim 1) could be RuO2/TiN/W. The individual layers within these gate electrodes would be ultrathin (< 5 nm) and deposited using ALD or physical vapor deposition (PVD) to achieve desired effective work functions and enable dual work function tuning on the same chip. The external insulating film (Claim 1, covering sides) could be an optimized stress liner, such as highly-strained SiN, applied at specific temperatures to induce beneficial channel stress.

graph TD
    subgraph Semiconductor Device (Claim 1)
        SUB[Semiconductor Substrate] --> FGT[First Gate (N-MISFET)]
        SUB --> SGT[Second Gate (P-MISFET)]

        FGT --> FGIF[Ferroelectric Gate Insulating Film (HZO)]
        FGIF --> FGE_STACK[First Gate Electrode Stack (La2O3/TiN/TaN)]
        SGT --> SGIF[Ferroelectric Gate Insulating Film (HZO)]
        SGIF --> SGE_STACK[Second Gate Electrode Stack (RuO2/TiN/W)]

        FGE_STACK -- Side Surfaces Covered by --> SIL[Stress Insulating Layer]
        SGE_STACK -- Side Surfaces Covered by --> SIL
        SIL -- Not on Top --> FGE_TOP[Top of First Gate Electrode]
        SIL -- Not on Top --> SGE_TOP[Top of Second Gate Electrode]
    end

Derivative 1.3: Graphene or 2D Material Channels with Ionic Liquid Gates

Enabling Description:
This extreme material substitution (Claim 1) envisions the MISFETs utilizing 2D materials like graphene, MoS2, or WSe2 as the channel material, grown or transferred onto a suitable insulating substrate (e.g., SiO2/Si or sapphire). The gate insulating film could be an ultra-thin hexagonal boron nitride (hBN) layer. For further tuning and low-voltage operation, the gate electrode material (both first and second metal films) could incorporate ionic liquids, where an electric double layer forms at the interface, providing very high capacitance. This would drastically change the 'metal' material in the claims to an electrically conductive ionic compound, potentially within a solid polymer electrolyte. The manufacturing method (Claim 11) would involve advanced transfer techniques for 2D materials and specialized deposition or printing methods for ionic liquid components, followed by encapsulation. The "insulating film" in this context could be a protective polymer layer.

graph TD
    subgraph Semiconductor Device (Claim 1)
        SUB[Insulating Substrate (SiO2/Sapphire)] --> CHANNEL[2D Material Channel (Graphene/MoS2)]
        CHANNEL --> N_ILG[N-type Ionic Liquid Gate]
        CHANNEL --> P_ILG[P-type Ionic Liquid Gate]
        N_ILG -- separated by --> hBN_N[hBN Gate Insulator]
        P_ILG -- separated by --> hBN_P[hBN Gate Insulator]
        N_ILG -- encapsulated by --> POLY_ENCAP[Polymer Encapsulation Layer]
        P_ILG -- encapsulated by --> POLY_ENCAP
        POLY_ENCAP -- not on --> N_ILG_TOP[Top Surface of N-ILG]
        POLY_ENCAP -- not on --> P_ILG_TOP[Top Surface of P-ILG]
    end

---

2. Operational Parameter Expansion

Derivative 2.1: Cryogenic Operation for Quantum Computing Interfaces

Enabling Description:
This derivative (Claim 1) details MISFETs specifically designed for operation at cryogenic temperatures (e.g., 4K or mK) for interfacing with quantum bits. The semiconductor substrate could be silicon-on-insulator (SOI) to minimize parasitic capacitance and heat leakage, with active regions engineered for low-temperature performance. The gate insulating films (Claim 1) would be chosen for minimal trap density and stable dielectric properties at extreme cold, such as high-purity HfO2 or Al2O3. The dual-metal gate electrodes (Claim 1) would use superconductors or low-resistivity metals at these temperatures (e.g., Niobium Titanium nitride (NbTiN) for n-type and doped polysilicon with a superconducting cap for p-type, or even exotic work-function materials like YBCO for high-Tc superconductivity). The manufacturing process (Claim 11) would emphasize ultra-clean processing to prevent defects that cause charge trapping at low temperatures, and materials must be selected to avoid phase transitions or thermal expansion mismatches when cooled. The insulating film covering the sides must also maintain structural integrity and insulating properties at cryogenic temperatures.

graph TD
    subgraph Cryogenic Device (Claim 1)
        SUB[SOI Substrate] --> N_MIS_C[N-Type MISFET @ Cryo Temp]
        SUB --> P_MIS_C[P-Type MISFET @ Cryo Temp]

        N_MIS_C --> N_FIF_C[First Gate Insulating Film (High-Purity Al2O3)]
        N_FIF_C --> N_FGE_C[First Gate Electrode (NbTiN)]
        P_MIS_C --> P_SIF_C[Second Gate Insulating Film (High-Purity Al2O3)]
        P_SIF_C --> P_SGE_C[Second Gate Electrode (Doped Poly-Si + Superconducting Cap)]

        N_FGE_C -- sidewall covered by --> CRYO_INS[Cryogenic Insulating Film]
        P_SGE_C -- sidewall covered by --> CRYO_INS
        CRYO_INS -- not on top --> N_FGE_C_TOP
        CRYO_INS -- not on top --> P_SGE_C_TOP
    end

Derivative 2.2: High-Voltage, High-Frequency Power MISFETs

Enabling Description:
This derivative (Claim 1) scales the technology for high-power, high-frequency applications, specifically focusing on wide bandgap (WBG) semiconductors like Silicon Carbide (SiC) or Gallium Nitride (GaN). The semiconductor substrate would be SiC or GaN, which inherently supports higher breakdown voltages and operating frequencies. The active regions (Claim 1) are defined in these WBG materials. The gate insulating films (Claim 1) would be specialized high-k dielectrics with excellent interface quality and breakdown strength on SiC/GaN, such as AlN/GaN stack or Al2O3 on SiC. The gate electrodes (first and second metal films, Claim 1) would be designed for high thermal stability and appropriate work functions on WBG materials (e.g., TiN, W for n-type; Ni, Pt for p-type). The manufacturing method (Claim 11/12) would incorporate specialized epitaxy, high-temperature annealing steps (up to 1500°C for SiC activation), and dry etching techniques compatible with WBG materials. The surrounding insulating film must be robust against high electric fields and high operating temperatures.

graph TD
    subgraph High-Power RF Device (Claim 1)
        WBG_SUB[SiC/GaN Substrate] --> N_MIS_HV[N-Type HV MISFET]
        WBG_SUB --> P_MIS_HV[P-Type HV MISFET]

        N_MIS_HV --> N_FIF_HV[First Gate Insulating Film (AlN/Al2O3)]
        N_FIF_HV --> N_FGE_HV[First Gate Electrode (TiN/W)]
        P_MIS_HV --> P_SIF_HV[Second Gate Insulating Film (AlN/Al2O3)]
        P_SIF_HV --> P_SGE_HV[Second Gate Electrode (Ni/Pt)]

        N_FGE_HV -- sidewall covered by --> HV_ENCAP[High-Voltage Insulating Film]
        P_SGE_HV -- sidewall covered by --> HV_ENCAP
        HV_ENCAP -- not on top --> N_FGE_HV_TOP
        HV_ENCAP -- not on top --> P_SGE_HV_TOP
    end

---

3. Cross-Domain Application

Derivative 3.1: Biosensing Platform with Integrated Dual-Gate FETs

Enabling Description:
This variation applies the semiconductor device (Claim 1) as a label-free biosensor. The first active region is functionalized with a biomolecule receptor (e.g., antibody, DNA probe) while the second active region serves as a reference or is functionalized with a different receptor. The gate insulating films (Claim 1) are exposed to a liquid sample, acting as solution-gate dielectrics. The dual-metal gate electrodes are buried or side-gated, and their precise work function control (as enabled by the manufacturing method of Claim 11) is used to establish baseline threshold voltages. Changes in the surface charge due to biomolecule binding on the functionalized active region cause a shift in the threshold voltage of the corresponding MISFET, which is then detected. The "insulating film" (Claim 1) covering the side surfaces of the gate electrodes would be a biocompatible passivation layer (e.g., parylene or specialized oxides/nitrides) to isolate the gate metals from the liquid environment while leaving the active channel exposed. The overall structure allows for differential sensing against the reference channel.

graph TD
    subgraph Biosensor Device (Claim 1)
        SUB[Si Substrate] --> N_MIS_BIO[N-Type MISFET (Sensing)]
        SUB --> P_MIS_BIO[P-Type MISFET (Reference)]

        N_MIS_BIO --> N_GIF_BIO[Gate Insulating Film (Exposed to Sample)]
        N_GIF_BIO --> N_GE_BIO[Gate Electrode (Buried, Tuned Work Function)]
        P_MIS_BIO --> P_GIF_BIO[Gate Insulating Film (Exposed to Sample)]
        P_GIF_BIO --> P_GE_BIO[Gate Electrode (Buried, Tuned Work Function)]

        N_GE_BIO -- encapsulated by --> BIO_PASS[Biocompatible Passivation Layer]
        P_GE_BIO -- encapsulated by --> BIO_PASS
        BIO_PASS -- on sides, not on channel --> N_CHANNEL_EXP[Exposed Sensing Channel]
        BIO_PASS -- on sides, not on channel --> P_CHANNEL_EXP[Exposed Reference Channel]

        N_GIF_BIO -- functionalized with --> RECEPTOR[Biomolecule Receptor]
    end

Derivative 3.2: Radiation-Hardened Integrated Circuits for Space Applications

Enabling Description:
This derivative leverages the robust gate electrode formation and isolation of US Patent 8,198,686 for integrated circuits intended for space and high-radiation environments. The semiconductor substrate would be a silicon-on-insulator (SOI) wafer with a thick buried oxide (BOX) layer to provide enhanced isolation against single-event upsets (SEUs) and total ionizing dose (TID) effects. The gate insulating films (Claim 1) would use radiation-hardened dielectrics such as specially treated SiO2 or Al2O3, known for their low interface trap density and charge trapping under radiation exposure. The dual-metal gate electrodes (Claim 1) would be designed with materials highly resistant to radiation-induced shifts in work function or material degradation (e.g., Pt, W, or TiN with specific grain structures). The insulating film covering the side surfaces and active regions would be a thick, dense Si3N4 layer, providing additional shielding and structural integrity against mechanical stress during launch and thermal cycling in space. The manufacturing method (Claim 11) would incorporate specific steps like pre- and post-radiation annealing, and material choices would focus on inherent radiation tolerance.

graph TD
    subgraph Rad-Hard IC (Claim 1)
        SOI_SUB[SOI Substrate with Thick BOX] --> N_MIS_RH[N-Type Rad-Hard MISFET]
        SOI_SUB --> P_MIS_RH[P-Type Rad-Hard MISFET]

        N_MIS_RH --> N_GIF_RH[First Gate Insulating Film (Rad-Hard SiO2/Al2O3)]
        N_GIF_RH --> N_FGE_RH[First Gate Electrode (Pt/W/TiN)]
        P_MIS_RH --> P_GIF_RH[Second Gate Insulating Film (Rad-Hard SiO2/Al2O3)]
        P_GIF_RH --> P_SGE_RH[Second Gate Electrode (Pt/W/TiN)]

        N_FGE_RH -- side covered by --> RH_INS[Radiation-Hardened Insulating Film (Dense Si3N4)]
        P_SGE_RH -- side covered by --> RH_INS
        RH_INS -- not on top --> N_FGE_RH_TOP
        RH_INS -- not on top --> P_SGE_RH_TOP
    end

---

4. Integration with Emerging Tech

Derivative 4.1: AI-Optimized Adaptive Gate Work Function Control (Post-Fabrication)

Enabling Description:
This derivative integrates AI into the manufacturing method (Claim 11/12) for post-fabrication optimization of gate work functions. After the initial formation of the dual-metal gates, an additional, extremely thin "tuning layer" (e.g., a few atomic layers of a specific metal or metal oxide) is deposited over the exposed gate electrodes (Claim 1), effectively becoming part of the "second metal film" or "conductive film." AI algorithms, analyzing real-time electrical performance data from test structures on the wafer, would then dictate precise, localized annealing or plasma treatments (e.g., ion implantation at very low doses, or laser annealing) to subtly alter the work function of this tuning layer. This process allows for fine-grained adjustment of threshold voltages across the wafer, compensating for process variations or tailoring performance for specific application bins. The manufacturing method (Claim 11) would add a step (f) where the AI-driven tuning is performed on the exposed gate electrodes before final passivation.

sequenceDiagram
    participant FAB as Fabrication Line
    participant AI as AI Optimization System
    participant WAFER as Semiconductor Wafer

    FAB->>WAFER: Form Gate Stacks (Claims 11/12 steps a-e)
    FAB->>WAFER: Deposit Ultra-thin Tuning Layer (post-Claim 11/12)
    WAFER->>FAB: Electrical Test Data
    FAB->>AI: Send Test Data for Analysis
    AI->>AI: Analyze performance, identify VT drift
    AI->>AI: Calculate optimal localized tuning parameters
    AI->>FAB: Send Tuning Parameters (e.g., laser pulse, dose)
    FAB->>WAFER: Apply Localized Post-Fab Treatment
    WAFER->>FAB: Re-test (optional)
    FAB->>WAFER: Final Passivation

Derivative 4.2: IoT-Enabled Environmental Sensor with Integrated Power Management

Enabling Description:
This derivative adapts the semiconductor device (Claim 1) for deployment in distributed IoT environmental sensing nodes. The dual-metal gate MISFETs are designed for ultra-low power consumption, perhaps by optimizing the gate stack materials (first and second metal films, Claim 1) for lower leakage currents and reduced operating voltages, possibly using extreme high-k dielectrics. The manufacturing method (Claim 11) ensures tight control over channel doping and gate length to achieve minimal off-state current. Crucially, the power management unit (PMU) for the IoT sensor, including rectifiers and voltage regulators, is integrated onto the same chip using additional MISFETs derived from the same fabrication flow. The "insulating film" (Claim 1) around the gate electrodes is optimized not only for isolation but also for thermal dissipation in self-contained, potentially hermetically sealed, IoT packages. The device includes a small, integrated microcontroller and RF transceiver for transmitting sensor data (e.g., temperature, humidity, gas concentration) to a network.

graph TD
    subgraph IoT Sensor Node (Claim 1)
        SUB[Si Substrate] --> PMU_FETS[Integrated Power Management MISFETs]
        SUB --> SENS_FETS[Sensing Array MISFETs]
        SUB --> RF_FETS[RF Transceiver MISFETs]
        SUB --> MCU_FETS[Microcontroller Logic MISFETs]

        PMU_FETS -- utilize --> DUAL_GATES[Dual-Metal Gates (Ultra-Low Power Optimized)]
        SENS_FETS -- utilize --> DUAL_GATES
        RF_FETS -- utilize --> DUAL_GATES
        MCU_FETS -- utilize --> DUAL_GATES

        DUAL_GATES -- encapsulated by --> ENV_INS[Environmental Sealing Insulating Film]
        ENV_INS -- provides --> THERMAL_DISSIPATION[Thermal Dissipation]
        SENS_FETS -- provide data to --> MCU_FETS
        MCU_FETS -- transmits via --> RF_FETS
    end

---

5. The "Inverse" or Failure Mode

Derivative 5.1: Self-Healing Gate Dielectric for Enhanced Reliability

Enabling Description:
This inverse mode derivative (Claim 1) focuses on a "fail-safe" or "self-healing" mechanism for the gate dielectric. The first and second gate insulating films are composed of a multi-layer stack where one or more layers are engineered to undergo a self-repairing process in response to localized dielectric breakdown. For example, a middle layer could contain embedded nanoparticles that, upon breakdown, migrate or fuse to re-insulate the damaged area, or a reversible phase change material could be incorporated. The manufacturing method (Claim 11/12) would involve precise deposition techniques for these multi-layer dielectrics, possibly involving atomic layer deposition (ALD) of complex oxides or nitrides with specific dopants. The dual-metal gate electrodes (first and second metal films) would be selected for their chemical compatibility with the self-healing layers, ensuring that the repair mechanism does not adversely affect work function. The surrounding insulating film would maintain its integrity during any localized healing event.

stateDiagram-v2
    [*] --> Healthy
    Healthy --> Stress[Electrical Stress/Defect]
    Stress --> Local_Breakdown[Localized Dielectric Breakdown]
    Local_Breakdown --> Self_Repair[Self-Repairing Layer Activation]
    Self_Repair --> Heal_Complete[Healing Complete]
    Heal_Complete --> Healthy
    Self_Repair --> Permanent_Failure[Permanent Failure (if repair fails)]
    Permanent_Failure --> [*]

Derivative 5.2: Inherently Current-Limiting MISFETs for Overload Protection

Enabling Description:
This derivative focuses on designing the MISFETs (Claim 1) to inherently limit current during an overload event, preventing catastrophic failure or damage to other circuit components. This is achieved by engineering the channel region (active regions) and gate structure such that under excessive drain current or voltage conditions, a controlled, reversible degradation or characteristic shift occurs. For instance, the gate stack (gate insulating film, first/second metal films) could incorporate a material that exhibits a controlled, self-limiting increase in resistance or a reversible punch-through characteristic under extreme bias, effectively increasing the channel resistance and limiting current flow. The manufacturing method (Claim 11/12) would precisely control the stoichiometry or crystal structure of specific layers within the gate stack or channel. This could involve using amorphous or nanocrystalline materials in the gate electrode or gate dielectric that have predictable, non-catastrophic responses to overstress. The external insulating film plays a role in isolating the device and managing localized heat generated during current limiting.

flowchart TD
    A[Normal Operation] --> B{Overload Event Detected?};
    B -- Yes --> C[Channel Current Exceeds Threshold];
    C --> D[Gate Stack Material Response (e.g., Resistivity Increase)];
    D --> E[Self-Limiting Current Flow];
    E --> F{Overload Resolved?};
    F -- Yes --> G[Material Reverts to Normal State];
    G --> A;
    F -- No --> H[Sustained Current Limiting];
    H --> I[Safe Shutdown/System Intervention];
    B -- No --> A;

---

Combination Prior Art Scenarios

Here are at least three scenarios combining US Patent 8,198,686 with existing open-source standards to create prior art.

1. Integration with RISC-V Open-Source Instruction Set Architecture (ISA) for Low-Power Microcontrollers

Enabling Description:
The dual-metal gate MISFET technology described in US Patent 8,198,686, enabling high-precision gate electrodes and reduced isolation region width, can be directly applied to the manufacturing of energy-efficient RISC-V based microcontrollers. Specifically, the n-type and p-type MISFETs with optimized work functions, as fabricated by the method in Claim 11, would form the core logic cells and memory arrays of a RISC-V processor. The miniaturization achieved by the patent's techniques (e.g., reduced isolation region width Wnp, as discussed in the patent's detailed description) directly translates to smaller die sizes for RISC-V cores. The ability to precisely control the work function of the gate electrodes is critical for tailoring the threshold voltages of the different transistors (n-type and p-type) within the RISC-V core, allowing for operation at ultra-low voltages and minimizing static power consumption, a key design goal for many RISC-V implementations. The open-source nature of RISC-V enables widespread adoption and further optimization of such silicon implementations.

Combination Prior Art: US8198686B2 combined with the RISC-V ISA (e.g., RV32I base integer instruction set).
URL: https://riscv.org/

2. CMOS Image Sensor Pixels utilizing Dual-Metal Gate Transistors for Enhanced Readout

Enabling Description:
The advanced dual-metal gate MISFET structures of US Patent 8,198,686 can be integrated into the pixel architecture of Complementary Metal-Oxide-Semiconductor (CMOS) image sensors, which often follow industry-standard pixel designs and interfaces. The precise control over threshold voltages offered by the different metal gate materials (e.g., the second metal film for n-type and first metal film plus conductive film for p-type in Claim 1) can be utilized for optimizing the performance of the in-pixel transistors, such as the transfer gate, reset gate, source follower, and row select transistors. For example, a finely tuned n-type MISFET (using the second metal film) as a transfer gate can improve charge transfer efficiency and reduce lag. The reduced isolation region width (Claim 1) allows for higher pixel density and smaller pixel pitch, leading to higher resolution image sensors. This application is particularly relevant for standard CMOS image sensor designs adhering to common interfaces and data protocols for readout.

Combination Prior Art: US8198686B2 combined with IEEE 1857.1 (Standard for Interfacing a Sensor to a Digital System) or common CMOS image sensor pixel architectures (e.g., 4T active pixel sensor).
URL: https://standards.ieee.org/standard/1857_1-2016.html

3. High-Performance Computing (HPC) Interconnect Transistors with FinFET-like Dual-Metal Gates

Enabling Description:
The methods for forming high-precision gate electrodes with reduced isolation regions, as described in US Patent 8,198,686 (Claims 11 and 12), can be adapted to fabricate advanced FinFET or Gate-All-Around (GAA) structures essential for high-performance computing (HPC) interconnects. While the patent explicitly discusses lateral single-gate IGFETs, the core principle of replacing dummy gates with precisely tuned dual-metal gates can be extended to multi-gate devices. For HPC applications, especially in processors adhering to open standards for interconnects (like PCIe or CXL), the ability to tightly control the work function of both n-type and p-type transistors (Claim 1) is crucial for achieving high switching speeds and minimizing latency. The 'first recess' and 'second recess' formation steps (Claim 11, step d) and the subsequent metal filling (Claim 11, step e) could be directly applied to the trenches around a fin structure, allowing for separate work function metals for n-FinFETs and p-FinFETs. The overall miniaturization enables denser integration of logic for faster data transfer within HPC systems.

Combination Prior Art: US8198686B2 combined with the PCI Express (PCIe) standard (e.g., PCIe 5.0 or 6.0) or Compute Express Link (CXL) standard, which define physical layer electrical and timing requirements.
URL: https://pcisig.com/specifications/pcie
URL: https://www.computeexpresslink.org/

---

Citations:
https://riscv.org/
https://standards.ieee.org/standard/1857_1-2016.html
https://pcisig.com/specifications/pcie
https://www.computeexpresslink.org/