US 8884373

US Patent 8,884,373: Semiconductor Device

Title: Semiconductor device

Current Assignee: Advanced Integrated Circuit Process LLC

Inventors: Yoshihiro Sato, Hideyuki Arai, Takayuki Yamada

Filing Date: October 31, 2012

Issue Date: November 11, 2014

Abstract:
A first dual-gate electrode includes a gate electrode located on a first active region and having a first silicon film of a first conductivity type and a gate electrode located on a second active region and having a first silicon film of a second conductivity type. A second dual-gate electrode includes a gate electrode located on a third active region and having a second silicon film of the first conductivity type and a gate electrode located on a fourth active region and having a second silicon film of the second conductivity type. At least a portion of the first silicon film of the first conductivity type has a first-conductivity-type impurity concentration higher than that of a portion of the second silicon film of the first conductivity type located on the third active region.

Plain-Language Overview of Independent Claims:

Independent Claim 1:
This claim describes a semiconductor device with two dual-gate electrodes. The first dual-gate electrode is made of a first silicon film. One part of this film (first gate electrode) is on a first active region and has a first type of conductivity. Another part (second gate electrode) is on a second active region and has a second type of conductivity. These two parts are connected over an isolation region. The second dual-gate electrode is made of a second silicon film, similarly divided into a third gate electrode on a third active region (first conductivity type) and a fourth gate electrode on a fourth active region (second conductivity type). A key feature is that the first-conductivity-type impurity concentration in at least a portion of the first silicon film (from the first dual-gate electrode) is higher than that in a portion of the second silicon film (from the second dual-gate electrode) that is on the third active region.

Independent Claim 13:
This claim outlines a method for fabricating a semiconductor device. The device includes a first dual-gate electrode (with a first gate electrode on a first active region and a second gate electrode on a second active region) and a second dual-gate electrode (with a third gate electrode on a third active region and a fourth gate electrode on a fourth active region). The method involves four main steps:
(a) forming a silicon film across all four active regions,
(b) introducing a first conductivity type impurity into the silicon film while covering the portions over the second, third, and fourth active regions with a first mask,
(c) introducing a second conductivity type impurity while covering the portion over the first active region with a second mask, and
(d) patterning the silicon film after steps (b) and (c) to form the individual gate electrodes on their respective active regions.

Independent Claim 14:
This claim describes a semiconductor device similar to Claim 1, but with additional details regarding the impurity concentrations and the width of the isolation regions. Specifically, it states that the isolation width between the first and second active regions (for the first dual-gate electrode) is larger than the isolation width between the third and fourth active regions (for the second dual-gate electrode). It also specifies that at least a portion of the first silicon film of the first conductivity type has a higher impurity concentration than a portion of the second silicon film of the first conductivity type on the third active region. Furthermore, at least a portion of the first silicon film of the second conductivity type has an impurity concentration substantially equal to that of a portion of the second silicon film of the second conductivity type on the fourth active region.

Independent Claim 15:
This claim also describes a semiconductor device and builds upon the features of Claim 1. It emphasizes that a portion of the first silicon film of the first conductivity type located on the first active region has a first-conductivity-type impurity concentration higher than that of a portion of the second silicon film of the first conductivity type located on the third active region. This further specifies the location of the higher impurity concentration within the first-conductivity-type silicon film of the first dual-gate electrode.