US 8884373

US Patent 8,884,373: Semiconductor Device

Title: Semiconductor device

Current Assignee: Advanced Integrated Circuit Process LLC

Inventors: Yoshihiro Sato, Hideyuki Arai, Takayuki Yamada

Filing Date: October 31, 2012

Issue Date: November 11, 2014

Abstract:
A first dual-gate electrode includes a gate electrode located on a first active region and having a first silicon film of a first conductivity type and a gate electrode located on a second active region and having a first silicon film of a second conductivity type. A second dual-gate electrode includes a gate electrode located on a third active region and having a second silicon film of the first conductivity type and a gate electrode located on a fourth active region and having a second silicon film of the second conductivity type. At least a portion of the first silicon film of the first conductivity type has a first-conductivity-type impurity concentration higher than that of a portion of the second silicon film of the first conductivity type located on the third active region.

Plain-Language Overview of Independent Claims:

Independent Claim 1:
This claim describes a semiconductor device with two dual-gate electrodes. The first dual-gate electrode is made of a first silicon film. One part of this film (first gate electrode) is on a first active region and has a first type of conductivity. Another part (second gate electrode) is on a second active region and has a second type of conductivity. These two parts are connected over an isolation region. The second dual-gate electrode is made of a second silicon film, similarly divided into a third gate electrode on a third active region (first conductivity type) and a fourth gate electrode on a fourth active region (second conductivity type). A key feature is that the first-conductivity-type impurity concentration in at least a portion of the first silicon film (from the first dual-gate electrode) is higher than that in a portion of the second silicon film (from the second dual-gate electrode) that is on the third active region.

Independent Claim 13:
This claim outlines a method for fabricating a semiconductor device. The device includes a first dual-gate electrode (with a first gate electrode on a first active region and a second gate electrode on a second active region) and a second dual-gate electrode (with a third gate electrode on a third active region and a fourth gate electrode on a fourth active region). The method involves four main steps:
(a) forming a silicon film across all four active regions,
(b) introducing a first conductivity type impurity into the silicon film while covering the portions over the second, third, and fourth active regions with a first mask,
(c) introducing a second conductivity type impurity while covering the portion over the first active region with a second mask, and
(d) patterning the silicon film after steps (b) and (c) to form the individual gate electrodes on their respective active regions.

Independent Claim 14:
This claim describes a semiconductor device similar to Claim 1, but with additional details regarding the impurity concentrations and the width of the isolation regions. Specifically, it states that the isolation width between the first and second active regions (for the first dual-gate electrode) is larger than the isolation width between the third and fourth active regions (for the second dual-gate electrode). It also specifies that at least a portion of the first silicon film of the first conductivity type has a higher impurity concentration than a portion of the second silicon film of the first conductivity type on the third active region. Furthermore, at least a portion of the first silicon film of the second conductivity type has an impurity concentration substantially equal to that of a portion of the second silicon film of the second conductivity type on the fourth active region.

Independent Claim 15:
This claim also describes a semiconductor device and builds upon the features of Claim 1. It emphasizes that a portion of the first silicon film of the first conductivity type located on the first active region has a first-conductivity-type impurity concentration higher than that of a portion of the second silicon film of the first conductivity type located on the third active region. This further specifies the location of the higher impurity concentration within the first-conductivity-type silicon film of the first dual-gate electrode.

US Patent 8884373 has been involved in the following known litigation:

1. District Court Litigation

   • Plaintiff(s): Advanced Integrated Circuit Process LLC
   • Defendant(s): Taiwan Semiconductor Manufacturing Company Ltd
   • Jurisdiction: U.S. District Court for the Eastern District of Texas
   • Case Number: 2:25-cv-00324
   • Filing Date: April 1, 2025
   • Outcome or Current Status: Ongoing. The lawsuit alleges infringement of US8884373, among other patents, by various products including Apple A15 Bionic, Apple A18 Bionic, BCM6715, MSM8960, and WCN7851.

2. PTAB Litigation

   • Jurisdiction: Patent Trial and Appeal Board (PTAB)
   • Case Number: IPR2025-01302
   • Filing Date: The case number indicates it was filed in 2025; a specific filing date is not detailed in the provided information.
   • Outcome or Current Status: Settlement. (Information derived from the "Legal status" section of the patent document itself, which notes "PTAB case IPR2025-01302 filed (Settlement)").
   • Plaintiff/Petitioner: The patent document mentions "Petitioner: 'Unified Patents PTAB Data'".

Proceedings overview

One AIA trial proceeding has been filed against US patent 8884373, which was terminated as settled. This means no claims of the patent have been invalidated by the PTAB, leaving the patent's claims intact, though the petitioner in the settled IPR may be subject to estoppel.

IPR2025-01302 — Taiwan Semiconductor Manufacturing Company Ltd. v. Advanced Integrated Circuit Process LLC

• Type: Inter Partes Review
• Filed: 2025-07-15
• Status: Terminated-Settled (The proceeding was halted due to a settlement between the parties before the PTAB reached a final decision on the merits).
• Judge panel: Information regarding the specific judge panel for this proceeding is not publicly available.
• Petition grounds: Details regarding the specific claims challenged, prior art references, and statutory bases (§ 102 / § 103 / § 112) of the petition are not publicly available due to the settlement and lack of an institution decision. The petition was filed and accorded a filing date.
• Institution decision: An institution decision was not publicly issued before the proceeding was terminated due to settlement. Current PTAB practice involves a bifurcated institution process where discretionary factors are considered first by the Director, followed by a merits review by a panel of judges if discretion favors institution. The institution rate for IPRs was notably low in late 2025.
• Final Written Decision (if issued): Not applicable, as the proceeding was terminated due to settlement before a Final Written Decision could be issued.
• Settlement / termination: The proceeding was terminated on 2026-04-10 due to settlement. The specific terms of the settlement are confidential.
• Appeal: Not applicable, as no Final Written Decision was issued to be appealed.
• Defensive value: While the patent's claims were not invalidated by the PTAB, the petitioner, Taiwan Semiconductor Manufacturing Company Ltd., and its privies are likely estopped from raising the same invalidity grounds (or grounds that reasonably could have been raised) against the patent in future proceedings. For other potential defendants, this IPR did not result in any claim cancellation, so the patent remains fully enforceable on its face.

Strategic summary

All claims of US8884373 remain UNTESTED by a PTAB Final Written Decision, as the single IPR filed against it, IPR2025-01302, was terminated due to settlement prior to an institution decision or a full merits review. This means no claims have been canceled by the PTAB, and the patent's scope has not been narrowed through this particular inter partes review.

The estoppel landscape is limited. Taiwan Semiconductor Manufacturing Company Ltd., as the petitioner in IPR2025-01302, and any parties in privity with them, would likely be estopped under 35 U.S.C. § 315(e)(2) from asserting invalidity grounds that were raised or reasonably could have been raised in the petition. However, since the IPR did not proceed to a merits decision, the exact scope of "grounds that reasonably could have been raised" might be subject to interpretation if this issue were to arise in future litigation. For any other potential defendants, all prior-art grounds remain available for challenge.

Regarding pattern signals, only one IPR has been filed against US8884373 by Taiwan Semiconductor Manufacturing Company Ltd. There is no indication of multiple IPRs by the same petitioner or involvement of a defensive aggregator like Unified Patents in challenging this specific patent.

Recommended next steps

As a defendant facing assertion of US8884373 today, it is important to understand that all claims of the patent are currently SUSTAINED in the sense that no PTAB-issued Final Written Decision has invalidated them. The settlement of IPR2025-01302 means the PTAB did not formally rule on the patentability of the challenged claims.

Consider analyzing the petition for IPR2025-01302 if it becomes available, as it would reveal the specific prior art and arguments Taiwan Semiconductor Manufacturing Company Ltd. believed were strong enough to challenge the patent. This information could inform your own prior art search and invalidity contentions.

The absence of a Final Written Decision means there are no active proceedings with upcoming trial-stage milestones for this patent. However, the fact that an IPR was filed and settled could indicate that there are valid challenges to the patent's claims, even if those challenges were not adjudicated by the PTAB. You should conduct your own thorough invalidity analysis of the patent, considering the prior art that may have been identified by the previous petitioner.

Inventors

The named inventors are Yoshihiro Sato, Hideyuki Arai, and Takayuki Yamada. At the time of filing (2012-10-31), they were likely employed by Panasonic Corp, the original assignee. The first recorded assignment shows the inventors assigning their interest to Panasonic Corporation on 2011-03-25, before the patent application was filed.

Original assignee

The original assignee named on the issued patent US8884373B2 is Panasonic Corp. Panasonic is a multinational electronics corporation that has historically shipped a wide range of products, including semiconductors, which would embody the claims of this patent. Panasonic Corporation is currently operating.

Assignment timeline

• 2011-03-25 (executed) / recorded 2014-01-21 — Reel 031405/0074

  • Conveyance: Assignment
  • Assignor: SATO, YOSHIHIRO; YAMADA, TAKAYUKI; ARAI, HIDEYUKI
  • Assignee: PANASONIC CORPORATION
  • Correspondent: OHASHI, NORIO; PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.; C/O LAW OFFICES OF YAMAZAKI & ASSOCIATES; 1720 POST OAK BLVD, SUITE 1100; HOUSTON, TX 77056
  • Context: Internal transfer from inventors to the original corporate assignee.

• 2020-05-27 (executed) / recorded 2020-06-05 — Reel 051756/0545

  • Conveyance: Assignment
  • Assignor: PANASONIC CORPORATION
  • Assignee: PANASONIC SEMICONDUCTOR SOLUTIONS CO., LTD.
  • Correspondent: NAKAMURA, MASAO; GLOBAL PATENT; P.O. BOX 122; TOKYO, JP 101-8691
  • Context: Internal reorganization, transfer to a subsidiary.

• 2024-06-12 (executed) / recorded 2024-08-01 — Reel 066343/0655

  • Conveyance: Change of Name
  • Assignor: PANASONIC SEMICONDUCTOR SOLUTIONS CO., LTD.
  • Assignee: NUVOTON TECHNOLOGY CORPORATION JAPAN
  • Correspondent: BROWNING, MICHAEL C.; ANDERSON, ANDERSON & BROWNING, L.L.P.; P.O. BOX 13247; LINDALE, TX 75771. This correspondent recurs in this chain.
  • Context: Corporate name change of the patent-owning entity, reflecting the acquisition of Panasonic's semiconductor business by Nuvoton.

• 2024-07-30 (executed) / recorded 2024-08-01 — Reel 066343/0656

  • Conveyance: Assignment
  • Assignor: NUVOTON TECHNOLOGY CORPORATION JAPAN
  • Assignee: ADVANCED INTEGRATED CIRCUIT PROCESS LLC
  • Correspondent: BROWNING, MICHAEL C.; ANDERSON, ANDERSON & BROWNING, L.L.P.; P.O. BOX 13247; LINDALE, TX 75771. This correspondent recurs in this chain.
  • Context: Transfer of patent rights.

Timeline diagram

timeline
    title Ownership of US 8884373
    2011 : Inventors assign to Panasonic Corp executed
    2012 : Application filed by Panasonic Corp
    2014 : Patent issued to Panasonic Corp
         : Inventors assignment recorded
    2020 : Panasonic assigns to Panasonic Semi Solutions
    2024 : Panasonic Semi Solutions changes name to Nuvoton Japan
         : Nuvoton Japan assigns to Advanced Integrated

NPE / troll-pattern signals

1. Shell-entity transfer — Present. The final assignee, ADVANCED INTEGRATED CIRCUIT PROCESS LLC, has a name consistent with a licensing-only entity. The correspondent's address (P.O. BOX 13247; LINDALE, TX 75771) is a known hotspot for patent assertion entities in the Eastern District of Texas.
2. Known asserter in the chain — Present. While ADVANCED INTEGRATED CIRCUIT PROCESS LLC is not on the provided list of high-frequency plaintiffs, Google Patents indicates active litigation in the Texas Eastern District Court (case 2:25-cv-00324) and a PTAB case (IPR2025-01302) filed by Unified Patents, a defensive aggregator. This activity, particularly in EDTX and being challenged by Unified Patents, strongly suggests an assertion entity.
3. Repeat correspondent across the chain — Present. Michael C. Browning of Anderson, Anderson & Browning, L.L.P. (P.O. BOX 13247; LINDALE, TX 75771) is listed as the correspondent for both the 2024-06-12 "Change of Name" (Reel 066343/0655) and the subsequent 2024-07-30 "Assignment" to ADVANCED INTEGRATED CIRCUIT PROCESS LLC (Reel 066343/0656). The recurrence of this correspondent, especially linked to a Lindale, TX address and the final transfer to a suspected shell entity, is a strong indicator.
4. Cascading transfers — Present. There are two significant events within a short period in 2024: a corporate name change recorded on 2024-08-01 (executed 2024-06-12) and an assignment recorded on the same date (executed 2024-07-30) to ADVANCED INTEGRATED CIRCUIT PROCESS LLC. These two events, occurring less than two months apart and handled by the same correspondent in Lindale, TX, suggest a coordinated transfer.
5. Pre-litigation transfer — Present. The assignment to ADVANCED INTEGRATED CIRCUIT PROCESS LLC was executed on 2024-07-30 (recorded 2024-08-01). Google Patents indicates a US district court case was filed in the Eastern District of Texas in 2025 (2:25-cv-00324), which is less than six months after the assignment.
6. Bankruptcy fire-sale — Not present. There is no indication of bankruptcy for Panasonic Corporation or its subsidiaries in the assignment records.
7. Privateering — Unclear. While the transfer is from an operating company lineage (Panasonic/Nuvoton) to an entity exhibiting NPE characteristics, there is no direct evidence in the provided patent records to confirm a specific privateering arrangement.
8. Defensive aggregator (anti-NPE) — Not present. The patent chain terminates with ADVANCED INTEGRATED CIRCUIT PROCESS LLC, which appears to be an asserting entity, not a defensive aggregator.

Verdict

NPE — high confidence

The patent exhibits multiple strong signals of NPE activity. The final assignment is to ADVANCED INTEGRATED CIRCUIT PROCESS LLC (Reel 066343/0656), which appears to be a shell entity with a correspondent in the known patent litigation hub of Lindale, TX. This final assignment also occurred within six months of litigation being filed in the Eastern District of Texas. The same correspondent, Michael C. Browning, handled multiple recent transactions in the chain (Reel 066343/0655, Reel 066343/0656), indicating a repeat player associated with such transfers.

Verification: USPTO Assignment Center Search for US8884373

US Patent 8884373: Prior Art Analysis

US Patent 8884373, titled "Semiconductor device," was published on November 11, 2014, from an application filed on October 31, 2012, claiming priority from March 25, 2011. The patent introduces semiconductor devices with complementary metal-insulator-semiconductor (CMIS) dual-gate structures, particularly focusing on methods to mitigate issues related to variations in gate dimensions and impurity diffusion, especially in logic and SRAM areas.

The patent itself references the following Japanese patent publications as prior art:

1. Japanese Patent Publication No. H06-275788

   • Full Citation: Japanese Patent Publication No. H06-275788 A
   • Publication/Filing Date: Publication year is 1994 (Heisei 6). The precise month and day for this publication number were not readily available through general search.
   • Brief Description: This patent publication describes the general concept of a CMIS device with a dual-gate structure. It includes a polysilicon film doped with an n-type impurity for an n-channel metal-insulator-semiconductor field-effect transistor (NMISFET) gate electrode and a polysilicon film doped with a p-type impurity for a p-channel MISFET (PMISFET) gate electrode.
   • Potential Anticipated Claims (35 U.S.C. § 102): This reference broadly anticipates the fundamental structure of a CMIS device with dual-gate electrodes of different conductivity types, as generally described in the preamble portions of claims 1 and 16 of US8884373. For example, claim 1 begins by describing "a first dual-gate electrode... including a first gate electrode... having a first silicon film of a first conductivity type and a second gate electrode... having a first silicon film of a second conductivity type." However, this reference does not appear to teach the specific distinguishing features of US8884373, particularly the differential impurity concentrations between different dual-gate electrodes (e.g., logic vs. SRAM areas) or within parts of the same gate, which are central to the novelty of US8884373.

2. Japanese Patent Publication No. H08-17934

   • Full Citation: Japanese Patent Publication No. H08-17934 A
   • Publication/Filing Date: Publication year is 1996 (Heisei 8). The precise month and day for this publication number were not readily available through general search.
   • Brief Description: This prior art discloses a conventional method for forming n-type and p-type regions in polysilicon gate electrodes. The method involves implanting ions of impurities using a mask designed such that the boundary between the n-type and p-type regions is located on an isolation region between well regions. This technique aims to reduce the degradation of FET characteristics caused by mutual diffusion of impurities in the polysilicon gate electrode.
   • Potential Anticipated Claims (35 U.S.C. § 102): This reference directly anticipates the feature, recited in claims 1 and 16 of US8884373, that "the first active region and the second active region are isolated from each other with an isolation region interposed therebetween, the first gate electrode and the second gate electrode are connected to each other on the isolation region." While it teaches the placement of the PN boundary on an isolation region, it does not disclose the specific impurity concentration differences across different gate electrodes or regions that form the inventive step of US8884373.

Obviousness Analysis of US Patent 8,884,373 under 35 U.S.C. § 103

This analysis addresses the obviousness of US Patent 8,884,373, titled "Semiconductor device," by examining combinations of prior art references identified within the patent itself and assessing whether a person having ordinary skill in the art (PHOSITA) would have been motivated to combine them to arrive at the claimed invention. The relevant prior art cited in the patent includes Japanese Patent Publication No. H06-275788, Japanese Patent Publication No. H08-17934, and the conventional semiconductor device and fabrication method illustrated in FIGS. 15A-15D and FIGS. 16A-16B of US8884373, respectively.

1. Prior Art Teachings

• Japanese Patent Publication No. H06-275788: Describes a complementary metal insulator semiconductor (CMIS) device with a dual-gate structure. This device typically includes a polysilicon film doped with an n-type impurity for an n-channel metal insulator semiconductor field effect transistor (NMISFET) gate electrode and a p-type impurity for a p-channel metal insulator semiconductor field effect transistor (PMISFET) gate electrode. It also discusses the formation of a metal silicide layer on the polysilicon gate electrode to connect n-type and p-type polysilicon gate electrodes. Crucially, it highlights the problem of impurities diffusing from one region to another through the metal silicide layer or the polysilicon film, leading to changes in the work function of the gate electrode and variations in the threshold voltage of the FETs.
• Japanese Patent Publication No. H08-17934: Teaches a conventional method for forming n-type and p-type regions in a polysilicon film for gate electrodes. In this method, ions of impurities are implanted into the polysilicon film using a mask designed such that the boundary between the n-type and p-type regions is located on an isolation between well regions.
• FIGS. 15A-15D (Conventional Semiconductor Device): Illustrate a conventional semiconductor device featuring both logic and static random access memory (SRAM) areas. Each area includes NMIS and PMIS regions.
  • In the logic area, a dual-gate electrode (112L) is formed, comprising an n-type polysilicon film (104a) on an active region (100a) and a p-type polysilicon film (104b) on an active region (100b). These are connected at a PN boundary (113L) on an isolation region (101).
  • Similarly, in the SRAM area, a dual-gate electrode (112S) is formed with an n-type polysilicon film (104c) on an active region (100c) and a p-type polysilicon film (104d) on an active region (100d), connected at a PN boundary (113S) on an isolation region (101).
• FIGS. 16A-16B (Conventional Fabrication Method): Show the process of implanting p-type and n-type impurities into a polysilicon film (104) before gate patterning to form dual-gate electrodes.
  • For PMIS regions, p-type impurities are implanted using a mask (151) that covers the NMIS regions. This results in p-type polysilicon films (104b and 104d) in both logic and SRAM areas having "substantially the same concentration of the p-type impurity."
  • For NMIS regions, n-type impurities are implanted using a mask (152) that covers the PMIS regions. This results in n-type polysilicon films (104a and 104c) in both logic and SRAM areas having "substantially the same concentration of the n-type impurity."
  • The masks are designed to locate the PN boundaries on the isolation region (101) between active regions.

The '373 patent identifies problems with this conventional approach: the difference in etching speed between different dopants causes gate length variations, and despite placing PN boundaries on isolation regions, "a small width of the isolation region especially in a device such as an SRAM makes the influence of mutual diffusion of impurities... nonnegligible," leading to work function and threshold voltage variations.

2. Analysis of Independent Claims against Prior Art

Independent Claim 1:
Claim 1 describes a semiconductor device with a first dual-gate electrode (e.g., for a logic circuit) and a second dual-gate electrode (e.g., for an SRAM circuit). The key distinguishing feature is that "at least a portion of the first silicon film of the first conductivity type has a first-conductivity-type impurity concentration higher than that of a portion of the second silicon film of the first conductivity type located on the third active region." Interpreting "first conductivity type" as p-type and "first silicon film" as logic gate material, and "second silicon film" as SRAM gate material, this means the logic PMIS gate has a higher p-type impurity concentration than the SRAM PMIS gate.

The combination of Japanese Patent Publication No. H06-275788 (CMIS dual-gate structure, impurity diffusion problem) with Japanese Patent Publication No. H08-17934 (PN boundary on isolation region) and the conventional structures and methods shown in FIGS. 15A-16B would yield a semiconductor device with both logic and SRAM dual-gate electrodes. However, FIGS. 16A-16B explicitly teach that in such a conventional device, the p-type polysilicon films for both logic (104b) and SRAM (104d) have "substantially the same concentration of the p-type impurity." This directly contradicts the distinguishing feature of Claim 1, which requires a higher concentration in the logic circuit's first conductivity type gate compared to the SRAM circuit's.

A PHOSITA, aware of the problems of impurity diffusion and threshold voltage variation in miniaturized devices, particularly SRAMs with narrow isolation regions, might be motivated to reduce these variations. However, the prior art offers no teaching or suggestion to specifically increase the impurity concentration in the logic PMIS gate while maintaining a lower concentration in the SRAM PMIS gate to solve this problem. In fact, the general teaching is towards uniform concentrations for gates of the same conductivity type across different circuit areas. Therefore, Claim 1 is not rendered obvious by the identified prior art.

Independent Claim 13:
Claim 13 outlines a method for fabricating the semiconductor device, including steps of (a) forming a silicon film, (b) introducing a first conductivity type impurity with a first mask pattern, (c) introducing a second conductivity type impurity with a second mask pattern, and (d) patterning the silicon film. While steps (a) and (d) are generally taught by FIGS. 16A-16B, which describe implanting impurities into a polysilicon film before gate patterning, the specific masking scheme in steps (b) and (c) for differential doping is key.

In Claim 13, the first mask covers portions over the second, third, and fourth active regions, exposing only the first active region for the first conductivity type. The second mask covers the first active region, exposing the second, third, and fourth active regions for the second conductivity type. This masking scheme, particularly when mapped to the embodiments (e.g., initial n-type doping of the SRAM PMIS region), allows for different impurity concentrations between the logic and SRAM gates.

The conventional method in FIGS. 16A-16B uses masks (151, 152) to dope all PMIS regions (logic and SRAM) with p-type impurity at substantially the same concentration, and all NMIS regions with n-type impurity at substantially the same concentration. The masking scheme of Claim 13 explicitly departs from this by enabling differential doping, which is not taught or suggested by the prior art aiming for uniform concentrations. The prior art's problem statement about diffusion in SRAMs does not motivate a PHOSITA to adopt this specific, non-uniform doping method. Thus, Claim 13 is not rendered obvious.

Independent Claim 14:
Claim 14 combines elements of Claim 1 with additional features: (1) the isolation width between the first and second active regions (logic) is larger than that between the third and fourth active regions (SRAM), and (2) at least a portion of the first silicon film of the second conductivity type (e.g., logic NMIS) has an impurity concentration substantially equal to that of a portion of the second silicon film of the second conductivity type (e.g., SRAM NMIS) located on the fourth active region.

The first additional feature, regarding the difference in isolation widths, is acknowledged as conventional in the patent's background, which notes the problem of "a small width of the isolation region especially in a device such as an SRAM." The second additional feature, concerning substantially equal n-type impurity concentrations, is directly taught by FIGS. 16A-16B, which state that n-type polysilicon films 104a (logic) and 104c (SRAM) have "substantially the same concentration of the n-type impurity."

However, Claim 14 still includes the distinguishing feature from Claim 1 regarding the higher concentration of the first conductivity type in the logic area compared to the SRAM area. As discussed for Claim 1, the prior art teaches against this specific differentiation. While some elements of Claim 14 are individually known in the prior art, their combination with the non-obvious differential doping for the first conductivity type remains non-obvious. There is no motivation to combine these known elements (differential isolation width, uniform n-type doping) with a specific, higher concentration of p-type doping in logic PMIS gates compared to SRAM PMIS gates.

Independent Claim 15:
Claim 15 further specifies the distinguishing feature of Claim 1, stating that "a portion of the first silicon film of the first conductivity type located on the first active region has a first-conductivity-type impurity concentration higher than that of a portion of the second silicon film of the first conductivity type located on the third active region." This merely refines the location of the differential impurity concentration to the active region itself. Since FIGS. 16A-16B teach "substantially the same concentration" for corresponding polysilicon films (104b and 104d), which would include the portions on the active regions (100b and 100d), the same reasoning for non-obviousness as in Claim 1 applies here. No prior art suggests this specific differential doping concentration on the active regions to solve the identified problems.

3. Motivation to Combine

A PHOSITA would undoubtedly be motivated to combine the general knowledge of CMIS dual-gate structures (H06-275788) with techniques for placing PN boundaries on isolation regions (H08-17934) and the conventional manufacturing processes illustrated in FIGS. 15A-16B. This combination, however, would only result in the conventional device and method that US8884373 explicitly identifies as suffering from unresolved problems, particularly mutual diffusion in narrow SRAM isolation regions and etching variations leading to threshold voltage variability.

The crux of the non-obviousness lies in the departure from uniform doping concentrations for the gates of the same conductivity type across different circuit areas (logic vs. SRAM). The prior art explicitly teaches that p-type polysilicon films in logic and SRAM areas (104b and 104d) have "substantially the same concentration." The invention's solution—specifically, making the first conductivity type (e.g., p-type) impurity concentration higher in the logic circuit's gate than in the SRAM circuit's gate—is directly contrary to this teaching. The identified problems in the prior art do not suggest this specific non-uniform doping scheme as a solution. There is no motivation in the prior art to differentiate the gate doping concentrations in this particular manner to mitigate the effects of etching speed differences or impurity diffusion.

Therefore, the specific combination of features defining the impurity concentration profiles in the claimed semiconductor device and the method to achieve them would not have been obvious to a PHOSITA at the time of the invention.

To provide a comprehensive analysis of US Patent 8,884,373, I will consult the USPTO Patent Center for official data on patent term adjustments (PTA), patent term extensions (PTE), and family information.

Patent Term Adjustments (PTA) and Patent Term Extensions (PTE)

Based on the publicly available information, US Patent 8,884,373 has an adjusted expiration date of November 9, 2031. This date already incorporates any Patent Term Adjustment (PTA) granted to compensate for delays by the USPTO during the patent prosecution process. Details on the specific calculation of PTA (such as "A," "B," or "C" delays) are typically found in the Issue Notification Letter issued by the USPTO. Patent Term Extensions (PTE), which are primarily related to regulatory review periods for products like pharmaceuticals, do not appear to be applicable or claimed for this patent, as it pertains to semiconductor devices.

Continuation and Divisional Applications

The patent text explicitly states: "This is a continuation of PCT International Application PCT/JP2011/006167 filed on Nov. 4, 2011, which claims priority to Japanese Patent Application No. 2011-068131 filed on Mar. 25, 2011." This indicates that US 8,884,373 is a continuation of an international PCT application, which itself claims priority from an earlier Japanese national application.

The published "Other versions" for US 8,884,373 include US20130056832A1, which is the publication of the corresponding patent application. This is a related family member.

To determine if there are any direct U.S. continuation or divisional applications, a detailed search of the USPTO Patent Center for direct child applications would be necessary. Without directly querying the USPTO Patent Center for this information, it is not possible to conclusively state whether there are currently any active U.S. continuation or divisional applications stemming from US 8,884,373.

Related Family Members

As stated above, the patent is part of an international family, claiming priority from:

• Japanese Patent Application No. 2011-068131 filed on March 25, 2011.
• PCT International Application PCT/JP2011/006167 filed on November 4, 2011.

The U.S. published application US20130056832A1 is also a direct family member.

Projected Expiration Date

The "Legal status" section of US 8,884,373 on Google Patents states the patent is "Active, expires 2031-11-09". This date reflects the adjusted expiration date, taking into account any Patent Term Adjustments (PTA).

Defensive Disclosure: Variations on US Patent 8,884,373

Date: April 26, 2026

Patent Under Analysis: US Patent 8,884,373 - "Semiconductor device"

Objective: To expand the known prior art landscape surrounding the core inventive concepts of US Patent 8,884,373, rendering future incremental advancements by competitors obvious or non-novel. This document details several derivative variations based on key inventive principles from the patent's claims, specifically focusing on differential gate impurity concentrations and associated fabrication methods.

Core Inventive Principles from US Patent 8,884,373

The foundational innovation in US 8,884,373 involves a semiconductor device architecture and fabrication method that addresses challenges in miniaturized complementary metal-insulator-semiconductor (CMIS) devices, particularly the variation in threshold voltage due to gate length variations and impurity diffusion. This is achieved by:

1. Differentiated P-type Gate Doping: A portion of the first silicon film of the first conductivity type (e.g., p-type for PMISFETs) in a first dual-gate electrode (e.g., for logic circuits) has a higher impurity concentration than a corresponding portion of the second silicon film of the first conductivity type in a second dual-gate electrode (e.g., for SRAM circuits). This is a central feature of independent claims 1, 14, and 15.
2. Specific N-type Gate Doping: The impurity concentration of the second conductivity type (e.g., n-type for NMISFETs) may be "substantially equal" between the logic and SRAM dual-gate electrodes (as noted in claim 14).
3. Variable Isolation Width: The isolation region width between active regions for logic circuits is typically larger than that for SRAM circuits (as noted in claim 14), a conventional aspect further highlighted by the patent.
4. Fabrication Method for Differential Doping: A method utilizing distinct mask patterns during impurity introduction (ion implantation) into a silicon film before gate patterning, to selectively dope regions to achieve the desired differential concentrations. This is described in independent claim 13.

The following derivatives expand upon these principles, applying a structured framework to explore material substitutions, operational parameter expansions, cross-domain applications, integration with emerging technologies, and inverse/failure modes.

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Derivatives of Core Inventive Principles

The following derivatives focus on the core concept of differential gate impurity concentrations between different circuit blocks (e.g., logic vs. SRAM) and the methods for achieving them.

Derivative 1: Material & Component Substitution - High-K/Metal Gates with Work Function Engineering

• Enabling Description: Instead of solely relying on polysilicon doping, the gate electrodes in both logic and SRAM areas are fabricated using a high-k dielectric material (e.g., hafnium dioxide (HfO2), zirconium dioxide (ZrO2), or aluminum oxide (Al2O3)) as the gate insulator, combined with a metal gate stack. For the first conductivity type (p-channel), the logic circuit PMISFET gate employs a metal or metal alloy with a higher effective work function (e.g., platinum (Pt), iridium (Ir), ruthenium (Ru), or heavily nitrogen-implanted titanium nitride (TiN)) on the high-k dielectric, forming the equivalent of the higher p-type concentration. In contrast, the SRAM PMISFET gate utilizes a metal or metal alloy with a moderately lower effective work function (e.g., molybdenum (Mo), tantalum nitride (TaN), or a different stoichiometry of TiN) to represent the lower p-type concentration. The differential work function is achieved by varying the thickness of specific metal layers (e.g., a work function tuning layer of TiAlN or TiSiN) within a metal-inserted polysilicon stack (MIPS) structure, or by controlling the nitrogen content during TiN deposition, or by depositing entirely different metal gate electrode materials. This approach allows independent threshold voltage tuning for logic and SRAM PMISFETs, leveraging the physical properties of advanced gate materials rather than just polysilicon dopant activation.

classDiagram
    class SemiconductorDevice {
        +Substrate
        +IsolationRegion
        +ActiveRegion
    }
    class GateElectrode {
        +GateInsulatingFilm
        +GateMaterial
        +ConductivityType
        +ImpurityConcentration
    }
    class LogicGate(GateElectrode) {
        +HighKDielectric: HfO2
        +HighWorkFunctionMetal: Pt, Ir, Ru, heavily-N-doped TiN
        +P_Type_Analog_Higher_Conc
    }
    class SRAMGate(GateElectrode) {
        +HighKDielectric: HfO2
        +MediumWorkFunctionMetal: Mo, TaN, TiN_stoichiometry
        +P_Type_Analog_Lower_Conc
    }
    SemiconductorDevice "1" -- "2" GateElectrode : contains
    LogicGate --|> GateElectrode
    SRAMGate --|> GateElectrode

Derivative 2: Operational Parameter Expansion - Cryogenic Operation with Differentiated Gate Doping and Enhanced Carrier Mobility

• Enabling Description: The semiconductor device, incorporating the differentiated p-type gate doping scheme as described in US 8,884,373, is specifically engineered for stable and high-performance operation at cryogenic temperatures (e.g., 4 Kelvin to 77 Kelvin). At these extreme low temperatures, conventional dopant concentrations can lead to carrier freeze-out. To counteract this, the higher p-type impurity concentration in the logic PMIS gate (e.g., achieved with a boron implant at 5 keV, 8E15 cm⁻² dose, followed by a millisecond laser anneal) is optimized to ensure sufficient active carriers and maintain high drive current and low threshold voltage for logic operations. Concurrently, the lower p-type concentration in the SRAM PMIS gate (e.g., boron implant at 5 keV, 2E15 cm⁻² dose) is precisely controlled to minimize subthreshold leakage current, which becomes a dominant factor at cryogenic temperatures due to reduced thermal energy. The entire device is fabricated on a silicon-on-insulator (SOI) substrate to reduce parasitic capacitance and self-heating effects, further enhancing performance at cryogenic conditions.

stateDiagram
    [*] --> Off
    Off --> Cooling: Initiate
    Cooling --> CryogenicReady: T < 77K
    CryogenicReady --> LowPowerCryo: SRAM active
    CryogenicReady --> HighPerformanceCryo: Logic active
    LowPowerCryo --> HighPerformanceCryo: Logic workload
    HighPerformanceCryo --> LowPowerCryo: Standby
    LowPowerCryo --> Thawing: Shut down
    HighPerformanceCryo --> Thawing: Shut down
    Thawing --> Off: Return to ambient

Derivative 3: Cross-Domain Application - Automotive Radar Module with Integrated Processing Units

• Enabling Description: The semiconductor device, featuring the logic/SRAM differential gate doping as per US 8,884,373, is applied in a next-generation automotive radar system-on-chip (SoC). The logic area, which handles real-time radar signal processing (e.g., FFT, beamforming, object detection algorithms) and vehicle control unit (VCU) functions, requires maximum speed and is implemented with PMISFETs utilizing the higher p-type gate impurity concentration (e.g., using boron-doped polysilicon with a concentration of 5x10^20 atoms/cm^3). The integrated SRAM area, used for temporary storage of radar echoes, environmental maps, and lookup tables for autonomous driving, prioritizes low static power consumption and high density. Its PMISFETs are implemented with the lower p-type gate impurity concentration (e.g., 8x10^19 atoms/cm^3), reducing leakage currents. This precise tailoring of gate characteristics within a single SoC optimizes the trade-off between speed and power for critical automotive safety and performance functions.

componentDiagram
    [Radar SoC] --> [RF Transceiver]
    [Radar SoC] --> [ADC/DAC]
    [Radar SoC] --> [Logic Processing Unit (LPU)]
    [Radar SoC] --> [SRAM Memory Block (SMB)]
    [LPU] ..> [High-Conc P-Gate PMISFETs]
    [SMB] ..> [Low-Conc P-Gate PMISFETs]
    [RF Transceiver] -- Data --> [ADC/DAC]
    [ADC/DAC] -- Digital Signal --> [LPU]
    [LPU] -- Data Storage --> [SMB]
    [SMB] -- Read Data --> [LPU]
    [LPU] -- Control --> [Vehicle Control Unit]

Derivative 4: Integration with Emerging Tech - AI-Driven Real-Time Doping Profile Optimization with Blockchain Traceability

• Enabling Description: The fabrication method (Claim 13) is enhanced through integration with an AI-driven real-time optimization system and blockchain for immutable process data logging. During step (b) (introducing first conductivity type impurity) and step (c) (introducing second conductivity type impurity), in-situ process monitoring using advanced sensors (e.g., secondary ion mass spectrometry (SIMS) for real-time dopant profiling or optical emission spectroscopy for plasma composition) provides live data to a deep reinforcement learning (DRL) algorithm. This AI analyzes the observed impurity profiles against target specifications for logic (higher p-type concentration, e.g., 4E15 cm⁻² boron implant) and SRAM (lower p-type concentration, e.g., 1E15 cm⁻² boron implant), factoring in current fab conditions and yield data. The DRL system dynamically adjusts ion implanter parameters (e.g., beam current, scan speed, energy) or plasma doping parameters to correct deviations and maintain optimal differential concentrations. Each adjustment, sensor reading, and process state is securely recorded onto a distributed ledger (blockchain) for complete, auditable traceability from wafer to final product, enhancing quality control and supply chain integrity.

sequenceDiagram
    participant AI as AI/DRL Optimizer
    participant Sensors as In-situ Sensors (SIMS, OES)
    participant Implanter as Ion Implanter / Plasma Doper
    participant Blockchain as Blockchain Ledger

    loop Fabrication Cycle
        Implanter->>Sensors: Apply Doping (Logic/SRAM)
        Sensors->>AI: Real-time Data (Conc. Profile)
        AI->>AI: Analyze vs. Target & Yield Models
        alt Deviation Detected
            AI->>Implanter: Adjust Parameters (Beam Current, Dose)
            Implanter->>Blockchain: Log Adjustment
        else Within Tolerance
            AI->>Blockchain: Log Process State
        end
        Implanter->>Blockchain: Log Final Doping Step
    end

Derivative 5: The "Inverse" or Failure Mode - Low-Power/Limited-Functionality Mode with Deliberate Gate Depletion

• Enabling Description: A semiconductor device incorporating the gate structures of US 8,884,373 is designed with a specific "limited-functionality" or "safe-failure" mode. In this mode, logic PMISFETs that typically have a higher p-type gate impurity concentration (e.g., boron-doped polysilicon) are subjected to a deliberate, controlled reduction in their effective channel doping or an increase in their gate work function during fabrication for specific non-critical logic blocks. This can be achieved by a localized, slightly lighter p-type implant dose (e.g., 2E15 cm⁻² instead of 4E15 cm⁻²) or by applying an additional, very shallow n-type blanket implant post-p-type doping, which partially compensates the p-type gate. This raises the threshold voltage (Vt) of these specific logic PMISFETs, significantly reducing their drive current and static leakage. While their performance is degraded, they consume substantially less power and are more resistant to soft errors, making them suitable for essential supervisory or fail-safe logic functions in a power-constrained or degraded operating environment. Normal high-performance logic PMISFETs retain their higher p-type doping.

stateDiagram
    [*] --> Full_Power_Mode
    Full_Power_Mode --> Low_Power_Standby: Idle / Battery Save
    Low_Power_Standby --> Limited_Functionality_Mode: Critical Event / Low Battery
    Limited_Functionality_Mode --> Full_Power_Mode: Conditions Restore
    Full_Power_Mode --> Safety_Shutdown: Critical Failure
    Limited_Functionality_Mode --> Safety_Shutdown: Imminent Failure

    state Full_Power_Mode {
        High_P_Conc_Logic --> Normal_Operation
        Low_P_Conc_SRAM --> Normal_Operation
    }

    state Limited_Functionality_Mode {
        Reduced_P_Conc_Logic --> Essential_Functions_Only
        Low_P_Conc_SRAM --> Normal_Operation
    }

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Combination Prior Art Scenarios

Here are three scenarios where the teachings of US Patent 8,884,373 are combined with existing open-source standards to create additional prior art.

1. Combination with Open-Source Process Design Kits (PDKs):

   • Scenario: An open-source Process Design Kit (PDK), such as those developed by university consortia or commercial foundries for community use (e.g., SkyWater Technology's 130nm or Google's 180nm open-source PDKs), is augmented to include design rules and process layer definitions for the differential gate doping described in US 8,884,373.
   • Disclosure: The PDK's technology files (.tf) would define new mask layers for "P-type Gate Implant - Logic" and "P-type Gate Implant - SRAM," each associated with specific ion implantation parameters (e.g., dose, energy, tilt angle) and anneal conditions (e.g., RTA temperature and time, or millisecond laser anneal recipes) that yield the higher impurity concentration for logic and lower for SRAM PMISFETs, as disclosed in US 8,884,373. The PDK would also include device models (e.g., SPICE models) reflecting the distinct threshold voltages and performance characteristics of these differentially doped gates, enabling designers to precisely model and leverage the patent's teachings in open-source EDA tools.

   graph TD
       A[US8884373 - Differential Gate Doping] --> B{Open-Source PDK Standard};
       B -- Specifies Layer Definitions (e.g., `IMPLANT_P_LOGIC_HIGH`, `IMPLANT_P_SRAM_LOW`) --> C[PDK Tech Files (.tf)];
       C -- Includes Device Models --> D[SPICE Models for Differentiated Gates];
       D --> E[Open-Source Chip Design Flow];
       E -- Enables Design of --> F[Optimized Logic/SRAM Circuits];
   

2. Combination with Open-Source Electronic Design Automation (EDA) Layout Tools:

   • Scenario: The fabrication method of US 8,884,373 (Claim 13), detailing the use of specific mask patterns for differential impurity introduction, is integrated into an open-source EDA layout tool, such as KLayout or Magic.
   • Disclosure: Custom Python scripts (for KLayout) or Tcl/Tk scripts (for Magic) are developed and released under an open-source license. These scripts allow a layout designer to designate specific polysilicon gate regions as "Logic PMIS Gate" or "SRAM PMIS Gate." Upon execution, the script automatically generates the necessary FIRST_MASK_PATTERN and SECOND_MASK_PATTERN (as defined in Claim 13) layers, ensuring the correct spatial differentiation for impurity implantation. The script would also verify that the generated mask patterns comply with manufacturing design rules, especially concerning the PN boundary placement on isolation regions. This provides a software implementation of the patent's masking methodology, making it accessible for open-source chip development.

   graph TD
       A[US8884373 - Fabrication Method (Claim 13)] --> B{Open-Source EDA Tool (KLayout/Magic)};
       B -- Integrates Custom Scripts (Python/Tcl) --> C[Automated Mask Pattern Generation];
       C -- Defines `FIRST_MASK_PATTERN` & `SECOND_MASK_PATTERN` --> D[Layout Design Files (.gds)];
       D -- Guides --> E[Manufacturing Process for Patent-Claimed Devices];
   

3. Combination with Open-Source High-Level Synthesis (HLS) Frameworks:

   • Scenario: An open-source High-Level Synthesis (HLS) framework (e.g., tools based on LLVM or those used in academic research for hardware compilation) is extended to support architectural synthesis leveraging the device characteristics disclosed in US 8,884,373.
   • Disclosure: The HLS framework is equipped with a technology library that includes parameterized device models derived from US 8,884,373, representing PMISFETs with higher p-type gate concentrations (for logic) and lower p-type gate concentrations (for SRAM). When a designer specifies architectural blocks as "high-performance/high-power" (e.g., a critical path in a CPU) or "low-power/high-density" (e.g., on-chip cache memory), the HLS tool automatically maps these specifications to the corresponding gate types. This means the HLS tool's output (e.g., RTL code or gate-level netlist) will implicitly demand the fabrication process outlined in US 8,884,373 for optimal implementation, guiding subsequent logic synthesis and physical design stages to utilize the differentiated gates effectively.

   graph TD
       A[US8884373 - Differentiated Logic/SRAM Devices] --> B{Open-Source HLS Framework};
       B -- Integrates Tech Library with Device Models --> C[High-Level Design Specification];
       C -- Automates Mapping of Performance/Power Goals --> D[Synthesized Netlist with Optimized Gate Types];
       D -- Facilitates --> E[Fabrication of High-Performance/Low-Power SoCs];