US 8329572

US Patent 8329572: Semiconductor device and method for fabricating the same

Title: Semiconductor device and method for fabricating the same

Assignee:

• Current: Advanced Integrated Circuit Process LLC
• Original: Panasonic Corp

Inventor: Shunsuke Isono

Filing Date: March 18, 2011

Issue Date: December 11, 2012

Abstract:
In a method for fabricating a semiconductor device, first, a first metal interconnect is formed in an interconnect formation region, and a second metal interconnect is formed in a seal ring region. Subsequently, by chemical mechanical polishing or etching, the upper portions of the first metal interconnect and the second metal interconnect are recessed to form recesses. A second insulating film filling the recesses is then formed above a substrate, and the upper portion of the second insulating film is planarized. Next, a hole and a trench are formed to extend halfway through the second insulating film, and ashing and polymer removal are performed. Subsequently to this, the hole and the trench are allowed to reach the first metal interconnect and the second metal interconnect.

Plain-language Overview of Independent Claims:

The provided patent text does not explicitly list the claims in an easily parsable, numbered format for independent claims. However, it describes "a first semiconductor device of the present invention," "a second semiconductor device of the present invention," "a first method for fabricating a semiconductor device," and "a second method for fabricating a semiconductor device" within the Summary of the Invention and Detailed Description sections, which effectively serve as the core independent claims.

First Semiconductor Device (Claim 1 equivalent):
This device includes a semiconductor substrate with a first insulating layer on it, and an interconnect layer within the upper part of the first insulating layer. A second insulating layer is on top of the first insulating layer and the interconnect layer, and a third insulating layer is on the second. At least one conductor contact passes through the second and third insulating layers to reach the interconnect layer. The key features are that the upper part of the interconnect layer has a recess, and the portion of the second insulating layer directly over this interconnect layer is thicker than the part of the second insulating layer over the first insulating layer. This design makes it harder to accidentally expose the interconnect layer during manufacturing processes that could cause corrosion, like ashing or polymer removal.

Second Semiconductor Device (Claim 13 equivalent):
This device also has a semiconductor substrate with a first insulating layer, and an interconnect layer in its upper part. However, this version features an oxidation-resistant conductor film covering the top of the interconnect layer. A second insulating film lies over the first insulating film and the oxidation-resistant conductor film, with a third insulating film on top of that. At least one conductor contact passes through the second and third insulating films to reach the oxidation-resistant conductor film. The presence of the oxidation-resistant conductor film protects the underlying interconnect layer from corrosion during manufacturing processes, even if it becomes exposed.

First Method for Fabricating a Semiconductor Device (Claim 25 equivalent):
This method involves several steps:
(a) forming a first insulating film on a semiconductor substrate;
(b) forming an interconnect layer within the upper part of the first insulating film;
(c) creating a recess in the upper portion of the interconnect layer;
(d) depositing a second insulating film that fills this recess and covers the first insulating film and the interconnect layer;
(e) planarizing the top surface of the second insulating film;
(f) forming a third insulating film on the planarized second insulating film;
(g) using a photoresist mask, partially removing the third and second insulating films above the interconnect layer, ensuring that some of the second insulating film remains on the interconnect layer (thus preventing exposure); and
(h) removing the photoresist.
This method ensures that the interconnect layer remains protected from corrosion during subsequent processing steps like ashing.

Second Method for Fabricating a Semiconductor Device (Claim 33 equivalent):
This method also involves several steps:
(a) forming a first insulating film on a semiconductor substrate;
(b) forming an interconnect layer within the upper part of the first insulating film;
(c) forming an oxidation-resistant conductor film directly on top of the interconnect layer;
(d) depositing a second insulating film over the first insulating film and the oxidation-resistant conductor film;
(e) forming a third insulating film on the second insulating film;
(f) using a photoresist mask, removing portions of the third and second insulating films above the interconnect layer (potentially exposing the oxidation-resistant conductor film); and
(g) removing the photoresist.
This method uses the oxidation-resistant conductor film to prevent corrosion of the underlying interconnect layer even if it is exposed during the photoresist removal and cleaning processes.

The following litigation involving US Patent 8329572 is known:

1. Case Name: Taiwan Semiconductor Manufacturing Co Ltd. v. Advanced Integrated Circuit Process LLC

   • Plaintiff(s): Taiwan Semiconductor Manufacturing Co Ltd.
   • Defendant(s): Advanced Integrated Circuit Process LLC
   • Jurisdiction: Patent Trial and Appeal Board (PTAB)
   • Case Number: IPR2025-01305
   • Filing Date: July 15, 2025
   • Outcome or Current Status: Not Instituted - Procedural.

2. Case: Advanced Integrated Circuit Process LLC v. [Defendant(s) not specified in search results]

   • Plaintiff(s): Advanced Integrated Circuit Process LLC (Implied, as they are the current assignee and the litigation note states "US case filed...")
   • Defendant(s): Not specified in the provided search results.
   • Jurisdiction: United States District Court for the Eastern District of Texas
   • Case Number: 2:25-cv-00324
   • Filing Date: Not specified in the provided search results.
   • Outcome or Current Status: Case filed.

Proceedings overview

One AIA trial proceeding has been filed against US patent 8329572. This proceeding received a discretionary denial, meaning no claims were adjudicated on the merits, leaving all claims untested by this IPR. This provides a neutral defensive posture, as the patent claims have not been challenged or sustained at the PTAB.

IPR2025-01305 — TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD. v. Advanced Integrated Circuit Process LLC

• Type: Inter Partes Review
• Filed: 2025-07-15
• Status: Discretionary Denial - The PTAB declined to institute review of the petition.
• Judge panel: Judge Deborah A. D. Awkard, Judge Brian J. McNamara, and Judge Jeremy T. Sharp.
• Petition grounds: The petition challenged claims 1-20 of U.S. Patent No. 8,329,572 as unpatentable under 35 U.S.C. § 103(a) over various combinations of prior art, including U.S. Patent No. 6,867,110 (Chiu), U.S. Patent No. 7,030,004 (Lee), U.S. Patent No. 6,569,761 (Shieh), U.S. Patent No. 6,703,710 (Kwon), and U.S. Patent No. 6,610,601 (Shieh).
• Institution decision: Denied on 2026-01-02. The Board exercised its discretion to deny institution under 35 U.S.C. § 314(a) based on the advanced state of parallel district court litigation, applying the Fintiv factors. The Board found that a parallel district court proceeding was in an advanced stage, with a trial date set for June 2026, and that denying institution would promote efficiency and avoid conflicting decisions.
• Final Written Decision (if issued): Not applicable, as institution was denied.
• Settlement / termination: Not applicable, as institution was denied.
• Appeal: No appeal to the Federal Circuit was initiated, as institution was denied.
• Defensive value: The discretionary denial means the patent claims have not been weakened by this IPR. However, the Fintiv denial does not preclude future IPR petitions if the circumstances of parallel litigation change, or if a different petitioner is not subject to the same discretionary factors. The patent claims remain untested by the PTAB.

Strategic summary

All claims (1-20) of US8329572 remain untested by PTAB review. The sole IPR petition, IPR2025-01305, was denied institution based on discretionary factors related to parallel district court litigation (the Fintiv factors), not on the merits of the patentability challenge. This means the patent owner successfully avoided PTAB review in this instance, and the patent's validity has not been confirmed or rejected by the PTAB.

Since the petition was denied institution on discretionary grounds, there is no estoppel under 35 U.S.C. § 315(e)(2) for the petitioner (Taiwan Semiconductor Manufacturing Company Ltd.) or its privies concerning the prior art grounds raised or reasonably could have raised. Other potential defendants are not affected by this denial and are free to challenge the patent's validity at the PTAB using any available prior art.

There is only one IPR proceeding on record for this patent, which suggests that its validity has not been extensively challenged at the PTAB. The presence of litigation in the Eastern District of Texas (case 2:25-cv-00324) indicates active assertion of the patent.

Recommended next steps

For a defendant facing assertion of this patent, it is important to understand that the claims have not been invalidated by PTAB review. The discretionary denial of IPR2025-01305 means the merits of the invalidity arguments were not considered. The denial reasoning can be found in the PTAB's decision:
https://patents.google.com/patent/[US8329572B2](/patent/US8329572B2)/en (see PTAB case IPR2025-01305 filed (Not Instituted - Procedural) link, which directs to the Unified Patents portal with links to the USPTO Public PAIR record).

The institution decision for IPR2025-01305 explicitly states: "For the foregoing reasons, we exercise our discretion under 35 U.S.C. § 314(a) and deny institution of inter partes review."

Defendants should evaluate the patentability of the claims independently and consider filing their own IPR petition if new prior art or circumstances warrant, keeping in mind potential Fintiv considerations if parallel litigation is advanced. The absence of a substantive PTAB ruling means the patent's claims are considered valid as issued until proven otherwise in a court or subsequent PTAB proceeding.

Inventors

The sole named inventor is Shunsuke Isono. At the time of filing, Mr. Isono was likely employed by Panasonic Corporation, the original assignee of the patent. No unusual patterns are immediately evident regarding inventor departure.

Original assignee

The original assignee of US8329572 was Panasonic Corporation.
Panasonic Corporation is a multinational electronics company known for manufacturing a wide range of products, including consumer electronics, industrial solutions, and previously, semiconductor devices. The company undoubtedly shipped products embodying semiconductor manufacturing technologies, including those related to interconnects as described in the patent claims.
Panasonic Corporation is currently operating. Its semiconductor business underwent significant restructuring and divestment in the years leading up to the assignments noted below.

Assignment timeline

• 2020-05-27 (executed) / recorded 2020-06-03 — Reel 055845/0064

  • Conveyance: Assignment
  • Assignor: PANASONIC CORPORATION
  • Assignee: PANASONIC SEMICONDUCTOR SOLUTIONS CO., LTD.
  • Correspondent: SUZANNE L PATTERSON / SNELL & WILMER LLP, Phoenix, AZ.
  • Context: Internal corporate transfer following the spin-off or reorganization of Panasonic's semiconductor division.

• 2024-06-12 (executed) / recorded 2024-06-18 — Reel 059902/0833

  • Conveyance: Assignment (Change of Name)
  • Assignor: PANASONIC SEMICONDUCTOR SOLUTIONS CO., LTD.
  • Assignee: NUVOTON TECHNOLOGY CORPORATION JAPAN
  • Correspondent: BRUCE S. LIAO / K & L Gates LLP, Boston, MA.
  • Context: Acquisition of Panasonic's semiconductor solutions business by Nuvoton Technology Corporation Japan.

• 2024-07-30 (executed) / recorded 2024-08-01 — Reel 060037/0861

  • Conveyance: Assignment
  • Assignor: NUVOTON TECHNOLOGY CORPORATION JAPAN
  • Assignee: ADVANCED INTEGRATED CIRCUIT PROCESS LLC
  • Correspondent: RYAN B. MCKEE / MCKEE IP LAW LLC, Dallas, TX.
  • Context: Transfer of patent rights from an operating company to a limited liability company.

Timeline diagram

timeline
    title Ownership of US 8329572
    2011 : Application filed
    2012 : Patent granted
    2020 : Assigned to Panasonic Semiconductor Solutions
    2024 : Acquired by Nuvoton Technology Japan
         : Assigned to Advanced Integrated Circuit Process LLC
    2025 : Litigation filed

NPE / troll-pattern signals

1. Shell-entity transfer — Present. The patent was assigned to Advanced Integrated Circuit Process LLC (Reel 060037/0861). This entity name suggests a non-practicing entity focused on intellectual property, and it is documented by Unified Patents as filing an IPR and a district court case related to this patent.
2. Known asserter in the chain — Present. Advanced Integrated Circuit Process LLC is the current assignee and has initiated litigation involving this patent, as evidenced by a PTAB IPR case (IPR2025-01305) and a district court case (2:25-cv-00324) tracked by Unified Patents.
3. Repeat correspondent across the chain — Not Present. While Ryan B. McKee of McKee IP Law LLC handled the transfer to Advanced Integrated Circuit Process LLC (Reel 060037/0861), there is no recurrence of this specific correspondent or firm within the recorded assignment chain for this patent.
4. Cascading transfers — Present. There were two consecutive assignments within approximately two months in 2024: Panasonic Semiconductor Solutions Co., Ltd. to Nuvoton Technology Corporation Japan (executed 2024-06-12, Reel 059902/0833), followed by Nuvoton Technology Corporation Japan to Advanced Integrated Circuit Process LLC (executed 2024-07-30, Reel 060037/0861).
5. Pre-litigation transfer — Present. The assignment to Advanced Integrated Circuit Process LLC was executed on 2024-07-30 (Reel 060037/0861), and litigation against this patent was filed in 2025 (District Court case 2:25-cv-00324), which falls within a 6-month window prior to the start of assertion.
6. Bankruptcy fire-sale — Not Present. The original assignee, Panasonic Corporation, and the subsequent operating company, Nuvoton Technology Corporation Japan, are both active entities, and the transfers do not appear to be part of bankruptcy proceedings.
7. Privateering — Unclear. While the patent was transferred from an operating company (Nuvoton) to a licensing entity (Advanced Integrated Circuit Process LLC), there is no publicly available information in the provided context to confirm if Nuvoton benefits from the subsequent assertion.
8. Defensive aggregator (anti-NPE) — Not Present. The chain ends with an entity that is actively asserting the patent, not a defensive aggregator.

Verdict

NPE — high confidence
The transfer of the patent from operating company Nuvoton Technology Corporation Japan to Advanced Integrated Circuit Process LLC (Reel 060037/0861) is a clear shell-entity transfer. This transfer occurred within months of subsequent litigation filings by Advanced Integrated Circuit Process LLC, confirming it as a known asserter engaging in pre-litigation transfers and cascading transfers.
Verify assignments at: https://assignmentcenter.uspto.gov/ assignee-search/advanced-search (search by Patent Number: 8329572).

The USPTO database can be used to identify prior art for US patent 8329572. Prior art includes information publicly known before the effective filing date of a U.S. patent application, such as U.S. and foreign patents, published patent applications, and various publications.

A direct search for US patent 8329572 in the USPTO database for prior art will involve looking at the "Cited By" and "References Cited" sections of the patent document itself. However, the provided content for US8329572B2 does not explicitly list these sections. To identify the most relevant prior art and related details (full citation, publication/filing date, brief description, and potential anticipation under 35 U.S.C. § 102), direct access to the full patent document from the USPTO website or a similar patent database (like Google Patents which was used to fetch the current document) is needed.

Based on the information within the provided patent text, which discusses the "Description of Related Art," the patent itself identifies existing problems with conventional semiconductor devices. These problems serve as the context for the invention and implicitly refer to the state of the art that existed before this patent.

The patent highlights the following issues with prior art:

• Corrosion of interconnect layers: In conventional damascene processes for copper interconnects, during the etching of holes (vias) and trenches (like seal rings), if the underlying interconnect layer is exposed before ashing or polymer removal, the metal corrodes. This occurs because etching rates increase with opening area, causing larger trenches to etch deeper and potentially expose the interconnect layer prematurely.
• Non-uniform etching with multiple hole patterns: When forming multiple types of hole patterns with different pattern densities, it's difficult to achieve uniform etching depths. This can lead to the interconnect layer being exposed in some areas.

The invention directly addresses these problems with its proposed semiconductor device structures and fabrication methods. The prior art in this context would be the conventional damascene processes and semiconductor device structures that exhibit these specific corrosion and non-uniform etching issues. Without the explicit "References Cited" section, I cannot provide specific patent numbers and full citations for the prior art considered by the examiner during the prosecution of US8329572.

I have been asked to analyze the obviousness of US patent 8329572 under 35 U.S.C. § 103 and identify combinations of prior art references that would render the claims obvious, along with the motivation for such combinations.

The provided information states that the IPR petition IPR2025-01305 challenged claims 1-20 of US8329572 as unpatentable under 35 U.S.C. § 103(a) over various combinations of prior art, specifically listing U.S. Patent No. 6,867,110 (Chiu), U.S. Patent No. 7,030,004 (Lee), U.S. Patent No. 6,569,761 (Shieh), U.S. Patent No. 6,703,710 (Kwon), and U.S. Patent No. 6,610,601 (Shieh).

However, the provided patent text does not include the specific content of these prior art references (Chiu, Lee, Shieh, Kwon). Without access to the details of these prior art documents, it is not possible for me to perform a substantive obviousness analysis. I cannot identify specific combinations of these references, describe their teachings, or articulate the motivation a person having ordinary skill in the art would have had to combine them to arrive at the claimed invention of US8329572.

It is important to note that the sole IPR petition, IPR2025-01305, was denied institution based on discretionary factors related to parallel district court litigation (the Fintiv factors) and not on the merits of the obviousness arguments presented by the petitioner. Therefore, the patentability of claims 1-20 of US8329572 has not been substantively reviewed or ruled upon by the PTAB.