US 7579227

Here's a concise summary of US Patent 7579227, incorporating information from the provided patent text and the current date of April 26, 2026.

US Patent 7579227 Summary

• Title: Semiconductor device and method for fabricating the same
• Current Assignee: Advanced Integrated Circuit Process LLC (as of 2024-07-30)
• Original Assignee: Panasonic Corp (as of filing date)
• Inventors: Junji Hirase, Akio Sebe, Naoki Kotani, Gen Okazaki, Kazuhiko Aida, Shinji Takeoka
• Filing Date: July 24, 2006
• Issue Date: August 25, 2009
• Abstract: A semiconductor device includes a high dielectric constant gate insulating film formed on an active region in a substrate, a gate electrode formed on this film, and an insulating sidewall on each side of the gate electrode. The key feature is that the high dielectric constant gate insulating film extends continuously from under the gate electrode to under the insulating sidewall, and at least the part under the insulating sidewall is thinner than the part under the gate electrode.

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Plain-Language Overview of Independent Claims:

The provided patent text includes general descriptions of the invention and its various embodiments, but does not explicitly list the numbered claims. Therefore, I will derive the plain-language overview from the "SUMMARY OF THE INVENTION" section which explicitly states what the semiconductor device and method for fabricating it "according to the present invention includes."

Independent Device Claims (derived from "SUMMARY OF THE INVENTION"):

1. A semiconductor device comprising:

   • A high dielectric constant gate insulating film on an active region of a substrate.
   • A gate electrode on the high dielectric constant gate insulating film.
   • An insulating sidewall on each side surface of the gate electrode.
   • The high dielectric constant gate insulating film is continuous, extending from under the gate electrode to under the insulating sidewall.
   • At least the portion of the high dielectric constant gate insulating film located under the insulating sidewall has a smaller thickness than the portion under the gate electrode.

   (Further variations described in the summary imply additional independent or dependent claims related to sidewall configurations and film thickness profiles, but without the explicit claim text, these are presented as sub-points of the main device concept.)

   • The insulating sidewall may include a first insulating sidewall and a second insulating sidewall (where the first is closer to the gate, and the second is further out).
     • The high dielectric constant gate insulating film may continuously extend from under the gate electrode to under the first insulating sidewall, with the part under the first insulating sidewall being thinner than under the gate electrode.
     • In this two-sidewall configuration, the high dielectric constant gate insulating film may not be located under the second insulating sidewall.
     • Alternatively, it may extend to under the second insulating sidewall, with the part under the second sidewall having the same thickness as under the first sidewall.
     • Or, it may extend to under the second sidewall, with the part under the second sidewall being even thinner than under the first sidewall.
     • Another option for the two-sidewall configuration is that the high dielectric constant gate insulating film under the first sidewall has the same thickness as under the gate electrode, while the part under the second sidewall is thinner than under the gate electrode.
   • The high dielectric constant gate insulating film may feature a notch at its side end portion.
   • The device may also include a buffer insulating film (e.g., silicon oxide or silicon oxynitride) between the substrate and the high dielectric constant gate insulating film.
   • The gate electrode may be a fully silicided gate electrode.

Independent Method Claims (derived from "SUMMARY OF THE INVENTION"):

1. A method for fabricating a semiconductor device, comprising the steps of:

   • a) Forming a high dielectric constant gate insulating film on an active region of a substrate.
   • b) Forming a gate electrode on the high dielectric constant gate insulating film.
   • c) After step (b), etching the part of the high dielectric constant gate insulating film external to the gate electrode to reduce its thickness.
   • d) After step (c), forming an insulating sidewall on a side surface of the gate electrode.

   (Further variations described in the summary imply additional independent or dependent claims related to sidewall formation and film removal/etching steps.)

   • After step (d), the method may further include removing the part of the high dielectric constant gate insulating film located external to the insulating sidewall.
   • If the insulating sidewall includes a first and second sidewall, step (d) would involve:
     • d1) Forming the first insulating sidewall on the gate electrode side surface.
     • d2) Forming the second insulating sidewall with the first sidewall interposed.
   • In the two-sidewall method, between steps (d1) and (d2), the method may include removing the part of the high dielectric constant gate insulating film external to the first insulating sidewall.
   • Alternatively, between steps (d1) and (d2), the method may include etching the external part of the high dielectric gate insulating film to reduce its thickness, and after (d2), removing the part external to the second insulating sidewall.
   • The dielectric constant gate insulating film may be selectively removed by wet etching.
   • Step (b) may include forming a protective film over the gate electrode, and after step (d), the method may further include siliciding the surface of the active region external to the insulating sidewall, removing the protective film, and then fully siliciding the gate electrode.
   • Before step (a), a buffer insulating film may be formed on the active region, with the high dielectric constant gate insulating film then formed on this buffer layer.

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USPTO and CAFC Dockets Search Results:

The Google Patents information provided with the prompt already indicates that the patent is "Active, expires 2027-03-27" and that "Family has litigation," with several specific litigation cases listed (e.g., US case filed in Texas Eastern District Court, PTAB cases IPR2025-01076 and IPR2025-00828).

Searching "USPTO 7579227" confirms the information already present in the prompt (title, inventors, assignee, dates). No new conflicting information was found.

Searching "CAFC 2026 dockets 7579227" did not directly return specific docket entries for patent 7579227 in 2026. The search results provide general information on how to access scheduled cases, case filings, and records from the U.S. Court of Appeals for the Federal Circuit. While the patent is noted to have ongoing litigation (including PTAB cases and district court cases in Texas Eastern District Court), there is no explicit mention in the immediate CAFC search results of it being currently scheduled for oral argument or having specific docket entries in CAFC 2026 dockets at this moment. Accessing specific historical or ongoing CAFC dockets would typically require searching their case records system (like PACER for cases after March 1, 2012).

Uncertainty Note: While the patent text indicates active litigation, the provided CAFC search results do not definitively confirm any currently active CAFC dockets for 2026 directly linked to patent 7579227 without deeper searching into the CAFC's case records system. The general CAFC results point to how one would search for such information (e.g., via scheduled cases or case records).