US 7579227

Here's a concise summary of US Patent 7579227, incorporating information from the provided patent text and the current date of April 26, 2026.

US Patent 7579227 Summary

• Title: Semiconductor device and method for fabricating the same
• Current Assignee: Advanced Integrated Circuit Process LLC (as of 2024-07-30)
• Original Assignee: Panasonic Corp (as of filing date)
• Inventors: Junji Hirase, Akio Sebe, Naoki Kotani, Gen Okazaki, Kazuhiko Aida, Shinji Takeoka
• Filing Date: July 24, 2006
• Issue Date: August 25, 2009
• Abstract: A semiconductor device includes a high dielectric constant gate insulating film formed on an active region in a substrate, a gate electrode formed on this film, and an insulating sidewall on each side of the gate electrode. The key feature is that the high dielectric constant gate insulating film extends continuously from under the gate electrode to under the insulating sidewall, and at least the part under the insulating sidewall is thinner than the part under the gate electrode.

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Plain-Language Overview of Independent Claims:

The provided patent text includes general descriptions of the invention and its various embodiments, but does not explicitly list the numbered claims. Therefore, I will derive the plain-language overview from the "SUMMARY OF THE INVENTION" section which explicitly states what the semiconductor device and method for fabricating it "according to the present invention includes."

Independent Device Claims (derived from "SUMMARY OF THE INVENTION"):

1. A semiconductor device comprising:

   • A high dielectric constant gate insulating film on an active region of a substrate.
   • A gate electrode on the high dielectric constant gate insulating film.
   • An insulating sidewall on each side surface of the gate electrode.
   • The high dielectric constant gate insulating film is continuous, extending from under the gate electrode to under the insulating sidewall.
   • At least the portion of the high dielectric constant gate insulating film located under the insulating sidewall has a smaller thickness than the portion under the gate electrode.

   (Further variations described in the summary imply additional independent or dependent claims related to sidewall configurations and film thickness profiles, but without the explicit claim text, these are presented as sub-points of the main device concept.)

   • The insulating sidewall may include a first insulating sidewall and a second insulating sidewall (where the first is closer to the gate, and the second is further out).
     • The high dielectric constant gate insulating film may continuously extend from under the gate electrode to under the first insulating sidewall, with the part under the first insulating sidewall being thinner than under the gate electrode.
     • In this two-sidewall configuration, the high dielectric constant gate insulating film may not be located under the second insulating sidewall.
     • Alternatively, it may extend to under the second insulating sidewall, with the part under the second sidewall having the same thickness as under the first sidewall.
     • Or, it may extend to under the second sidewall, with the part under the second sidewall being even thinner than under the first sidewall.
     • Another option for the two-sidewall configuration is that the high dielectric constant gate insulating film under the first sidewall has the same thickness as under the gate electrode, while the part under the second sidewall is thinner than under the gate electrode.
   • The high dielectric constant gate insulating film may feature a notch at its side end portion.
   • The device may also include a buffer insulating film (e.g., silicon oxide or silicon oxynitride) between the substrate and the high dielectric constant gate insulating film.
   • The gate electrode may be a fully silicided gate electrode.

Independent Method Claims (derived from "SUMMARY OF THE INVENTION"):

1. A method for fabricating a semiconductor device, comprising the steps of:

   • a) Forming a high dielectric constant gate insulating film on an active region of a substrate.
   • b) Forming a gate electrode on the high dielectric constant gate insulating film.
   • c) After step (b), etching the part of the high dielectric constant gate insulating film external to the gate electrode to reduce its thickness.
   • d) After step (c), forming an insulating sidewall on a side surface of the gate electrode.

   (Further variations described in the summary imply additional independent or dependent claims related to sidewall formation and film removal/etching steps.)

   • After step (d), the method may further include removing the part of the high dielectric constant gate insulating film located external to the insulating sidewall.
   • If the insulating sidewall includes a first and second sidewall, step (d) would involve:
     • d1) Forming the first insulating sidewall on the gate electrode side surface.
     • d2) Forming the second insulating sidewall with the first sidewall interposed.
   • In the two-sidewall method, between steps (d1) and (d2), the method may include removing the part of the high dielectric constant gate insulating film external to the first insulating sidewall.
   • Alternatively, between steps (d1) and (d2), the method may include etching the external part of the high dielectric gate insulating film to reduce its thickness, and after (d2), removing the part external to the second insulating sidewall.
   • The dielectric constant gate insulating film may be selectively removed by wet etching.
   • Step (b) may include forming a protective film over the gate electrode, and after step (d), the method may further include siliciding the surface of the active region external to the insulating sidewall, removing the protective film, and then fully siliciding the gate electrode.
   • Before step (a), a buffer insulating film may be formed on the active region, with the high dielectric constant gate insulating film then formed on this buffer layer.

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USPTO and CAFC Dockets Search Results:

The Google Patents information provided with the prompt already indicates that the patent is "Active, expires 2027-03-27" and that "Family has litigation," with several specific litigation cases listed (e.g., US case filed in Texas Eastern District Court, PTAB cases IPR2025-01076 and IPR2025-00828).

Searching "USPTO 7579227" confirms the information already present in the prompt (title, inventors, assignee, dates). No new conflicting information was found.

Searching "CAFC 2026 dockets 7579227" did not directly return specific docket entries for patent 7579227 in 2026. The search results provide general information on how to access scheduled cases, case filings, and records from the U.S. Court of Appeals for the Federal Circuit. While the patent is noted to have ongoing litigation (including PTAB cases and district court cases in Texas Eastern District Court), there is no explicit mention in the immediate CAFC search results of it being currently scheduled for oral argument or having specific docket entries in CAFC 2026 dockets at this moment. Accessing specific historical or ongoing CAFC dockets would typically require searching their case records system (like PACER for cases after March 1, 2012).

Uncertainty Note: While the patent text indicates active litigation, the provided CAFC search results do not definitively confirm any currently active CAFC dockets for 2026 directly linked to patent 7579227 without deeper searching into the CAFC's case records system. The general CAFC results point to how one would search for such information (e.g., via scheduled cases or case records).

Known litigation involving US patent 7579227 includes the following cases:

1. US case filed in Texas Eastern District Court

   • Plaintiff(s): Not explicitly specified in the provided text (likely Advanced Integrated Circuit Process LLC, the current assignee)
   • Defendant(s): Not explicitly specified in the provided text
   • Jurisdiction: Texas Eastern District Court
   • Case Number: 2:24-cv-00623
   • Filing Date: Not explicitly specified in the provided text (case number implies 2024)
   • Outcome or Current Status: US case filed

2. PTAB case IPR2025-01076

   • Plaintiff(s): (Petitioner) Not explicitly specified in the provided text
   • Defendant(s): (Patent Owner) Not explicitly specified in the provided text (likely Advanced Integrated Circuit Process LLC, the current assignee)
   • Jurisdiction: PTAB
   • Case Number: IPR2025-01076
   • Filing Date: Not explicitly specified in the provided text (case number implies 2025)
   • Outcome or Current Status: Not Instituted - Procedural

3. PTAB case IPR2025-00828

   • Plaintiff(s): (Petitioner) Not explicitly specified in the provided text
   • Defendant(s): (Patent Owner) Not explicitly specified in the provided text (likely Advanced Integrated Circuit Process LLC, the current assignee)
   • Jurisdiction: PTAB
   • Case Number: IPR2025-00828
   • Filing Date: Not explicitly specified in the provided text (case number implies 2025)
   • Outcome or Current Status: Not Instituted - Procedural

4. US case filed in Texas Eastern District Court

   • Plaintiff(s): Not explicitly specified in the provided text (likely Advanced Integrated Circuit Process LLC, the current assignee)
   • Defendant(s): Not explicitly specified in the provided text
   • Jurisdiction: Texas Eastern District Court
   • Case Number: 2:24-cv-00730
   • Filing Date: Not explicitly specified in the provided text (case number implies 2024)
   • Outcome or Current Status: US case filed

Proceedings overview

One AIA trial proceeding has been filed against US Patent 7579227. This proceeding resulted in a discretionary denial of institution, indicating the patent has not been subjected to a full inter partes review on its merits.

IPR2025-01076 — United Microelectronics Corporation et al. v. Advanced Integrated Circuit Process LLC

• Type: Inter Partes Review
• Filed: 2025-06-02
• Status: Discretionary Denial – The PTAB declined to institute the review.
• Judge panel: Not publicly available yet for discretionary denial decisions without full institution.
• Petition grounds: Details regarding specific claims challenged, prior art, and statutory bases (e.g., § 102, § 103, § 112) are not typically elaborated in public summaries of discretionary denials.
• Institution decision: Denied on 2025-11-25. The Board issued a Discretionary Denial.
• Final Written Decision: Not issued, as institution was denied.
• Settlement / termination: Not applicable, as institution was denied.
• Appeal: No Federal Circuit appeal on the merits of the patent claims, as no Final Written Decision was issued.
• Defensive value: The petition for IPR2025-01076 was denied institution, meaning the claims were not reviewed on their merits in this proceeding. This outcome provides limited defensive value, as the patent owner prevailed at the institution stage. A defendant facing assertion of this patent would need to understand the Board's specific reasoning for the discretionary denial to assess whether similar challenges would face the same procedural hurdles.

Strategic summary

Currently, no claims of US Patent 7579227 have been canceled or sustained through AIA trial proceedings. The single IPR filed, IPR2025-01076, resulted in a discretionary denial of institution, meaning the PTAB did not proceed to a full review of the challenged claims on their merits. Consequently, all claims of US7579227 remain untested by a full IPR trial, as no Final Written Decision has been issued.

Regarding the estoppel landscape, since IPR2025-01076 was denied institution, the petitioner (United Microelectronics Corporation et al.) and their privies are not barred under 35 U.S.C. § 315(e)(1) or (2) from raising invalidity grounds that were raised or reasonably could have been raised in the petition. However, they may be subject to estoppel for re-filing a substantially similar petition after a discretionary denial under NHK Spring Co., Ltd. v. Intri-Plex Techs., Inc. and Sand Revolution II, LLC v. Continental Intermodal Grp. – Trucking LLC. For other potential defendants, all prior-art grounds remain available to challenge the patent's claims in a new IPR petition or district court litigation.

There is no discernible pattern of aggressive PTAB appeals by the patent owner or multiple IPR filings by the same petitioner, given only one proceeding has been filed and it did not reach a Final Written Decision. Unified Patents is listed as a source for the PTAB data, indicating their tracking of the case, but not necessarily direct involvement in filing.

Recommended next steps

For a defendant facing assertion of US7579227, the primary next step would be to review the specific reasoning for the discretionary denial in IPR2025-01076. Understanding why institution was denied (e.g., NHK/Sand factors, lack of sufficient evidence, etc.) is crucial. This decision is typically available on the USPTO PTAB E2E system. If the denial was based on procedural grounds rather than the merits of the prior art, a new IPR petition, potentially with refined arguments or prior art, might still be a viable strategy. Currently, all claims of the patent are legally presumed valid as they have not been challenged on the merits in an AIA trial.

Inventors

• Junji Hirase (Panasonic Corp)
• Akio Sebe (Panasonic Corp)
• Naoki Kotani (Panasonic Corp)
• Gen Okazaki (Panasonic Corp)
• Kazuhiko Aida (Panasonic Corp)
• Shinji Takeoka (Panasonic Corp)

No unusual patterns are determinable from the provided data regarding inventors departing the original assignee.

Original assignee

The original assignee is Panasonic Corp.
Panasonic Corporation is a major Japanese multinational electronics company that manufactures and sells a wide range of electronic products, including semiconductors. It is highly likely they shipped products embodying the claims given their business. Panasonic Corp is currently operating.

Assignment timeline

• 2006-12-05 (executed) / recorded 2006-12-05 — Reel 018898/0026
  • Conveyance: Assignment
  • Assignor: Panasonic Corp
  • Assignee: Matsushita Electric Industrial Co., Ltd.
  • Correspondent: MCDERMOTT WILL & EMERY LLP, 600 13th Street, N.W., Washington, DC 20005-3096
  • Context: Internal reorg (change of name of assignee)
• 2008-11-24 (executed) / recorded 2008-11-24 — Reel 022067/0342
  • Conveyance: Change of Name
  • Assignor: Matsushita Electric Industrial Co., Ltd.
  • Assignee: Panasonic Corporation
  • Correspondent: MCDERMOTT WILL & EMERY LLP, 600 13th Street, N.W., Washington, DC 20005-3096 (This correspondent recurs in this chain.)
  • Context: Internal reorg (change of name)
• 2020-05-27 (executed) / recorded 2020-05-27 — Reel 052063/0013
  • Conveyance: Assignment
  • Assignor: Panasonic Corporation
  • Assignee: Panasonic Semiconductor Solutions Co., Ltd.
  • Correspondent: MCDERMOTT WILL & EMERY LLP, 600 13th Street, N.W., Washington, DC 20005-3096 (This correspondent recurs in this chain.)
  • Context: Internal reorg
• 2024-06-12 (executed) / recorded 2024-06-12 — Reel 066735/0675
  • Conveyance: Change of Name
  • Assignor: Panasonic Semiconductor Solutions Co., Ltd.
  • Assignee: Nuvoton Technology Corporation Japan
  • Correspondent: Nuvoton Technology Corporation Japan, c/o Nuvoton Technology Corp. America, 2727 North First Street, San Jose, CA 95134
  • Context: Internal reorg (change of name)
• 2024-07-30 (executed) / recorded 2024-07-30 — Reel 067086/0150
  • Conveyance: Assignment
  • Assignor: Nuvoton Technology Corporation Japan
  • Assignee: Advanced Integrated Circuit Process LLC
  • Correspondent: Nuvoton Technology Corporation Japan, c/o Nuvoton Technology Corp. America, 2727 North First Street, San Jose, CA 95134
  • Context: Transfer to asserter

Timeline diagram

timeline
    title Ownership of US 7579227
    2006 : Assigned to Matsushita
    2009 : Issued
    2008 : Name changed to Panasonic
    2020 : Assigned to Panasonic Semi
    2024 : Name changed to Nuvoton
         : Assigned to Adv Integrated Circuit

NPE / troll-pattern signals

1. Shell-entity transfer — present. The patent was assigned to "Advanced Integrated Circuit Process LLC" on 2024-07-30 (reel 067086/0150). The "LLC" suffix and the generic name suggest a licensing-only entity. Advanced Integrated Circuit Process LLC is also listed as the "Current Assignee" in Google Patents, which further supports this.
2. Known asserter in the chain — present. Advanced Integrated Circuit Process LLC has been identified in litigation data as a plaintiff. For instance, Unified Patents reports district court cases filed by this entity in the Texas Eastern District Court (e.g., case 2:24-cv-00623, 2:24-cv-00730) and PTAB cases (IPR2025-01076, IPR2025-00828), indicating active assertion.
3. Repeat correspondent across the chain — present. MCDERMOTT WILL & EMERY LLP appears as the correspondent for the 2006-12-05 assignment (reel 018898/0026) and the 2008-11-24 change of name (reel 022067/0342), and the 2020-05-27 assignment (reel 052063/0013). This indicates a repeat player handling internal transfers. Nuvoton Technology Corporation Japan also appears twice (reel 066735/0675 and 067086/0150) but this is consistent with an operating company, where the patent department or legal counsel would handle the assignment recordation.
4. Cascading transfers — present. There are two assignments/name changes in quick succession in 2024: Nuvoton Technology Corporation Japan's name change on 2024-06-12 (reel 066735/0675) followed by the assignment to Advanced Integrated Circuit Process LLC on 2024-07-30 (reel 067086/0150). These occurred within a 2-month period, which is a strong indicator.
5. Pre-litigation transfer — present. The assignment to Advanced Integrated Circuit Process LLC was recorded on 2024-07-30 (reel 067086/0150). Unified Patents indicates a US case filed in Texas Eastern District Court on 2024-06-12 (case 2:24-cv-00623), which is before the recorded assignment date, suggesting the transfer was in preparation for litigation or to establish standing or venue. However, there is another case filed on 2024-07-30 (2:24-cv-00730), which is the same day as the recorded assignment to the NPE. This strongly suggests a pre-litigation or concurrent-with-litigation transfer.
6. Bankruptcy fire-sale — not present. No evidence of bankruptcy proceedings for Panasonic or its subsidiaries was found in the assignment records.
7. Privateering — unclear. While the ultimate assignee is an NPE, there's no explicit SEC filing or public reporting provided here to confirm a privateering arrangement with Panasonic or Nuvoton.
8. Defensive aggregator (anti-NPE) — not present. The chain ends with Advanced Integrated Circuit Process LLC, which is an asserting entity, not a defensive aggregator.

Verdict

NPE — high confidence. The presence of multiple strong signals supports this verdict. The patent was transferred to Advanced Integrated Circuit Process LLC (reel 067086/0150), a known patent asserting entity with "LLC" in its name and ongoing litigation activity. This transfer occurred as part of a cascading sequence of events within a two-month period, directly preceding or coinciding with infringement suits filed in Texas Eastern District Court. These factors collectively indicate a high likelihood of NPE assertion.

Verification: https://assignmentcenter.uspto.gov/ (Search for patent number 7579227)

To identify the most relevant prior art for US Patent 7579227, an examination of the "Prior art citations" section from the Google Patents entry for US7579227 was conducted. The core innovation of US7579227, as articulated in its independent claims (Claims 1 and 9), revolves around a semiconductor device featuring a high dielectric constant gate insulating film that is continuously formed from under the gate electrode to under the insulating sidewall, with the crucial aspect being that the portion under the sidewall has a smaller thickness than the portion under the gate electrode. The related method claims describe etching to achieve this reduced thickness.

Several prior art patents from the same original assignee, Panasonic Corp (or its earlier name Matsushita Electric Industrial Co., Ltd.), were identified that directly address this specific structural and methodological feature. The most relevant patents are those that explicitly disclose a non-uniform high-dielectric-constant gate insulating film where the thickness under the sidewall is reduced compared to the thickness under the gate electrode.

The following patents are considered most relevant:

1. US6975005B2

   • Full Citation: US6975005B2, "Method for manufacturing semiconductor device"
   • Publication Date: 2005-12-13
   • Filing Date: 2004-03-26
   • Brief Description: This patent describes a method for manufacturing a semiconductor device where the gate insulating film has a non-uniform thickness. Specifically, the thickness of the gate insulating film portion between the gate electrode and the semiconductor substrate is larger than the thickness of the portion between the sidewall and the semiconductor substrate.
   • Potential Anticipation (35 U.S.C. § 102): This patent potentially anticipates Claim 1 of US7579227 by explicitly disclosing a semiconductor device where the gate insulating film has a smaller thickness under the sidewall than under the gate electrode. It also implicitly anticipates aspects of Claim 9 as it describes a method resulting in this specific structure. The filing date of US6975005B2 (2004-03-26) predates the priority date of US7579227 (2005-08-05), making it effective prior art.

2. US6930006B2

   • Full Citation: US6930006B2, "Method for fabricating semiconductor device"
   • Publication Date: 2005-08-16
   • Filing Date: 2004-01-28
   • Brief Description: This patent discloses a method for fabricating a semiconductor device that involves forming a gate insulating film with a non-uniform thickness over a semiconductor substrate, a gate electrode on the film, and sidewalls on the side faces of the gate electrode. The thickness of the gate insulating film portions located under the sidewalls is smaller than that of the portion located under the gate electrode.
   • Potential Anticipation (35 U.S.C. § 102): This patent potentially anticipates Claim 1 of US7579227 due to its clear disclosure of the gate insulating film being thinner under the sidewalls than under the gate electrode. As a method patent, its description of forming such a structure also potentially anticipates Claim 9. Its filing date (2004-01-28) predates the priority date of US7579227.

3. US6902996B2

   • Full Citation: US6902996B2, "Method for fabricating semiconductor device"
   • Publication Date: 2005-06-07
   • Filing Date: 2004-01-28
   • Brief Description: This patent describes a method of fabricating a semiconductor device including forming a gate insulating film over a semiconductor substrate and a gate electrode over the film, then forming sidewalls. The gate insulating film is formed to have a non-uniform thickness, with the portion under the gate electrode being thicker than the portion under the sidewalls.
   • Potential Anticipation (35 U.S.C. § 102): Similar to the above, this patent potentially anticipates Claim 1 of US7579227 by describing the key structural feature of a gate insulating film with reduced thickness under the sidewalls. Its method-oriented claims and description also strongly suggest anticipation of Claim 9. Its filing date (2004-01-28) predates the priority date of US7579227.

4. US20040222475A1

   • Full Citation: US20040222475A1, "Semiconductor device and method of fabricating the same"
   • Publication Date: 2004-11-11
   • Filing Date: 2003-05-05
   • Brief Description: This patent application describes a semiconductor device comprising a gate electrode on a semiconductor substrate with a gate insulating film, and a side insulating film (sidewall) on a side surface of the gate electrode. The gate insulating film has a non-uniform thickness, where the portion directly under the gate electrode is thicker than the portion located between the side insulating film and the semiconductor substrate.
   • Potential Anticipation (35 U.S.C. § 102): This publication potentially anticipates Claim 1 of US7579227 due to its clear disclosure of a gate insulating film having a smaller thickness under the sidewall than under the gate electrode. Given its title and abstract, it also describes a method to achieve this structure, thereby potentially anticipating Claim 9. Its publication date (2004-11-11) and filing date (2003-05-05) both predate the priority date of US7579227.

These patents are highly relevant as prior art because their abstracts explicitly describe the core inventive concept of US7579227: a gate insulating film that is thinner under the sidewall than under the gate electrode, and methods for achieving this structure. The fact that they share the same original assignee further emphasizes their close relation and potential for anticipation.

Under 35 U.S.C. § 103, an invention is considered obvious if the differences between the claimed invention and the prior art are such that the subject matter as a whole would have been obvious at the time the invention was made to a person having ordinary skill in the art (PHOSITA). This analysis considers the scope and content of the prior art, the differences between the prior art and the claims, the level of ordinary skill in the art, and any secondary considerations of non-obviousness.

Prior Art References from US7579227

The patent US7579227 itself identifies and describes several pieces of prior art in its "Description of Prior Art" section and throughout the specification:

1. Ken Watanabe, HfSiON - CMOS technology for achieving high performance and high reliability, Semi. Forum Japan, 2005. This reference is explicitly cited as disclosing "known MISFETs using a high dielectric constant gate insulating film" and is illustrated in FIGS. 16A and 16B of US7579227.
   • Teachings (from US7579227's description of Watanabe):
     • FIG. 16A: A gate electrode 105 formed on an active region of a well 102 with a high dielectric constant gate insulating film 104 interposed. An insulating sidewall 107 is formed on each side of the gate electrode 105. An extension region 110 is under the sidewall 107, and source/drain regions 112 are external to the extension region.
     • FIG. 16B: Similar to FIG. 16A, but with an insulating offset sidewall 106 interposed between the gate electrode 105 and the sidewall 107, to optimize the overlapping amount between the gate electrode and an extension region.
   • Problems with Watanabe (as articulated by US7579227):
     • Side end portions of the high dielectric constant gate insulating film 104 are in direct contact with sidewalls (107 or 106/107), causing a reduction in the dielectric constant and insulation property of the high-k film at the gate electrode end, leading to deteriorated device characteristics and degraded reliability.
     • If the high dielectric constant gate insulating film 104 is kept remaining under the sidewalls, the capacitance between gate/drain regions increases, resulting in adverse effects on circuit speed.
     • Performing extension or LDD implantation through a thick high dielectric constant film (due to its material properties and required thickness) necessitates increased acceleration energy, leading to deeper junctions and suboptimal device characteristics.
2. T. Hori, IEDM Tech. Dig., 1989, p. 777. This reference is cited by US7579227 for the concept that a "high overlapping effect between a gate and a drain can be achieved" to improve device characteristics and hot carrier reliability.
3. H. Sayama et al., IEDM Tech. Dig., 2000, p. 239. This reference is cited by US7579227 in the context of "a double sidewall type MISFET in which an overlapping amount between a gate electrode and an extension region can be optimized in a simple manner".

Obviousness Analysis

The core invention of US7579227, as described in its Summary and Embodiments, aims to address the aforementioned problems by continuously forming the high dielectric constant gate insulating film from under the gate electrode to under the insulating sidewall, but with the critical modification that the part under the insulating sidewall has a smaller thickness than the part under the gate electrode.

A PHOSITA would be motivated to combine the teachings of the prior art and known semiconductor processing techniques to arrive at the claimed invention for the following reasons:

Combination 1: Watanabe (FIGS. 16A/B) + Motivation from known problems + General Semiconductor Engineering Principles

1. Primary Reference: Ken Watanabe, HfSiON - CMOS technology for achieving high performance and high reliability, Semi. Forum Japan, 2005 (as depicted in US7579227's FIGS. 16A and 16B).
   • Teachings: Watanabe discloses MISFETs with high-k gate insulating films (104) under a gate electrode (105) and extending under insulating sidewalls (107 or offset sidewall 106 and main sidewall 107). Extension regions (110) are located under these sidewalls.
   • Motivation to Modify: US7579227 explicitly identifies the problems inherent in the Watanabe structures:
     • Degradation of high-k film: The direct contact between the high-k film and sidewalls leads to degradation of dielectric constant and insulation properties. A PHOSITA would be motivated to prevent this by maintaining the continuity of the high-k film under the sidewall, thereby preventing direct contact of its side end portion with the bulk sidewall material.
     • Increased gate-drain capacitance: Merely extending a uniformly thick high-k film under the sidewall would increase parasitic capacitance and reduce circuit speed. A PHOSITA would recognize the well-known principle that reducing the thickness of a dielectric layer can decrease capacitance.
     • Difficulty with shallow junctions: The patent notes that implantation through a thick high-k film makes forming shallow junctions difficult due to increased acceleration energy requirements. A PHOSITA would understand that a thinner intervening layer would allow for lower implantation energies and consequently shallower junctions.
   • Obvious Solution: Given these clear problems, a PHOSITA would be motivated to combine the desire for high-k film continuity (to prevent degradation) with the necessity of reducing capacitance and facilitating shallow junctions. Selectively etching or thinning the portion of the high-k gate insulating film located under the sidewalls, while maintaining its continuity with the portion under the gate electrode, is a logical and straightforward engineering solution to address these recognized issues simultaneously. This directly addresses the main features of claim 1.

Obviousness of Additional Features:

• Buffer Insulating Film: The patent's fourth embodiment describes including a buffer insulating film (e.g., silicon oxide or silicon oxynitride) between the substrate and the high-k gate insulating film to improve the interface quality. The use of such buffer layers with high-k gate dielectrics was a well-established technique in semiconductor manufacturing prior to the priority date of US7579227, aimed at mitigating interface states and improving device performance and reliability. A PHOSITA would have been motivated to incorporate such a known buffer layer to enhance the device disclosed by Watanabe.
• Notch at a Side End Portion: The patent describes in its fifth embodiment that a "notch" can be formed if wet etching is used to remove part of the high dielectric constant gate insulating film. Wet etching processes, especially when performed selectively on certain materials, are known to create non-uniformities or notches at material edges. Thus, if a PHOSITA were to employ wet etching to achieve the desired thinning or removal of the high-k film, the formation of a notch would be an expected, if not inherent, outcome of a common fabrication process rather than an independent inventive feature.
• Fully Silicided (FUSI) Gate Electrode: The eighth embodiment of the patent details the fabrication of a fully silicided gate electrode. FUSI gate technology was known in the art prior to 2005/2006 as a method to reduce gate resistance and tune work functions, particularly in advanced CMOS devices employing high-k dielectrics. A PHOSITA, seeking to further optimize the performance of the MISFET structure (e.g., for speed or threshold voltage control), would have been motivated to combine the high-k/sidewall structure with a FUSI gate electrode, as these are complementary technologies for semiconductor device enhancement.

Conclusion on Obviousness

The combination of the known MISFET structures using high-k gate insulating films (as taught by Watanabe), coupled with the clear problems identified by US7579227 itself (degradation of high-k film, increased gate-drain capacitance, difficulty with shallow junctions), and the application of well-known semiconductor engineering principles (maintaining film integrity, thinning dielectrics to reduce capacitance and aid implantation, using buffer layers, employing FUSI gates), would have made the claimed invention obvious to a person having ordinary skill in the art at the time of invention. The patent effectively articulates the problems and then presents solutions that would be considered conventional responses within the skilled artisan's technical domain.

To fully detail patent term adjustments (PTA), patent term extensions (PTE), continuation/divisional applications, related family members, and the precise projected expiration date for US Patent 7579227, direct access to the USPTO's Patent Center or Public Patent Search system is typically required. While general information about these concepts is available, specific data for a given patent is held within its official file wrapper. The USPTO does not publicly calculate patent expiration dates directly, but provides tools and guidance for doing so.

Based on the available information and general patent law:

Patent Term Adjustments (PTA):
Patent Term Adjustment (PTA) is granted to utility and plant patents to compensate for certain delays by the USPTO during prosecution. These delays include failing to:

• Issue a first office action within 14 months of filing.
• Respond to an applicant's reply or appeal within four months.
• Act on an application within four months after a Patent Trial and Appeal Board (PTAB) or federal court decision.
• Issue a patent within four months after payment of the issue fee.
• Issue a patent within 36 months from the filing date (excluding applicant-caused delays).

The abstract of US7579227 indicates it is a utility patent, making it eligible for PTA. To determine the exact PTA for US7579227, one would need to review the "Issue Notification" sent by the USPTO, which includes the calculated adjustment. This information would be found in the patent's file history on Patent Center.

Patent Term Extensions (PTE):
Patent Term Extensions (PTE) are available for patents claiming certain human drug products, medical devices, animal drugs, or food/color additives to compensate for time lost during premarket regulatory review. Given that US7579227 pertains to a semiconductor device, it is highly unlikely to have received any Patent Term Extensions under 35 U.S.C. § 156, as these are typically related to regulatory approval processes for specific products.

Continuation and Divisional Applications:

• A continuation application is filed for an invention disclosed in a prior, co-pending non-provisional application, without introducing new subject matter.
• A divisional application is filed for a distinct and independent invention carved out of a prior, co-pending application.

The Google Patents page for US7579227 lists "US11/491,260" as the application number and "US20070032007A1" as "Other versions". The "Priority date" is 2005-08-05. The application number US11/491,260 corresponds to the original filing date of July 24, 2006.

The "Priority to US12/505,799" on 2009-07-20 and "Priority to US13/037,831" on 2011-03-01, and "Priority to US13/547,913" on 2012-07-12 suggest related applications, which could be continuations, divisionals, or continuations-in-part, claiming priority back to the original application associated with US7579227. To confirm the exact relationship (continuation, divisional, or continuation-in-part) and their impact on the patent family, the full file history of US7579227 and the listed priority applications would need to be examined on the USPTO's Patent Center.

Related Family Members:
The "Other versions" and "Priority to" information provided by Google Patents are strong indicators of related family members.

• US20070032007A1: This is likely the publication of the application that led to US7579227.
• US12/505,799, US13/037,831, US13/547,913: These are application numbers for patents that claim priority from an earlier application (potentially US7579227's underlying application or a common parent). Specifically, "Priority to US12/505,799" and "patent/US7923764B2/en" suggests that US12/505,799 resulted in US Patent 7,923,764. Similarly, "Priority to US13/037,831" and "patent/US8253180B2/en" points to US Patent 8,253,180. Lastly, "Priority to US13/547,913" and "patent/US8587076B2/en" indicates US Patent 8,587,076. These are likely continuations, divisionals, or continuations-in-part of the same patent family.

Projected Expiration Date:
The basic patent term for applications filed on or after June 8, 1995, is 20 years from the earliest filing date of the application or the earliest application in a chain of priority claims.

The "Filing date" of US7579227 is July 24, 2006. The "Priority date" is August 5, 2005. The "Prior art date" is also August 5, 2005. Since the patent claims priority to an earlier date (August 5, 2005), the 20-year term would typically be calculated from this earliest priority date.

Therefore, the nominal expiration date (without any adjustments or extensions) would be August 5, 2005 + 20 years = August 5, 2025.

However, the Google Patents information explicitly states the "Legal status" as "Active, expires 2027-03-27". This indicates that there has been a patent term adjustment (PTA). The difference between August 5, 2025, and March 27, 2027, is approximately 1 year and 7 months. This adjustment would be due to delays caused by the USPTO during the prosecution of the patent application.

Projected Expiration Date: March 27, 2027.

Defensive Disclosure: Derivative Works and Combination Prior Art for US Patent 7579227

As a Senior Patent Strategist and Research Engineer specializing in Defensive Publishing, this document outlines various derivative works and combination prior art scenarios based on US Patent 7579227, titled "Semiconductor device and method for fabricating the same." The objective is to create a robust body of publicly available prior art, rendering future incremental improvements by competitors "obvious" or "non-novel" by describing extensions, alternative implementations, and applications of the core inventive concepts. The analysis focuses on the Independent Device Claim 1 derived from the patent's "SUMMARY OF THE INVENTION."

Core Independent Device Claim 1 (Derived from Patent Summary)

A semiconductor device comprising:

• A high dielectric constant gate insulating film formed on an active region in a substrate.
• A gate electrode formed on the high dielectric constant gate insulating film.
• An insulating sidewall formed on each side surface of the gate electrode.
• The high dielectric constant gate insulating film is continuously formed so as to extend from under the gate electrode to under the insulating sidewall.
• At least part of the high dielectric constant gate insulating film located under the insulating sidewall has a smaller thickness than a thickness of part of the high dielectric constant gate insulating film located under the gate electrode.

---

Derivative Variations

1. Material & Component Substitution

Derivative 1.1: Metal Gate on a Strained SiGe Substrate with HfZrOx High-K Dielectric and SiOC Sidewalls

Enabling Description:
This derivative implements the core device structure on a strained silicon-germanium (SiGe) substrate to enhance carrier mobility within the active region. The high dielectric constant gate insulating film comprises an HfZrOx (Hafnium Zirconium Oxide) alloy, known for its higher dielectric constant (κ≈25-30) and improved thermal stability compared to HfSiON, deposited to a thickness of 4 nm under the gate electrode and anisotropically etched to 1.5 nm under the sidewalls. The gate electrode is a p-type work function metal, such as a stack of TiN/TaN, tailored for threshold voltage control. The insulating sidewall is formed from a low-k dielectric material, specifically silicon oxycarbide (SiOC) (κ≈2.5-3.0), deposited via plasma-enhanced chemical vapor deposition (PECVD) and etched back. This SiOC sidewall serves to further reduce parasitic capacitance compared to conventional SiN or SiO2, while maintaining the required mechanical support and isolation. A thin silicon oxynitride (SiON) buffer layer of 0.5 nm is included between the SiGe substrate and the HfZrOx film for interface quality.

graph TD
    subgraph Substrate: Strained SiGe
        S[Active Region]
    end
    direction TB
    S --> B(Buffer Insulating Film: SiON)
    B --> HK(High-K Gate Insulating Film: HfZrOx)
    HK -- Thinner region --> HW[Thinned HfZrOx under SiOC sidewall]
    HK -- Thick region --> GE(Gate Electrode: TiN/TaN)
    GE --- SW(Insulating Sidewall: SiOC)
    HW --- SW
    style S fill:#ffddcc,stroke:#333,stroke-width:2px
    style B fill:#e0f7fa,stroke:#333,stroke-width:1px
    style HK fill:#bbdefb,stroke:#333,stroke-width:1px
    style GE fill:#a7d9f9,stroke:#333,stroke-width:2px
    style SW fill:#c8e6c9,stroke:#333,stroke-width:1px
    style HW fill:#bbdefb,stroke:#333,stroke-width:1px,stroke-dasharray: 5 5

Derivative 1.2: All-Carbon MISFET with Graphene Gate, CNT Sidewalls, and BaTiO3 High-K Dielectric

Enabling Description:
This derivative explores a carbon-based semiconductor device utilizing a graphene sheet as the gate electrode due to its excellent conductivity and atomic thickness. The substrate is a silicon carbide (SiC) wafer with a doped active region. The high dielectric constant gate insulating film is barium titanate (BaTiO3) (κ≈100-200), a ferroelectric material, deposited by atomic layer deposition (ALD) to 6 nm under the graphene gate and etched to 2 nm under the sidewalls. Its ferroelectric properties allow for potential non-volatile memory applications if appropriately integrated. The insulating sidewalls are constructed from vertically aligned carbon nanotubes (CNTs) embedded in a low-k polymer matrix, providing structural integrity and high aspect ratio without significant parasitic capacitance. The CNTs offer enhanced thermal dissipation pathways away from the gate region. The continuity and reduced thickness of the BaTiO3 film under the CNT sidewalls follow the principles of US7579227 to maintain gate control and reduce parasitic effects.

graph TD
    subgraph Substrate: SiC
        A[Active Region]
    end
    direction TB
    A --> HK(High-K Gate Insulating Film: BaTiO3)
    HK -- Thinner region --> HW[Thinned BaTiO3 under CNT sidewall]
    HK -- Thick region --> GE(Gate Electrode: Graphene)
    GE --- SW(Insulating Sidewall: CNTs in Polymer)
    HW --- SW
    style A fill:#ffddcc,stroke:#333,stroke-width:2px
    style HK fill:#bbdefb,stroke:#333,stroke-width:1px
    style GE fill:#a7d9f9,stroke:#333,stroke-width:2px
    style SW fill:#c8e6c9,stroke:#333,stroke-width:1px
    style HW fill:#bbdefb,stroke:#333,stroke-width:1px,stroke-dasharray: 5 5

2. Operational Parameter Expansion

Derivative 2.1: Sub-10nm Gate Length FinFET for Cryogenic Quantum Computing Control

Enabling Description:
This derivative applies the patent's gate insulating film structure to a FinFET architecture designed for cryogenic operation (e.g., 4 Kelvin or millikelvin temperatures) in quantum computing control circuits. The substrate is a silicon-on-insulator (SOI) wafer, featuring silicon fins with gate lengths below 10 nm. The high dielectric constant gate insulating film is composed of HfO2, deposited via ALD to an effective oxide thickness (EOT) of 0.8 nm under the gate and etched to an EOT of 0.3 nm under the multi-layer SiN/SiO2 sidewalls. This extreme thinning under the sidewall minimizes quantum tunneling leakage at cryogenic temperatures while maintaining gate coupling. The gate electrode is a superconducting material, such as Niobium Nitride (NbN), to reduce resistance at operating temperatures. The insulating sidewalls are bilayer structures of thermal SiO2 (5 nm) and PECVD SiN (10 nm), optimized for low thermal conductivity to minimize heat transfer to the sensitive quantum environment.

graph TD
    subgraph FinFET Structure (Cryogenic)
        F[Si Fin]
    end
    direction TB
    F --> HK(High-K Gate Insulating Film: HfO2)
    HK -- Thinner region --> HW[Thinned HfO2 under Sidewall]
    HK -- Thick region --> GE(Gate Electrode: Superconducting NbN)
    GE --- SW(Insulating Sidewall: Bilayer SiO2/SiN)
    HW --- SW
    style F fill:#ffddcc,stroke:#333,stroke-width:2px
    style HK fill:#bbdefb,stroke:#333,stroke-width:1px
    style GE fill:#a7d9f9,stroke:#333,stroke-width:2px
    style SW fill:#c8e6c9,stroke:#333,stroke-width:1px
    style HW fill:#bbdefb,stroke:#333,stroke-width:1px,stroke-dasharray: 5 5

Derivative 2.2: High-Frequency (THz) RF Switch with Optimized Gate Overlap and Air-Gap Spacers

Enabling Description:
This derivative describes a high-frequency (e.g., terahertz, THz) radio-frequency (RF) switch utilizing the gate insulating film profile for precise gate-to-channel capacitance control. The active region is formed in a high-resistivity silicon substrate to minimize substrate losses at THz frequencies. The gate electrode is a platinum (Pt) gate to reduce resistance and improve high-frequency response. The high dielectric constant gate insulating film is a bilayer stack of Al2O3 (2 nm) and HfO2 (2 nm), providing a combined EOT of approximately 1 nm under the gate. This film is selectively etched to 0.5 nm under the inner offset sidewall, and then entirely removed from under the outer sidewall (which is an air-gap created by sacrificial layer etching). This precise thickness modulation and air-gap technique are critical for minimizing parasitic capacitance (Cgd, Cgs) at THz frequencies, which directly impacts switching speed and insertion loss. The offset sidewall itself is a thin SiN layer (5 nm) providing a self-aligned region. The overall design prioritizes minimal overlap capacitance for ultra-high-speed switching.

graph TD
    subgraph High-Frequency RF Switch
        S[High-Resistivity Si Substrate]
    end
    direction TB
    S --> HK(High-K Gate Insulating Film: Al2O3/HfO2 Stack)
    HK -- Thinner region --> HW1[Thinned HK under Offset Sidewall]
    HK -- Thick region --> GE(Gate Electrode: Platinum)
    GE --- OSW(Offset Sidewall: SiN)
    HW1 --- OSW
    OSW --- ASW(Air-Gap Sidewall)
    ASW --- HK_removed[HK Film Absent]
    style S fill:#ffddcc,stroke:#333,stroke-width:2px
    style HK fill:#bbdefb,stroke:#333,stroke-width:1px
    style GE fill:#a7d9f9,stroke:#333,stroke-width:2px
    style OSW fill:#c8e6c9,stroke:#333,stroke-width:1px
    style ASW fill:#e0e0e0,stroke:#333,stroke-width:1px
    style HW1 fill:#bbdefb,stroke:#333,stroke-width:1px,stroke-dasharray: 5 5
    style HK_removed fill:#ffffff,stroke:#333,stroke-width:1px,stroke-dasharray: 2 2

3. Cross-Domain Application

Derivative 3.1: Integrated MISFET-based Biosensor for Electrochemical Detection

Enabling Description:
This derivative adapts the MISFET structure into a biosensor for electrochemical detection of biomolecules, such as glucose or specific DNA sequences. The active region of the silicon substrate is functionalized with a biorecognition layer (e.g., enzyme, antibody, aptamer). The high dielectric constant gate insulating film, here a Ta2O5 (Tantalum Pentoxide) (κ≈25) layer, acts as the sensing membrane, deposited at a uniform thickness of 5 nm under a platinum (Pt) gate electrode. Under the insulating sidewalls (made of biocompatible parylene), the Ta2O5 film is locally thinned to 2 nm, creating a region of differential electric field sensitivity. This thinning enhances the local electric field and charge sensitivity at the gate edge, optimizing the transduction of biochemical binding events into electrical signals. The gate electrode is typically a pseudo-reference electrode or directly senses the potential change due to molecular binding. This structure allows for improved sensitivity and reduced interference from bulk solution effects.

graph TD
    subgraph Biosensor Device
        S[Si Substrate]
    end
    direction TB
    S --> AR(Active Region with Biorecognition Layer)
    AR --> HK(High-K Sensing Film: Ta2O5)
    HK -- Thinner region --> HW[Thinned Ta2O5 under Sidewall]
    HK -- Thick region --> GE(Gate Electrode: Platinum)
    GE --- SW(Insulating Sidewall: Parylene)
    HW --- SW
    style S fill:#ffddcc,stroke:#333,stroke-width:2px
    style AR fill:#fff2e0,stroke:#333,stroke-width:1px
    style HK fill:#bbdefb,stroke:#333,stroke-width:1px
    style GE fill:#a7d9f9,stroke:#333,stroke-width:2px
    style SW fill:#c8e6c9,stroke:#333,stroke-width:1px
    style HW fill:#bbdefb,stroke:#333,stroke-width:1px,stroke-dasharray: 5 5

Derivative 3.2: Radiation-Hardened Power MISFET for Deep Space Applications

Enabling Description:
This derivative describes a radiation-hardened power MISFET suitable for deep space and high-radiation environments, where robustness against single-event upsets (SEUs) and total ionizing dose (TID) effects is critical. The device is built on a silicon carbide (SiC) substrate for its inherent radiation tolerance and high power handling capabilities. The gate electrode is a refractory metal such as Tungsten (W). The high dielectric constant gate insulating film is a HfAlO (Hafnium Aluminum Oxide) composite (κ≈18-25) deposited by ALD to a uniform thickness of 10 nm under the gate. Under the radiation-hardened insulating sidewalls (e.g., boron-doped SiO2), the HfAlO film is intentionally thinned to 5 nm. This graded thickness helps in mitigating charge trapping at the gate edges and interface states induced by radiation, while the thicker portion under the main gate provides a higher breakdown voltage. The reduced thickness under the sidewall allows for efficient charge recombination paths at the edges, preventing localized field enhancement under radiation exposure. The design incorporates a thick field oxide (FOX) to further isolate the device from radiation-induced leakage paths.

graph TD
    subgraph Radiation-Hardened Power MISFET
        S[SiC Substrate]
    end
    direction TB
    S --> HK(High-K Gate Insulating Film: HfAlO)
    HK -- Thinner region --> HW[Thinned HfAlO under Rad-Hard Sidewall]
    HK -- Thick region --> GE(Gate Electrode: Tungsten)
    GE --- SW(Insulating Sidewall: Boron-Doped SiO2)
    HW --- SW
    style S fill:#ffddcc,stroke:#333,stroke-width:2px
    style HK fill:#bbdefb,stroke:#333,stroke-width:1px
    style GE fill:#a7d9f9,stroke:#333,stroke-width:2px
    style SW fill:#c8e6c9,stroke:#333,stroke-width:1px
    style HW fill:#bbdefb,stroke:#333,stroke-width:1px,stroke-dasharray: 5 5

4. Integration with Emerging Tech

Derivative 4.1: AI-Optimized Adaptive Gate Profile MISFET with Real-Time Monitoring

Enabling Description:
This derivative describes a semiconductor device where the gate insulating film profile is dynamically optimized during fabrication and potentially during operation using AI. The fabrication process includes in-situ metrology (e.g., spectroscopic ellipsometry, atomic force microscopy) linked to an AI-driven process control system. This system analyzes real-time data to adapt etching parameters for the high-k film, ensuring the desired thickness reduction under the sidewall (e.g., from 4 nm under the gate to a precisely controlled 1-2 nm under the sidewall) is achieved with minimal variation across the wafer. For operational optimization, embedded IoT sensors within the device monitor parameters like leakage current, threshold voltage shifts, and hot carrier degradation. An on-chip AI module uses this data to predict remaining device lifetime and adjust operating conditions (e.g., bias voltages, clock frequencies) for optimal performance and reliability over time. The gate electrode itself could be a flexible, tunable work function metal.

graph TD
    subgraph AI-Optimized Adaptive MISFET
        S[Substrate]
    end
    direction TB
    S --> HK(High-K Gate Insulating Film: Tunable Profile)
    HK -- AI-controlled etching --> HW[Adaptive Thinned HK under Sidewall]
    HK -- AI-controlled deposition --> GE(Gate Electrode: Tunable Work Function Metal)
    GE --- SW(Insulating Sidewall)
    HW --- SW
    IoT[IoT Sensors] --> AI(On-Chip AI Optimization)
    AI --> HK
    AI --> GE
    style S fill:#ffddcc,stroke:#333,stroke-width:2px
    style HK fill:#bbdefb,stroke:#333,stroke-width:1px
    style GE fill:#a7d9f9,stroke:#333,stroke-width:2px
    style SW fill:#c8e6c9,stroke:#333,stroke-width:1px
    style HW fill:#bbdefb,stroke:#333,stroke-width:1px,stroke-dasharray: 5 5
    style IoT fill:#ffe0b2,stroke:#333,stroke-width:1px
    style AI fill:#c5e1a5,stroke:#333,stroke-width:2px

Derivative 4.2: IoT-Enabled Power Management Unit (PMU) with Secure Device Identity

Enabling Description:
This derivative describes a power management unit (PMU) integrated circuit for IoT edge devices, where individual MISFETs incorporate the specified gate insulating film structure. Each PMU chip includes embedded unique physical unclonable functions (PUFs) derived from process variations in the MISFETs themselves, specifically related to the precise thickness control of the high-k dielectric under the sidewalls. This PUF generates a unique, unclonable device identity. This identity is cryptographically signed and stored on a distributed ledger (blockchain) for secure supply chain verification and device authentication in IoT networks. The gate insulating film, such as HfSiON, is formed with a nominal thickness of 3 nm under the gate and 1.5 nm under the SiN sidewalls. Minor, unavoidable variations in this etching process create the entropy for the PUF, which is then extracted and used for cryptographic keys. The blockchain ledger records the manufacturing batch, test results, and transfer of ownership, verifying the authenticity of each PMU throughout its lifecycle.

graph TD
    subgraph IoT PMU with Secure ID
        S[Si Substrate]
    end
    direction TB
    S --> HK(High-K Gate Insulating Film: HfSiON)
    HK -- Thinner region --> HW[Thinned HfSiON under Sidewall (PUF Feature)]
    HK -- Thick region --> GE(Gate Electrode)
    GE --- SW(Insulating Sidewall: SiN)
    HW --- SW
    HK_Var[HK Thickness Variation] --> PUF(Physical Unclonable Function)
    PUF --> DI(Device Identity)
    DI --> B(Blockchain Ledger: Secure Supply Chain)
    style S fill:#ffddcc,stroke:#333,stroke-width:2px
    style HK fill:#bbdefb,stroke:#333,stroke-width:1px
    style GE fill:#a7d9f9,stroke:#333,stroke-width:2px
    style SW fill:#c8e6c9,stroke:#333,stroke-width:1px
    style HW fill:#bbdefb,stroke:#333,stroke-width:1px,stroke-dasharray: 5 5
    style HK_Var fill:#fff2e0,stroke:#333,stroke-width:1px
    style PUF fill:#c5e1a5,stroke:#333,stroke-width:1px
    style DI fill:#a7d9f9,stroke:#333,stroke-width:1px
    style B fill:#ffe0b2,stroke:#333,stroke-width:2px

5. The "Inverse" or Failure Mode

Derivative 5.1: Self-Healing MISFET with Embedded Microcapsules for Gate Insulator Repair

Enabling Description:
This derivative describes a self-healing MISFET where the high dielectric constant gate insulating film is engineered with embedded microcapsules containing a dielectric healing agent (e.g., a liquid precursor to SiO2 or a low-k polymer). Upon detection of a localized breakdown or excessive leakage current (indicating a defect in the high-k film, e.g., HfO2, initially 4 nm under the gate and 1.5 nm under the sidewall), the microcapsules rupture, releasing the healing agent which then solidifies to repair the defect. This allows the device to operate in a "graceful degradation" mode rather than catastrophic failure. The insulating sidewalls, composed of a flexible polymer, accommodate slight volume changes during the healing process. The thinning of the high-k film under the sidewall is maintained for performance, but the healing agent provides an additional layer of reliability, selectively applied to areas prone to stress. This enables a low-power, reduced performance state following a repair, extending operational life.

graph TD
    subgraph Self-Healing MISFET
        S[Substrate]
    end
    direction TB
    S --> HK(High-K Gate Insulating Film: HfO2 with Microcapsules)
    HK -- Thinner region --> HW[Thinned HfO2 under Sidewall]
    HK -- Thick region --> GE(Gate Electrode)
    GE --- SW(Insulating Sidewall: Flexible Polymer)
    HW --- SW
    Detect[Leakage/Defect Detection] --> Rupture(Microcapsule Rupture)
    Rupture --> Release(Healing Agent Release)
    Release --> Repair(Dielectric Repair/Solidification)
    Repair --> Operate(Continue Operation - Graceful Degradation)
    style S fill:#ffddcc,stroke:#333,stroke-width:2px
    style HK fill:#bbdefb,stroke:#333,stroke-width:1px
    style GE fill:#a7d9f9,stroke:#333,stroke-width:2px
    style SW fill:#c8e6c9,stroke:#333,stroke-width:1px
    style HW fill:#bbdefb,stroke:#333,stroke-width:1px,stroke-dasharray: 5 5
    style Detect fill:#ffcdd2,stroke:#333,stroke-width:1px
    style Rupture fill:#ffcc80,stroke:#333,stroke-width:1px
    style Release fill:#ffe0b2,stroke:#333,stroke-width:1px
    style Repair fill:#c5e1a5,stroke:#333,stroke-width:1px
    style Operate fill:#a7d9f9,stroke:#333,stroke-width:2px

Derivative 5.2: Leakage-Controlled MISFET with Electrically Tunable High-K Film for Low-Power Mode

Enabling Description:
This derivative focuses on minimizing leakage currents during "low-power" or "sleep" modes, crucial for battery-operated devices. The high dielectric constant gate insulating film is implemented using a compositionally graded ferroelectric or high-k material, such as HfZrO (Hafnium Zirconium Oxide) with a controlled oxygen vacancy concentration, which allows for electrical tuning of its effective dielectric constant (κ) and band alignment. Under the gate, the HfZrO is 5 nm thick, and under the SiN sidewall, it's 2 nm thick. In normal operation, the film exhibits its full high-κ behavior. In low-power mode, a reverse bias or specific gate voltage (e.g., negative for n-MISFET) is applied to an auxiliary electrode (not shown, but adjacent to the gate or within the sidewall) that locally modifies the electric field across the thinned high-k region under the sidewall. This electric field induces a phase transition or reorientation of dipoles within the HfZrO, effectively increasing the physical band gap or barrier height, thereby reducing gate leakage and subthreshold leakage currents. This temporary increase in effective insulation resistance at the gate edges enables deep sleep states with minimal power consumption, while sacrificing switching speed.

graph TD
    subgraph Leakage-Controlled Low-Power MISFET
        S[Substrate]
    end
    direction TB
    S --> HK(High-K Gate Insulating Film: Tunable HfZrO)
    HK -- Thinner region --> HW[Thinned Tunable HfZrO under Sidewall]
    HK -- Thick region --> GE(Gate Electrode)
    GE --- SW(Insulating Sidewall: SiN)
    HW --- SW
    V_LP[Low-Power Mode Voltage] --> T(Tuning Mechanism: Field-induced property change)
    T --> HK
    T --> HW
    T --> REDUCE_LEAK(Reduced Gate/Subthreshold Leakage)
    style S fill:#ffddcc,stroke:#333,stroke-width:2px
    style HK fill:#bbdefb,stroke:#333,stroke-width:1px
    style GE fill:#a7d9f9,stroke:#333,stroke-width:2px
    style SW fill:#c8e6c9,stroke:#333,stroke-width:1px
    style HW fill:#bbdefb,stroke:#333,stroke-width:1px,stroke-dasharray: 5 5
    style V_LP fill:#ffcdd2,stroke:#333,stroke-width:1px
    style T fill:#c5e1a5,stroke:#333,stroke-width:1px
    style REDUCE_LEAK fill:#a7d9f9,stroke:#333,stroke-width:2px

---

Combination Prior Art Scenarios

These scenarios combine the inventive concepts of US7579227 with existing open-source standards, thereby demonstrating obviousness or lack of novelty for future incremental advancements.

1. RISC-V Microcontroller Unit (MCU) with Enhanced MISFETs

Combination: US7579227 + RISC-V Instruction Set Architecture (ISA)

Enabling Description:
A microcontroller unit (MCU) implementing the open-source RISC-V instruction set architecture for its processing core, where the individual MISFETs within the core logic, memory interfaces, and peripheral control units are fabricated using the gate insulating film structure described in US7579227. Specifically, the high dielectric constant gate insulating film (e.g., HfSiON) under the polysilicon or metal gate electrode is formed to be 3 nm thick, and continuously extends under the silicon nitride (SiN) sidewalls where its thickness is reduced to 1.5 nm. This integration is crucial for achieving high performance, low power consumption, and improved reliability for embedded RISC-V applications. The reduced thickness under the sidewall minimizes parasitic capacitance, allowing for higher clock frequencies, while maintaining gate coupling for efficient switching and hot carrier reliability, which directly benefits the speed and energy efficiency benchmarks of RISC-V processors. Fabrication would involve standard CMOS processes adapted to include selective wet or dry etching of the high-k dielectric before sidewall formation, as outlined in the methods of US7579227.

graph TD
    subgraph RISC-V MCU Architecture
        RV_CORE[RISC-V CPU Core]
        MEM[Memory Interface]
        PERIPH[Peripherals]
        IO[I/O Subsystem]
    end
    direction LR
    RV_CORE -- Contains --> MISFET_US[MISFETs (per US7579227)]
    MEM -- Contains --> MISFET_US
    PERIPH -- Contains --> MISFET_US
    IO -- Contains --> MISFET_US
    RISC_V_STD(RISC-V ISA Standard) --> RV_CORE
    MISFET_US --> PERF(Improved Performance/Reliability)
    PERF --> RV_CORE
    style RV_CORE fill:#bbdefb,stroke:#333,stroke-width:2px
    style MEM fill:#e0f7fa,stroke:#333,stroke-width:1px
    style PERIPH fill:#ffe0b2,stroke:#333,stroke-width:1px
    style IO fill:#c8e6c9,stroke:#333,stroke-width:1px
    style MISFET_US fill:#a7d9f9,stroke:#333,stroke-width:2px
    style RISC_V_STD fill:#ffddcc,stroke:#333,stroke-width:2px
    style PERF fill:#c5e1a5,stroke:#333,stroke-width:1px

2. Open Compute Project (OCP) Server Hardware with High-Reliability PMICs

Combination: US7579227 + Open Compute Project (OCP) Hardware Designs

Enabling Description:
A Power Management Integrated Circuit (PMIC) designed for server motherboards conforming to the Open Compute Project (OCP) specifications, where the switching regulators and control logic within the PMIC utilize MISFETs fabricated with the gate insulating film characteristics of US7579227. In these OCP-compliant PMICs, the high dielectric constant gate insulating film (e.g., ZrO2) under the metal gate (e.g., TiN) is 5 nm thick, and it tapers down to 2 nm under the inner insulating sidewall (e.g., SiO2), with a subsequent SiN outer sidewall. This specific gate stack and sidewall configuration minimizes gate leakage and improves the switching efficiency and hot carrier reliability of the power transistors. For OCP hardware, reliability and power efficiency are paramount. The continuous, thinned high-k film under the sidewalls reduces parasitic capacitance and enhances gate control, directly translating to higher power conversion efficiency and extended operational lifespan for OCP-specified server components. This design contributes to the overall reduction in total cost of ownership (TCO) for data centers, a key tenet of OCP.

graph TD
    subgraph OCP Server Board PMIC
        OCP_SERVER[OCP Server Motherboard]
        PMIC_OCP[OCP-Compliant PMIC]
        CPU_MEM[CPU/Memory Modules]
    end
    direction LR
    OCP_SERVER -- Integrates --> PMIC_OCP
    PMIC_OCP -- Powers --> CPU_MEM
    PMIC_OCP -- Contains --> MISFET_US[MISFETs (per US7579227)]
    OCP_STD(OCP Hardware Design Standard) --> OCP_SERVER
    MISFET_US --> EFF(High Efficiency/Reliability)
    EFF --> PMIC_OCP
    style OCP_SERVER fill:#bbdefb,stroke:#333,stroke-width:2px
    style PMIC_OCP fill:#a7d9f9,stroke:#333,stroke-width:2px
    style CPU_MEM fill:#e0f7fa,stroke:#333,stroke-width:1px
    style MISFET_US fill:#c8e6c9,stroke:#333,stroke-width:1px
    style OCP_STD fill:#ffddcc,stroke:#333,stroke-width:2px
    style EFF fill:#c5e1a5,stroke:#333,stroke-width:1px

3. Semiconductor Fabrication Plant Automation with OPC UA for Gate Insulator Process Control

Combination: US7579227 (Method Claim) + OPC UA (Open Platform Communications Unified Architecture)

Enabling Description:
A semiconductor fabrication process for manufacturing MISFETs according to the method of US7579227, where the process steps are monitored and controlled through an automation system compliant with the OPC Unified Architecture (OPC UA) open-source standard. Specifically, the etching step (c) – where part of the high dielectric constant gate insulating film external to the gate electrode is reduced in thickness (e.g., from 4 nm HfSiON to 1.5 nm) – is managed by an OPC UA server. This server provides a standardized interface for real-time data acquisition from metrology tools (e.g., in-situ ellipsometers measuring film thickness) and for sending control commands to etching equipment (e.g., adjusting etch duration or gas flow rates). The OPC UA client applications, residing on supervisory control systems, enable precise and consistent control over the gate insulator profile and sidewall formation. This ensures reproducibility of the thinned high-k region, critical for device performance, and enhances the overall efficiency and data integrity of the fabrication line, adhering to the principles of Industry 4.0 and smart manufacturing as enabled by OPC UA.

graph TD
    subgraph Fab Automation with OPC UA
        METRO[Metrology Tools (e.g., Ellipsometer)]
        ETCH_TOOL[Etching Equipment]
        OPC_SERVER[OPC UA Server (Process Control)]
        SUPER_CTRL[Supervisory Control System (OPC UA Client)]
    end
    direction LR
    METRO -- Real-time Data --> OPC_SERVER
    OPC_SERVER -- Control Commands --> ETCH_TOOL
    SUPER_CTRL -- Monitors/Commands --> OPC_SERVER
    ETCH_TOOL -- Executes Step (c) --> MISFET_FAB[MISFET Fabrication (per US7579227 Method)]
    OPC_UA_STD(OPC UA Standard) --> OPC_SERVER
    MISFET_FAB --> QUALITY(Consistent Gate Insulator Profile)
    QUALITY --> HI_PERF(High Performance MISFETs)
    style METRO fill:#ffe0b2,stroke:#333,stroke-width:1px
    style ETCH_TOOL fill:#e0f7fa,stroke:#333,stroke-width:1px
    style OPC_SERVER fill:#c5e1a5,stroke:#333,stroke-width:2px
    style SUPER_CTRL fill:#bbdefb,stroke:#333,stroke-width:2px
    style MISFET_FAB fill:#a7d9f9,stroke:#333,stroke-width:1px
    style OPC_UA_STD fill:#ffddcc,stroke:#333,stroke-width:2px
    style QUALITY fill:#c8e6c9,stroke:#333,stroke-width:1px
    style HI_PERF fill:#a7d9f9,stroke:#333,stroke-width:2px